Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

Cole Zemke
IBM czemke@us.ibm.com

Jitendra Lagu
Synopsys Professional Services, Synopsys Inc lagu@synopsys.com Kevin Brelsford WWAS, Synopsys Inc Kevin.Brelsford@synopsys.com

ABSTRACT Layout parasitic extraction is a critical phase of todays design flows. Smaller geometries require RC extraction tools which will accurately predict delays during simulation and timing analysis. Parasitic effects are becoming more prominent as gate geometries shrink to below 90 nm. The IBM Parasitic Extraction team at Essex Junction, Vermont is working closely with the Synopsys Professional Services team to develop and test technology files to enable the layout parasitic extraction of advanced processes for foundry customers. The purpose of this paper is to conduct a numerical analysis of various parasitic effects and to show how interconnect delay issues are magnified with shrinking process geometries.

Table of Contents
1.0. Introduction ............................................................................................................................3 2.0 Double Counting of Gate Capacitance .................................................................................3 3.0 Well Proximity Effect .............................................................................................................6 4.0 STI Stress Effect .....................................................................................................................8 5.0 Metal Fill and its Influence on Capacitance.........................................................................8 6.0 Parasitic Effects of Metal Cheesing.....................................................................................13 7.0 Conclusions and Recommendations....................................................................................15 8.0 Acknowledgement.................................................................................................................15 9.0 References..............................................................................................................................16

Table of Figures
Figure 2.1 Breakup of polysilicon during LVS extraction .........................................................4 Figure 2.2 XTR view of NMOS and PMOS transistors .............................................................5 Figure 3.1 Implantation of n-type dopant to create an n-well ...................................................6 Figure 3.2 Scattering of ions from photoresist into n-well and substrate.................................6 Figure 3.3 Example of device positions relative to well edges....................................................7 Figure 4.1 Si02 and n+ diffusion junction ....................................................................................8 Figure 5.1 Process without metal fill ............................................................................................9 Figure 5.2 Process with metal fill..................................................................................................9 Figure 5.3 Simulation flow for comparison of results with and without fill emulation.........11 Figure 5.4 Percent increase in capacitance due to fill emulation ............................................12 Figure 5.5 Increase in capacitance due to fill emulation ..........................................................12 Figure 6.1 Dishing to the left and cheesing to the right.......................................................13 Figure 6.2 Resistance vs. width with cheesing (true R) and without cheesing (ideal R) .......13 Figure 6.3 Testcase.......................................................................................................................14 Figure 6.4 Capacitive coupling vs. hole dimension for 25% hole density...............................15

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

1.0 Introduction
Accurate layout parasitic extraction is one of the most important requirements in todays design flows. With the minimum gate sizes approaching 65 nm and below, in addition to resistive, capacitive, and inductive effects, extraction tools are also required to provide data required by simulation tools to model physical effects which were not required by previous transistor models, such as proximity and stress effects. Such data is vital since these effects can alter device characteristics. The Parasitic Extraction team at Essex Junction, VT is working closely with Synopsys Professional Services to provide design kits for many technologies which allow our customers to perform parasitic extraction successfully. For example, Synopsys has provided the ability to encrypt nxtgrd files, for 90 nm and 65 nm technologies which allows IBM to provide nxtgrds created with detailed dielectric information to our customers without compromising process confidentiality. In this paper we discuss several features which are of paramount importance to accurate extraction and device modeling at deep sub-micron technologies. Using IBMs technologies, we have attempted to show how various parasitic components occur and how they can impact timing and other performance criteria. A gate capacitance double counting problem is discussed, and some simple solutions are provided to eliminate this double counting. STI stress parameters and well proximity effect also alter the characteristics of MOS devices. Synopsys Hercules LVS and Star-RCXT tools have enabled IBM to incorporate these effects into design kits. Metal fill can induce parasitic capacitive effects. We, with the enablement of fill emulation in Star-RCXT, have been able to provide our customers the means to model this effect in a relatively simple manner. Metal cheesing produces both parasitic resistive and capacitive effects. Currently, the resistive effect is accounted for in our Star-RCXT enablement.

2.0 Double Counting of Gate Capacitance

Double-counting of gate capacitance is an inadvertent error that can cause large errors in circuit simulations. Double-counting refers to the inclusion of a capacitance both in the parasitic netlist and in the device model. There are several components of gate capacitance, namely: 1) 2) 3) 4) Gate to substrate capacitance Gate to diffusion capacitance Gate to metal capacitance Gate to POLY (polysilicon for routing and gates) lateral capacitance (if applicable)

As illustrated in Figure 2.1, the poly routing normally ends up connecting to a gate terminal, where it may terminate or continue. A gate is formed when poly is placed over diffusion layers. The total POLY capacitance will now have 2 components, one from the routing and one from the gate. The gate component, however, is usually accounted for in MOSFET models. Hence it is required to exclude the parasitic extraction of the gate capacitance, since this capacitance is already accounted for in the MOSFET model. Therefore, POLY must be excluded from gate layers, as shown in the following example (layer names are not related to IBMs actual runset names and are fictitious).
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BOOLEAN nmos_gate OR pmos_gate OR other_gate TEMP = all_the_gates BOOLEAN poly NOT all_the_gates TEMP = poly

Routing POLY

GATE Diffusion

Routing POLY

Substrate

Accounted for in device models Figure 2.1 Breakup of polysilicon during LVS extraction

The effect of gate capacitance double counting can be clearly seen for the devices shown in Figure 2.2 (not to scale) where an XTR view of an NMOS transistor and a PMOS transistor is shown. With double counting the POLY routing shows a total capacitance of 6.29 fF for the PMOS transistor and 6.28 fF for the NMOS transistor. After double counting is eliminated, the extracted parasitic capacitance for POLY routing for the PMOS as well as the NMOS transistor drops down to 0.772 fF. It should be noted that these devices are non-minimum size devices. The effect of gate double counting will be more noticeable for larger devices as compared to smaller devices. This is because larger devices will tend to have higher capacitance values due to a larger gate area. Also nets which connect to multi-finger devices will be greatly affected. Based on a real PLL circuit designed using IBMs 90 nm technology, whose details are provided later in the metal fill section, we have tabulated the change in capacitance values on certain nets which have poly routing and include transistor gate regions. It should be noted that the nets may have both NMOS and PMOS device gates connected to their POLY layer. Multifinger devices show a larger variation as expected. The net names in table 2.1 have been changed to maintain data confidentiality. Also, the results provided here are for devices having nonminimum gate sizes.

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

Net Name

NET7 NET6 NET3 NET8 NET1 NET10 NET9 NET5 NET2 NET4

Value without Absolute % capacitance double Difference Difference counting (fF) 62.8763 47.747 15.1293 24.04 57.6062 32.3141 25.2921 43.90 26.214 11.5483 14.6657 55.94 24.9326 10.9013 14.0313 56.27 72.4525 16.9376 55.5149 76.62 13.7669 2.9274 10.8395 78.73 24.34 4.70676 19.63324 80.66 7.28931 1.23543 60.5388 83.05 50.3345 7.81984 42.5146 84.46 25.1663 3.29555 21.87075 86.90 Table 2.1 Differences in poly capacitances extracted with and without gate capacitances

Value with capacitance double counting (fF)

The % Difference column is computed as a ratio between absolute capacitance difference and net capacitance value with double counting. This ratio is multiplied by 100 to give a percent value. It can be seen from the table that differences in capacitance are significant. This in turn can have a profound effect on the timing of the overall circuit. The effect of double counting gate capacitance can be problematic in any size process geometry. However, the methods described previously in creating the Hercules LVS and StarRCXT mapping file must be followed more and more strictly as process geometries shrink. Even small capacitances can have an effect on circuit performance, and developers must work to ensure that no capacitances (and resistances and inductances) included in the device model are extracted in parasitic extraction.

Figure 2.2 XTR view of NMOS and PMOS transistors

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

3.0 Well Proximity Effect

Retrograde well implants, while beneficial to CMOS technologies for many reasons, cause ion scattering that can alter the threshold voltage of devices near well edges. [1] Take for example the creation of an n-well. Figure 3.1 shows the implantation of n-type dopant into a ptype substrate to create an n-well. The well edge is defined by the edges of the photoresist.

n+

n+

n+

n+

n+

n+

n+

n+

n+

n+

Photoresist

Photoresist

p- Substrate
Figure 3.1 Implantation of n-type dopant to create an n-well

However, ions scattered from just inside the photoresist can escape the photoresist and change the doping of the n-well and substrate near the mask edge. Figure 3.2 shows this effect.

n+

n+

n+

n+

n+

Photoresist

n- NWELL

p- Substrate
Figure 3.2 Scattering of ions from photoresist into n-well and substrate

A more detailed explanation of the well proximity effect, in terms of p-well, n-well, and triple well representations, is given in [1]. For simulation, this effect can be taken into account within
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device models. However, as [1] states, for each individual device the impact of this effect depends on the overall width of the device, the location of the device relative to the mask edge, the lateral range of the effect, and the density and depth of the scattered ions relative to those intentionally implanted in the region. Figure 3.3 shows devices in different positions relative to well edges. Each devices threshold voltage will be impacted differently by well proximity effects.

nmos1 pmos1

nmos2

pmos2

n-well

Figure 3.3 Example of device positions relative to well edges

nmos2 is much closer to the n-well edge than nmos1, and will experience much more threshold voltage variation. Likewise, pmos1 is very close to two n-well edges, and will be affected much more dramatically by the well proximity effect than pmos2. The device model itself cannot determine the width of the device and the devices position relative to well edges. The LVS extraction must provide this information to the model in the form of MOS device properties within the final parasitic netlist. While the device width is a typical product of LVS extraction, information on the devices position relative to well edges are not. IBM and Synopsys Professional Services have worked together to implement an algorithm to extract this information. While the algorithm was originally implemented in Scheme, beginning from Hercules version 2003.12, it is possible to extract this information through the Hercules runset without the need for Scheme code. The details of this algorithm are proprietary and will not be discussed in this paper. Obviously the effect worsens in shrinking process geometries as feature sizes decrease and smaller active regions reside closer to well edges. A demonstration of the severity of the well proximity effect is not covered for this paper. However, it should be noted that this effect is not negligible. For instance, the transition times of an inverter used in the IBM Star-RCXT verification flow, simulated in a 90 nm technology but

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

not at minimum dimensions, changes approximately 4% when well proximity is taken into account.

4.0 STI Stress Effect

Another parasitic effect that directly affects device characteristics is the stress induced by shallow trench isolation (STI). Physically, this effect is the lateral mechanical stress induced by the STI on the device active area (i.e. the differing mechanical properties between Si and Si02). Figure 4.1 displays the junction in question. Much literature is available that discusses this effect in more detail, including [2].
Junction between STI and device active area

SiO2 (Shallow Trench Isolation)

n+ diffusion ( MOSFET source or drain) p- Substrate

Figure 4.1 Si02 and n+ diffusion junction

Device simulation models, such as BSIM4.3 MOSFET models, require certain geometric parameters in order to model this effect. [3] Basically these parameters describe the distance from the channel region to isolation, with some intricacies. Much like the well proximity effect, the distance from the channel region to isolation changes per device hence these geometric parameters must be extracted from the layout, in this case by Hercules LVS extraction. Synopsys Professional Services and IBM have teamed to develop algorithms to derive these parameters to allow for accurate modeling of this effect. Again, the details of this algorithm are proprietary and will not be discussed in this paper. As with the well proximity effect, the effects from STI stress on device characteristics worsen as process geometries shrink and the distance from channel region to isolation lessens. As for well proximity effects, a demonstration of the severity of the STI stress effect is not covered for this paper. Again, it should be noted that this effect is not negligible. For the same inverter simulated for well proximity effects, the transition time (for the high to low output transition) changes approximately 6% when STI stress is taken into account.

5.0 Metal fill and its Influence on Capacitance

Metal fill usage is a common process requirement for manufacturing todays ICs. Chemical mechanical polishing (CMP) has been used in recent years to planarize interlayer dielectrics. CMP processes are sensitive to layout patterns, and this can cause certain regions on chip to have thicker dielectric layers than other areas due to differences in the underlying
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topography. Under such circumstances, metal fill has been found to be one of the most commercially viable options in reducing layout dependent dielectric thickness variation. Metal-fill patterning is the process of filling large open areas on each metal layer with a metal pattern that is either grounded or left floating, to compensate for pattern-driven variations. [4] Figure 5.1 shows the cross-section of a process without metal fill. As is shown, the Metal 2 above empty areas of Metal 1 will cause a significant drop in the profile of Dielectric 2. As seen in Figure 5.2, inserting Metal 1 in the empty spaces can help maintain the ideally required cross sectional profile.

Figure 5.1 Process without metal fill (Courtesy: Star-RCXT Corporate Applications Engineering)

Figure 5.2 Process with metal fill (Courtesy: Star-RCXT Corporate Applications Engineering)

Metal fill can be either grounded or floating. Foundries use automatic metal fill algorithms to insert dummy fills in the design such that fill is inserted in areas where metal is sparsely distributed. These algorithms create metal fill based on horizontal metal spacing and other criteria. Generally these algorithms are proprietary in nature. Physical verification tools such as Hercules can be effectively used in inserting such dummy metal fills based on certain criteria.
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As will be seen later, metal fill most certainly adds parasitic capacitance. It is important to enable designers with a realistic estimate of the parasitic capacitance caused by metal fill insertion. Synopsys Star-RCXT has provided a means of achieving this. The Star-RCXT Interconnect Technology File (ITF) can be used to model the effect of real fill without actually inserting fill into the design. This fill is called emulated fill since it emulates the effect of fill polygons. In certain design flows, using real fill in the earlier stages of the design cycle can be time consuming. Moreover, the fill algorithm must be run on the gds file each and every time a small change is made to the design. The gds file then has to be re-run through Hercules LVS and Star-RCXT. Emulated fill eliminates the need to go through these steps and provides an accurate estimate of the fill effect. Star-RCXT metal fill emulation is designed to estimate the capacitive effect of small, floating fill shapes within the routed core area. This effect is calculated by the embedding a fine dust in the empty areas of the core (according to the fill specifications in the ITF file). The details of including the emulated fill are provided in the latest Star-RCXT User Guide and Command Reference Manual. [5], [6] Although it is not discussed in this paper, Star-RCXT also has the ability to model actual metal fill using the option METAL_FILL_POLYGON_HANDLING. [6] To perform analysis on the effect of metal fill, we have used a PLL block from one of IBMs 90 nm designs which has been taped out successfully. Emulated fill data has been used in the following observations to maintain the confidentiality of real fill data. Also a flowchart of the method used to run our tests is shown in Figure 5.3. The following table, Table 5.1, summarizes some of the details of the design: Type of Design Technology Number of Devices PLL 90 nm PMOS - 3728 NMOS - 4206 Capacitors - 1689 Resistors - 155 BJT 70

Table 5.1 Details of PLL design

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

PLL gds file

Run through Hercules, obtain XTR view

Run through Star RCXT

.nxtgrd file without emulated fill

.nxtgrd file with emulated fill

Run through Star RCXT

Obtain parasitic netlist

Obtain parasitic netlist

Compare results

Figure 5.3 Simulation flow for comparison of results with and without fill emulation

Figure 5.4 shows a plot of number of nets vs. percentage increase in capacitance values. It should be noted that the graph includes only the nets where the increase in the absolute value of capacitance from the addition of emulated fill was greater than 1 fF. We saw that approximately 11% of the nets fall into that category. As seen from the plot, the majority of these nets show 0 to 25% increase in their capacitance value.

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

45 Increase in Capacitance value (%) 40 35 30 25 20 15 10 5 0 0 50 100 150 200 250 300 Number of Nets
Figure 5.4 Percent increase in capacitance due to fill emulation

Figure 5.5 shows a plot of the magnitude of the increase in capacitance versus the number of nets for the same nets shown in Figure 5.4. As seen from the graph, the majority of the nets show an approximate capacitance increase of 1fF to 50 fF.
10000

Absolute increase in Capacitance Value (fF)

1000

100

10

1 1 31 61 91 121 151 181 211 241 271 Number of Nets

Figure 5.5 Increase in capacitance due to fill emulation SNUG San Jose 2005 12 Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

To complete our analysis, we used the PLL design to compare simulations using fill emulation and with actual fill shapes added. While the accuracy of the results can not be disclosed in this paper, it is interesting to note the difference in extraction run-times. Extractions using fill emulation experienced a run-time improvement of 71% for Hercules LVS and 93% for Star-RCXT, as compared to extractions with actual fill shapes added. The extractions with fill emulation had virtually the same run-time as extractions without both fill emulation and added fill shapes.

6.0 Parasitic Effects of Metal Cheesing

In deep submicron (DSM) technologies, metallization processes are often controlled through insertion of specific structures which cause non-ideal parasitic effects. In addition to metal fill, wide metal lines are often cheesed to assure uniform metal thickness. Wide metal wires have a tendency to dish (Figure 6.1) during chemical-mechanical polish (CMP). To prevent this, slots of metal are removed to even out the metal thickness (Figure 6.1).
Metal

Metal Dielectric Dielectric

Figure 6.1 Dishing to the left and cheesing to the right

Cheesing has obvious implications to the resistance of a metal line. For metal widths that are cheesed (above a certain width), resistance will be higher than without cheesing, as shown in Figure 6.2. In addition to resistive effects, there are capacitive effects of cheesing that need to be considered. In UDSM (ultra deep sub-micron) technologies, we need to carefully consider the assumption that cheesing has a negligible effect on capacitance.

Resistance

True R Ideal R

Width

Figure 6.2 Resistance vs. width with cheesing (true R) and without cheesing (ideal R)

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

Capacitive effects have been ignored to date due to the larger dimensions of metal layers and spacing between layers, and the fact that fringing inside the holes will compensate for the missing metal. For our testcases, we use a generic UDSM 3-layer technology consisting of 100nm metal and inter-level dielectric heights with un-doped SiO2 as the dielectric (R = 3.1). Our testcase is intended to represent a ground bus on M2, with a signal line running parallel above and below on M1 and M3. The ground bus dimensions are 200 um x 20 um. The metal line dimensions are 10 um x 1um. The testcase is shown in Figure 6.3.

Figure 6.3 Testcase

Using a hole density of 25% (hole width and spacing are equal) we will try to find the smallest hole dimensions for which a coupling capacitance of greater than 1fF is detected between the two signal wires. The 25% density was selected to represent a potential worst case for cheese patterns. In order to find the worst capacitive coupling, we will vary hole sizes between 0.1um and 2.0um. Additionally, for each hole size tested, we will test increasing x-y offsets to evaluate variation in the results for a given hole size. The results of this testing can be seen in Figure 6.4. From these results, we can see that below 0.5um hole size (at 25% hole density), the coupling effects are negligible (below 1fF). At 0.5um and above, however, we see that there is coupling through the metal that needs to be considered.

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

7 6 5 [M1-M3] CC (fF) 4 3 2 1 0 0 0.5 1 1.5 2 2.5 Hole Dimension (um) Mean Cc with Error Bars Max Cc

Figure 6.4 Capacitive coupling vs. hole dimension for 25% hole density

Additionally, this data demonstrates that above this threshold, not only is the capacitance non-negligible, but unpredictable as well. The variation from mean to worst case is accounted for by the offset. Therefore, if the wire were to move slightly, its coupling would be drastically different.

7.0 Conclusions and Recommendations

This paper has shown various parasitic effects that should be taken into account in circuit simulations. Working with Synopsys Professional Services, IBM has been able to model these effects in its design kits. The effects described in this paper are just a limited set of issues that should be taken into account.

8.0 Acknowledgements
We would like to thank our managers, Essam Mina (IBM), John Palmer (Synopsys), and Adam Rosenberg (Synopsys). Many thanks should also be given to Rich Lemert (Synopsys) and Ed Seibert (IBM) whose work enabled the features and extractions mentioned in this paper. We would also like to thank Terry Lowe and Padmanava Sen for providing us with testcase data.

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies

9.0 References
[1] T. Hook, J. Brown, P. Cottrell, E. Adler, D. Hoyniak, J. Johnson, and R. Mann, Lateral ion implant straggle and mask proximity effect, IEEE Transactions on Electron Devices, vol. 50, pp. 1946 1951, September 2003. G. Scott, J. Lutze, M. Rubin, F. Nouri, and M. Manley, NMOS drive current reduction caused by transistor layout and trench isolation induced stress, IEDM Tech Dig., pp. 827830, 1999. BSIM4.3.0 Users Manual, 2003 W-S. Lee, K-H. Lee, J-K. Park, T-K. Kim, Y-K. Park, J-T. Kong, Investigation of the capacitance deviation due to metal-fills and the effective interconnect geometry modeling, Proceedings of the Fourth International Symposium on Quality Electronic Design, 2003. Star-RCXT User Guide, Version V-2004.06, June 2004. Star-RCXT Command Reference, Version V-2004.06, June 2004.

[2]

[3] [4]

[5] [6]

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Numerical Analysis of Parasitic Effects in Deep Submicron Technologies