Lecture 6

Finite State Machines and Sequential Circuits

4.1

Error Detection
   
parity bit
4.2

data

Parity Generator

Figure out what this circuit does:

4.3

Moore Machines
Circuit Output Output Generation

Memory

Clock

Current State Control Inputs

Next State Function

Next State
4.4

Controllable Counter: Moore

W=1 W=1 C/010 W=1 B/001 W=0 A/000 W=1 W=0 H/111 W=0 G/110 W=1 W=0 W=0 W=0 D/011 W=0 E/100 W=0 F/101 W=1
4.5

W=1

W=1

Mealy Machines
Output Generation Memory

Circuit Output

Clock

Current State Control Inputs

Next State Function

Next State
4.6

Controllable Counter: Mealy

W=1/010 C B W=0/001 A W=0/ 010 W=0/ 011 D W=0/ 100 W=1/ 100 E W=1/011 W=1/001

W=0/101 W=1/000 W=0/000 H W=0/ 111 W=0/ 110 G W=1/110 F W=1/ 101
4.7

W=1/111

Moore vs. Mealy Machines

Question: If our circuits are triggered on the rising edge of the clock, when do states change in either machine? Trick Question: If our circuits are triggered on the rising edge of the clock, when do outputs change in either machine? Question: What is the difference between Moore and Mealy machines? Mealy machines generate output independently of the clock, so outputs can change at any time. Conversely, the outputs in Moore machines can only change at the rising edge of the clock. Mealy machines may sometimes have less states than Moore, however, their outputs are not synchronous with the clock what could pose a problem.
4.8

Two Different Circuit Categories

Synchronous: Outputs change only at discrete instants of time, that is, at the edges of a clock signal. Asynchronous: Outputs change whenever the inputs change. If a circuit has multiple inputs and they are presented at different points in time, the output will exhibit multiple changes.
4.9

Timing
D Q Flip-flop C tprop Combinational logic block D Q Flip-flop C tsetup

tcombinational

How do we determine the clock period for this circuit to operate correctly?

clock period > t prop + tcombinational + t setup

Complication: clock skew
4.10

10

Dealing with clock skew

Clock arrives at time t D Q Flip-flop C Combinational logic block with delay time of Clock arrives after t + D Q Flip-flop C

clock period > t prop + tcombinational + t setup + t skew

The safe thing to do is to over-dimension the clock period adding a small error margin.

4.11

11

Synchronizers
Asynchronous input Clock Q D Flip-flop C Synchronous output

If the clock edge catches the input during a transition (setup time not observed), the flip-flop goes into metastability.
Asynchronous input Clock D Q Flip-flop C D Q Flip-flop C Synchronous output

This works if the clock period is longer than the potential metastability period. 4.12

12

Exercise: Controllable Counter

Current Next state W state (XYZ) (XYZ) 000 000 001 001 010 010 011 011 0 1 0 1 0 1 0 1 001 000 010 001 011 010 100 011 Current Next state W state (XYZ) (XYZ) 100 100 101 101 110 110 111 111 0 1 0 1 0 1 0 1 101 100 110 101 111 110 000 111
4.13

13

Going for the minimal circuit

XY ZW 00 00 01 11 10 01 11 10 XY 00 ZW 00 01 11 10

0 0 1 1

0 0 1 1

0 0 1 1
XY

0 1 0 1
ZW

01 11 10

00 00 01 11 10

01

11

10

Z
4.14

14

Next, design the output functions:

Moore:
Outo =

Out1 = Out 2 =

Mealy:

Outo =

Out1 = Out 2 =
4.15

15