amplifiers

Designing high efficiency overdriven and saturated power amplifiers

An uncomplicated approach to high-efficiency, quasi-class E, RF power amplifier design based on active devices working in cutoff
By Francisco Javier OrtegaGonzlez, Alberto Asensio-Lpez, Alberto Martn-Consuegra, Juan Angel Ruiz and Germn Torregrosa-Penalva
t is common knowledge that efficiency is a major issue with the design of any transmitter. The benefits of high efficiency include power consumption, low power derating and high reliability, among others. In order to improve efficiency sever1 al specific amplification classes, such as class E have been described in classical literature. Nevertheless, the strict conditions required by high efficiency amplification techniques are difficult to achieved at high frequencies.

Devices intrinsic capacitances, packaging parasitics, low gain and intrinsic losses are the main limiting factors of high efficiency modes. The constraints become even more severe if high output power levels are involved. This article will discuss the design of a high efficiency VHF power amplifier (collector efficiency 0 = 85%, power added efficiency (PAE) = 72 %, output power (POUT) = 20 W) based on the proper control of the load and source impedance at fundamental and harmonic frequencies. Recent relevant works2 have shown the influence of proper load termination to achieve good approximations to high efficiency classes. Some practical works have shown that these approaches are feasible in practice3. It also has been proven that if the strict conditions of pure high efficiency classes cannot be fulfilled, good efficiency results can be achieved using approximated but proper design.

High efficiency approximated approach

Class E and other classical high efficiency modes are usually based on heavily overdriven and saturated devices working in cutoff and forward saturation regions. Inverse active and saturation regions have not been realized with high efficiency modes except for non-idealized operation 4,5 . Nevertheless, the most important rule to accomplish high efficiency operation lies on non coincidence of current and voltage at the same time over the active devices output. Any amplification class (pure or not) fulfilling this rule leads to high efficiency, one way or another. Recent works3,6,7 have shown through load-pull measurements and simulations that high efficiency operation is possible at high frequencies using heavily overdriven devices working in inverse active and saturated regions during part of their duty cycle. The amplifier system discussed in this article forces its active device to work in reverse regions to achieve high efficiency at high frequencies.
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Operating principles
The main cause precluding class E operation at high frequencies is the large intrinsic capacitances of most power transistors. The reactance of intrinsic transistor capacitances is often very low. So, to obtain optimum class E operation at high frequencies low-load impedances are needed. Unfortunately, most times low loads lead to higher output power levels and currents than specified for safe transistor operation. Maintaining high efficiency and safe operation forces the use of load impedances different from loads for optimum class E operation. High efficiency can be retained with different loads but they may cause negative collector-to-emitter voltage VCE < 0 during part of the signal period. Negative VCE voltage does not necessarily mean breakdown of the device or collector efficiency reduction. Using a proper base circuit and high reactive source impedance at the harmonics, the transistor can be forced to operate in inverse active and saturation regions.

Amplifier test fixture.

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During this period, VCE is low (zero for an ideal device) and the power derated by the transistor is also low, even for a significant collector current level. Nevertheless, because of the existence of inverse collector current the overall conduction angle of the device is effectively reduced. Therefore, the output power POUT is also reduced compared to the output power in optimum class E conditions, PE 1 . This power reduction can be considered a benefit in some extreme situations. These effects are illustrated Figure 1. This figure is a simulation of the collector current I C and V CE for the referred load conditions (note that the

fier, is derived from Z L = 4.3+4.6j. Assuming a parasitic inductance from the package and printed circuit board LP = 1.5 nH (0.84j @90 MHz), the effective load for the transistor is established as Z'L = 4.3 + 3.7j. On the other hand, the source impedance at the fundamental frequency is optimized for maximum power gain. The load and source impedances at the harmonics are set strongly reactive (at least 3 times the load at the fundamental). Discrete three-element matching networks are used to provide both the source an load impedances at the fundamental frequency while keeping strong inductive behavior at harmonic frequencies.

drive with very low 0 improvement is achieved but both, power gain and PAE. degrade very fast. The reason for this behavior is that fast degradation of gain occurs with high driving levels. Figure 3 shows this effect, output power (POUT) and power gain (G) are plotted vs. input power. The degradation of gain with only small improvement in output power POUT is evident. Figure 4 shows the collector to emitter voltage VCE and emitter current IE measured at the active device working under high efficiency conditions. Note that the effect of non negligible base current appears in this measurement as well.

Conclusions Amplifier testing and optimization

The amplifier was tested and optimized using the custom test-fixture shown in the photo on page 46. It not only provides a fixture for the transistor but also allows the variation of the load and source impedance while the load at the harmonics is kept strongly reactive. The test-fixture also provides ports for sampling of significant amplifier voltages and currents. This samples are measured in a broadband digital oscilloscope. At radio frequencies classical high efficiency amplification classes cannot be easily achieved. However, careful approximations can achieve good results with low efficiency degradation. A high efficiency design using forward and inverse active and saturation regions has been presented. An example has been designed constructed and the results measured. The device was loaded with high reactive source and load impedances at harmonic frequencies. The load at the fundamental frequency was chosen to function in sub-optimum class E with negative collectorto-emitter voltage during part of the duty cycle. This negative VCE allows inverse active conduction and saturation of the transistor. This operational mode has shown

Figure 1. Inverse saturation effect.

intrinsic capacitances of the transistor have been extracted outside the device during the simulation in order to clarify the discussed effect).

Results and measurements

Figure 2 shows collector efficiency, 0, and power added efficiency, PAE, vs. input power PIN. It should be noted that an optimum input power level exists (PIN = 2.75 W for this amplifier) for maximum PAE. Beyond this input

Amplifier design
The amplifier presented to illustrate this technique is based on the well known classical 2N6083 RF bipolar power transistor. The transistor manufacturer announces collector efficiency 0 = 65% and output power POUT = 30 W at 175 MHz for this device. The amplifier achieves 0C = 85% and POUT = 20 W at 90 MHz using the same device. In order to design the output load at the fundamental frequency, a linear equivalent value of the output capacitance C OUT = 105 pF was estimated from the measured open-base collector capacitance C OB . This capacitance exhibits a reactance XCOUT = 15.36j at 90 MHz. If this capacitance is the only reactive component used in the load network it forces an output power level PE = 31.2 W at VCC = 12.5 VDC for optimum class E operation 1 . The desired output power for this amplifier is POUT = 20 W. The curves published in3 have been used to design the amplifier load network. The relationship P OUT /P E = 0.64, (from3) the optimum load for this ampli-

Figure 2. 0 and PAE versus input power (PIN).

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very high collector efficiency and good PAE. with remarkable output power level at high frequencies.

References:
[1] Nathan O. Sokal, Alan D. Sokal, Class E-A New Class of high efficiency Tuned Single-Ended Switching Power Amplifiers", IEEE Journal of SolidState Circuits, VOL. SC-10, NO. 3, pp. 168-176, june 1975. [2 Frederick H. Raab, Class-E, class-C, and class-F power amplifiers based upon a finite number of harmonics", IEEE Transactions on Microwave Theory and Techniques, Volume: 49, NO. 8, pp. 1462-1468, Aug 2001. [3] Francisco Javier OrtegaGonzlez, Alberto Asensio-Lpez, Jos Luis Jimnez Martin, Germn Torregrosa-Penalva, High Efficiency Load-Pull Harmonic Controlled Class E Power Amplifier", IEEE Microwave and Guided Wave Letters, VOL 8, No 10, pp. 348-350, october 1998. [4] Frederick H. Raab, Effects of

Circuit variations on the Class E Tuned Power Amplifier", IEEE Journal of SolidState Circuits, VOL. SC-13, NO.2, pp. 239-247, april 1978. [5] Willian H.. Cantrell, Tuning Analysis for the High-Q Class-E Power Amplifier", I E E E Transactions on Microwave Theory and Techniques, VOL. 48, NO. 12, Figure 3. P and gain versus P OUT IN pp. 2397-2402, december 2000. [7] Marian K. Kazimierczuk, [6] Francisco Javier Ortega-Gonzlez, Wojiech A. Tabisz, Class C-E High Alberto Asensio-Lpez, Jos Luis Efficiency Tuned Power Amplifier," Jimnez Martin, Effects of Matching on IEEE Transactions on Circuit and RF Power Amplifier Efficiency and Systems, VOL. 36, NO. 3, pp. 421-428, Output Power", Microwave Journal, pp. march 1989. 60-72, april 1998.
Continued on page 52

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About the authors

Francisco Javier Ortega Gonzlez received the Ingeniero de Telecomunicacin degree from Universidad Politcnica de Madrid, Madrid, Spain, and the Ph.D. degree at the Dpto. de Seales, Sistemas y Radiocomunicaciones, E.T.S.I. Telecomunicacin, Universidad Politcnica de Madrid. His research activities are in the area of high frequency circuit design, electromagnetism and radar systems. Email; fjortega@diac.upm.es Alberto Asensio received the Ingeniero de Telecomunicacin degree from the Technical University of Madrid, Madrid, Spain in 1984, and the Ph.D. degree at the Signals, Systems, and Radiocommunications Department of the Technical School of Telecommunication Engineering of the same University in 1990, where he has been Associate Professor since 1991. His research activities are in the area of high frequency circuit design and radar systems. E-mail: vera@gmr.ssr.upm.es Alberto Martin Consuegra received the Ingenierio Tcnico de Telecomunicacin degree from de Universidad Politecnica de Madrid, Madrid, Spain. Currently is working toward its Ingeniero Electrnico degree at the Alcala de Henares University, Madrid. His research activities are in the area of electronic and high frequency circuit design. Juan Angel Ruiz was born in Madrid, Spain. Currently he is working toward its Ingeniero Tcnico de Telecomunicacin degree at the Universidad Politecnica de Madrid, Madrid. His research activities are in the area of high frequency circuit design and wireless networks. Germn Torregrosa Penalva received the Ingeniero de Telecomunicacin degree from Universidad Politcnica de Madrid, Madrid, Spain, in 1999, and is currently working toward the Ph.D. degree at the Dpto. de Seales, Sistemas y Radiocomunicaciones, E.T.S.I.Telecomunicacin, Universidad Politcnica deMadrid. His research activities are in the area of high frequency circuitdesign and radar systems.

Figure 4. VCE and IE measured waveforms.

Acknowledgements:
This work was supported by project TIC 2001-3839-C03-01 of the Spanish National Board of Scientific and Technology Research (MCYT).

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