A PROJECT REPORT ON

“THREE PHASE
LINE & LOAD REGULATION
USING SCR AND MICRO-CONTROLLER”
MICRO-CONTROLLER

AT ICIT. Pvt. Ltd.

PUNE.

BY,

Vipul Agarwal (06BE499)

Sushant Kadam (06BE514)
Vaibhav Vijay Lokhande (06BE522)
Dushyant Rajnikant Rana (06BE541)
Gupta Pratibha Ramniwas (06BE540)
Amarsinh Dhairyasinh Rajeshirke (06BE538)

Project report submitted to University of Pune, Pune.

VLSI Design & Research Centre

Department of Electronic Science
University of Pune - 411007.
 CERTIFICATE

This is to certify that Vipul Agarwal, Dushyant Rana, Amarsinh Rajeshirke,

Vaibhav Lokhande, Sushant Kadam, Gupta Pratibha Ramniwas has carried out the
project work towards the partial fulfillment of “Certificate course in Embedded System
Design” at VLSI design & research centre, Department of Electronic Science, University
of Pune.

Project title : Three Phase Line & Load Regulation by Using SCR and Controller
Duration : Jan-07 to Feb-07

This project has been carried out under the supervision of Mrs. Preeti Salunkhe and
guidance of Ms. Jyutika Nalawade, Automatic Electric Pvt. Ltd.

University Coordinator Project guide

Dr. A. D. Shaligram Ms. Jyutika

Nalawad VLSI design &research centre, Automatic Electric Pvt.
Ltd,
Department of electronic science, Lonavla.
University of Pune.

Project coordinator

Mrs. Preeti Salunkhe

VLSI Design & Research Center,
ICIT PVT LTD, Pune.
 CERTIFICATE

This is to certify that Vipul Agarwal has carried out the project work towards the
partial fulfillment of “Certificate course in Embedded System Design” at VLSI design &
research centre, Department of Electronic Science, University of Pune.

Project title : Three Phase Line & Load Regulation by Using SCR and Controller
Duration : Jan-07 to Feb-07

This project has been carried out under the supervision of Mrs. Preeti Salunkhe and
guidance of Ms. Jyutika Nalawade, Automatic Electric Pvt. Ltd.

University Coordinator Project guide

Dr. A. D. Shaligram Ms. Jyutika

Nalawad VLSI design &research centre, Automatic Electric Pvt.
Ltd,
Department of electronic science, Lonavla.
University of Pune.

Project coordinator

Mrs. Preeti Salunkhe

VLSI Design & Research Center,
ICIT PVT LTD, Pune.
 CERTIFICATE

This is to certify that Dushyant Rana has carried out the project work towards the
partial fulfillment of “Certificate course in Embedded System Design” at VLSI design &
research centre, Department of Electronic Science, University of Pune.

Project title : Three Phase Line & Load Regulation by Using SCR and Controller
Duration : Jan-07 to Feb-07

This project has been carried out under the supervision of Mrs. Preeti Salunkhe and
guidance of Ms. Jyutika Nalawade, Automatic Electric Pvt. Ltd.

University Coordinator Project guide

Dr. A. D. Shaligram Ms. Jyutika

Nalawad VLSI design &research centre, Automatic Electric Pvt.
Ltd,
Department of electronic science, Lonavla.
University of Pune.

Project coordinator

Mrs. Preeti Salunkhe

VLSI Design & Research Center,
ICIT PVT LTD, Pune.
 CERTIFICATE

This is to certify that Amarsinh Dhairyasinh Rajeshirke has carried out the
project work towards the partial fulfillment of “Certificate course in Embedded System
Design” at VLSI design & research centre, Department of Electronic Science, University
of Pune.

Project title : Three Phase Line & Load Regulation by Using SCR and Controller
Duration : Jan-07 to Feb-07

This project has been carried out under the supervision of Mrs. Preeti Salunkhe and
guidance of Ms. Jyutika Nalawade, Automatic Electric Pvt. Ltd.

University Coordinator Project guide

Dr. A. D. Shaligram Ms. Jyutika

Nalawad VLSI design &research centre, Automatic Electric Pvt.
Ltd,
Department of electronic science, Lonavla.
University of Pune.

Project coordinator

Mrs. Preeti Salunkhe

VLSI Design & Research Center,
ICIT PVT LTD, Pune.
 CERTIFICATE

This is to certify that Vaibhav Lokhande has carried out the project work towards
the partial fulfillment of “Certificate course in Embedded System Design” at VLSI design
& research centre, Department of Electronic Science, University of Pune.

Project title : Three Phase Line & Load Regulation by Using SCR and Controller
Duration : Jan-07 to Feb-07

This project has been carried out under the supervision of Mrs. Preeti Salunkhe and
guidance of Ms. Jyutika Nalawade, Automatic Electric Pvt. Ltd.

University Coordinator Project guide

Dr. A. D. Shaligram Ms. Jyutika

Nalawad VLSI design &research centre, Automatic Electric Pvt.
Ltd,
Department of electronic science, Lonavla.
University of Pune.

Project coordinator

Mrs. Preeti Salunkhe

VLSI Design & Research Center,
ICIT PVT LTD, Pune.
 CERTIFICATE

This is to certify that Sushant Kadam has carried out the project work towards the
partial fulfillment of “Certificate course in Embedded System Design” at VLSI design &
research centre, Department of Electronic Science, University of Pune.

Project title : Three Phase Line & Load Regulation by Using SCR and Controller
Duration : Jan-07 to Feb-07

This project has been carried out under the supervision of Mrs. Preeti Salunkhe and
guidance of Ms. Jyutika Nalawade, Automatic Electric Pvt. Ltd.

University Coordinator Project guide

Dr. A. D. Shaligram Ms. Jyutika

Nalawad VLSI design &research centre, Automatic Electric Pvt.
Ltd,
Department of electronic science, Lonavla.
University of Pune.

Project coordinator

Mrs. Preeti Salunkhe

VLSI Design & Research Center,
ICIT PVT LTD, Pune.
 CERTIFICATE

This is to certify that Gupta Pratibha Ramniwas has carried out the project work
towards the partial fulfillment of “Certificate course in Embedded System Design” at VLSI
design & research centre, Department of Electronic Science, University of Pune.

Project title : Three Phase Line & Load Regulation by Using SCR and Controller
Duration : Jan-07 to Feb-07

This project has been carried out under the supervision of Mrs. Preeti Salunkhe and
guidance of Ms. Jyutika Nalawade, Automatic Electric Pvt. Ltd.

University Coordinator Project guide

Dr. A. D. Shaligram Ms. Jyutika

Nalawad VLSI design &research centre, Automatic Electric Pvt.
Ltd,
Department of electronic science, Lonavla.
University of Pune.

Project coordinator

Mrs. Preeti Salunkhe

VLSI Design & Research Center,
ICIT PVT LTD, Pune.