Tarun Kumar Agarwal, Amit R. Trivedi, Vaidyanathan Subramanian and M. Jagadesh Kumar, IEEE Trans. on on Electron Devices, Vol.

58, pp.3485-3493, October 2011.

Compact Modeling of Partially Depleted Silicon-on-Insulator Drain-Extended MOSFET (DEMOS) including High-voltage and Floating Body Effects
Tarun Kumar Agarwal, Amit R. Trivedi, Vaidyanathan Subramanian, and M. Jagadesh Kumar, Senior Member, IEEE.

AbstractIn this paper, a scalable compact model for partially depleted SOI drain extended MOSFETs (DEMOS) is developed using a sub-circuit approach. The proposed compact model captures the special dc behavior of a partially depleted SOI DEMOS transistor. Our model accounts for high voltage effects such as quasi saturation, impact ionization in the drift region along with a oating body effect such as the kink effect in the output characteristics of the oating body PD SOI DEMOS transistor. In the sub-circuit approach used, the channel region is modeled using the BSIM4SOI model and the drift region is modeled using a bias-dependent resistance model along with a current-controlled current source. The model is validated for a set of channel and drift lengths to demonstrate the scalability of the model. The accuracy of the proposed compact model is veried using 2-D numerical simulations. Index TermsSOI DEMOS, High voltage devices, quasi saturation, impact ionization, Sub circuit approach, oating body effects, kink effect, Compact model, Scalability.

I. I NTRODUCTION Currently, the drain extended MOSFETs (DEMOS) have become quite preferable as a high voltage (HV) device for smart power ICs and interest in the accurate modeling of HV MOS transistors has increased in recent years due to the compatibility of these devices with standard CMOS technology [1]. HV MOS transistors can be designed for a wide range of voltage supplies, ranging from 5 V to 1000 V, leading to numerous applications, ranging from a power amplier (PA) in mobile handsets and base stations to automotive systems [2]. Over the years, as Si-RF technologies are maturing, silicon-oninsulator (SOI) HV MOSFETs have become a preferred choice over bulk HV MOSFETs providing enhanced power added efciency (PAE) and reduced crosstalk [3]. Optimal design of power circuits requires an accurate compact model of partially depleted SOI DEMOSFETs, which captures the high voltage behavior along with the oating body effects. To model the bulk HV MOSFETs and the SOI HV MOSFETs with a body contact, various modeling approaches are
This work was supported in part by the IBM Faculty award to M. J .Kumar. T. K. Agarwal and M. J. Kumar are with the Department of Electrical Engineering, Indian Institute of Technology, Delhi 110016, India (e-mail: tarun.agrawal90@gmail.com, mamidala@ieee.org). A. R. Trivedi and V. Subramanian are with Semiconductor Research and Development Center, IBM, Bangalore 560024, India (e-mail: amtrived@in.ibm.com, vaisubra@in.ibm.com).

reported in literature [4][9]. A frequently followed approach is to use a sub circuit along with the conventional low-voltage MOS transistor models. Some compact models are examples of this approach such as HV-EKV [4], [5], MM20 models [6], [7]. These models account only for the quasi saturation effect and show good results in terms of accuracy and speed for both dc and ac domains. But, sufcient emphasis on accurate modeling of other high voltage effects such as impact ionization in the drift region is not present in these models and also channel length scaling is not reported for all dc characteristics of HV MOSFETs. On the other hand, Wang et al. [10] report only the impact ionization in the drift region at higher gate biases and a physical model based on the BSIM3 substrate current model to model the impact ionization in the drift region. To the best of our knowledge, there is no compact model in literature for the oating body partially depleted SOI DEMOSFETs taking into account the quasi saturation effect, the impact ionization in the drift region and the kink effect in the output characteristics. The aim of this paper is, therefore, to develop a scalable compact model for partially depleted SOI DEMOSFETs simultaneously considering all the above special dc effects. To model these effects accurately, a sub-circuit consisting of a bias-dependent resistor and a current-controlled current source are used along with the BSIM4SOI compact model [11], [12]. The BSIM4SOI compact model can predict the kink for the gate biases where the channel region current is dominating. But, as the drift region starts dominating at higher gate biases, a sub-circuit is needed to model the kink effect along with the other high voltage effects. The other effects dominant in SOI transistors such as self-heating effect (SHE) can be easily modeled using the BSIM4SOI model and the developed model can be extended to capture ac behavior of a PD SOI DEMOS transistor. It may be noted that our compact model in its present form does not model the breakdown characteristics accurately. The accuracy of the proposed compact model is veried by 2-D device simulations [13]. II. D EVICE STRUCTURE AND SIMULATION RESULTS Fig. 1 shows the cross sectional schematic of a conventional oating body PD SOI MOS and a oating body PD SOI DEMOS transistor respectively. It is shown that a oating

body DEMOS device shown in Fig. 1(b) is derived from a PD SOI NMOS device shown in Fig. 1(a) by simply extending the drain of the device with a lightly doped drift region. Similarly, a body contacted DEMOS device can be derived from a oating body DEMOS device shown in Fig. 1(b) by simply having a p-type doped region beneath the source. The device parameters for simulation are given in Table. I based on a fabricated high voltage PD SOI MOS device in [14]. The device simulations are done using a 2-D numerical simulator, ATLAS from SILVACO [13]. To maintain sanity and selfconsistency in the simulated data, calibration of the impact ionization model in ATLAS is performed with the measured data of a PD SOI DEMOS device fabricated with SOI CMOS process [14]. In calibration, impact ionization coefcients are optimized to best t the experimental results (AN1 = 2x106 cm1 , AN2 = 2x106 cm1 , BN1 = 1.7x106 V/cm and BN2 = 1.7x106 V/cm). Further details are provided in Appendix. A. The drift region doping for the reference device is chosen to have a breakdown voltage higher than 15 V for the oating body device and 20 V for the body contacted device. Some aspects such as graded channel doping density and gate overlap are not considered in the design of DEMOS device shown in Fig. 1(b). This is due to the availability of sub micrometer photolithography to dene the channel length in the same way as CMOS devices and a self aligned drift-region implantation to the gate, rather than relying on the double-diffusion process [15]. The concept of intrinsic drain potential (VK ) has been a powerful tool to understand and model the high voltage effects observed in HV MOS transistors [16]. As Fig. 1(b) shows, VK denotes the surface potential at the junction of the intrinsic MOS region and the drift region. Fig. 2 shows the variation of VK with gate and drain biases for the body contacted PD SOI DEMOS device obtained using ATLAS. An interesting observation from Fig. 2 is that VK decreases with VG after reaching a maximum (VKM AX ) at a xed drain voltage VD . The reasons for this reduction in VK are clearly explained in [16]. Our analysis also shows that for lower values of VG , when the pinch-off of the depletion region in the drift region occurs, VK reaches its maximum value (VKM AX ) and current will be forced through the depletion zone of the drift region. However, as VG increases, pinch-off is delayed resulting in a local accumulation or corner injection of carriers in the substrate near the drift region leading to the VK reduction with VG after reaching the maximum [16]. Further, it can be physically explained using Kirk Effect. Kirk effect states that when the injected electron density from channel to the drift region exceeds the doping concentration of the drift region (Ndr ), the peak electric eld shifts from the channel-drift (p n ) junction to the drift-drain (n n+ ) junction at higher gate biases [17]. It further explains that VK increases with the gate voltage due to the existence of peak electric eld at the channel-drift (p n ) junction. This leads to an increase in the surface potential at p n junction with an increase in the gate voltage. And, with further increase in the gate voltage, VK decreases due to the existence of the peak electric eld at the drift-drain (n n+ ) junction. As a result, the surface potential decreases at the p n junction while

it increases at the n n+ junction. Based on the variation of VK with the gate voltage, we dene two modes of operation for HV MOSFETs. First being, a low voltage FET (or intrinsic MOS) dominant mode of operation in which VK increases with the gate voltage and reaches to a maximum (VKM AX ). Second mode of operation is when the drift region starts dominating and VK starts decreasing from VKM AX with an increase in the gate voltage. Based on the variation of VK , quasi saturation and the impact ionization in the drift region are physically explained using Kirk effect which further explains the second hump in the impact ionization current as shown in Fig. 3. To understand the kink behavior in the oating body PD SOI DEMOSFETs, a conventional PD SOI MOS transistor is chosen as a starting point. And it is observed that a oating body PD SOI DEMOS device behaves as a conventional oating body PD SOI MOS device in the rst mode of operation based on the VK variation. And, in the drift dominant second mode of operation, due to the impact ionization in the drift region or electron-hole pair generation at n n+ junction, the oating body potential shows different behavior than a conventional oating body PD SOI MOS transistor as shown in Fig. 4. It is clear from Fig. 4(b) that in the drift dominant mode of operation, the body potential starts rising at lower drain voltages, resulting in a kink in the output characteristics of the oating body PD SOI DEMOSFETs at lower drain voltages. And, with further increase in the gate voltage, the transistor enters the deep triode region of operation and the kink in the output characteristics disappears as shown in Fig. 5(b). In conclusion, to accurately model the kink behavior in the drift dominant mode of operation, the impact ionization in the drift region is to be accurately modeled. III. M ODELING STRATEGY Based on the physical insights gained from the device simulations, a compact model for partially depleted SOI DEMOSFETs is derived from the BSIM4SOI model and the sub-circuit. Here, the BSIM4SOI model is used to model the intrinsic MOS dominant mode of operation and the sub circuit, containing a bias-dependent resistance and a current-controlled current source, is used to model the drift region dominant mode of operation of the transistor. Fig. 6 shows the SPICE sub-circuit implementation, containing an intrinsic MOSFET, a bias-dependent resistor and a current-controlled current source (CCCS). The drain terminal of the intrinsic MOSFET is named as K. VK is calculated using the BSIM4SOI model and the bias-dependent resistor within the simulator. In this way, the drain to source current (IDS ), body current (IB ) and VK are expressed explicitly in terms of the external node voltages (D, G, S, B, X) where X (substrate node) is always grounded. A. Channel region or intrinsic MOS modeling The intrinsic MOSFET of the PD SOI DEMOS device is modeled using the BSIM4SOI compact model. The BSIM4SOI model shows good capability in modeling oating body effects, observed in partially depleted SOI MOSFETs, along with self heating effects (SHE) by using an improved impact ionization current and parasitic BJT current model [18].

In oating body conguration, only three external nodes are present for the intrinsic MOS which are gate (G), source (S) and substrate (X) while drain (K) and body (B) node voltages of the intrinsic MOS (VB and VK ) are calculated iteratively in circuit simulation. The potential of body node VB is calculated by the balance of all body current components and VK is calculated by the intrinsic MOS and the drift region currents. The body resistance, which is the part of the BSIM4SOI model, is neglected in the developed model i.e. the body resistance model parameters present in the BSIM4SOI model are set to their default values. The channel current, calculated using the BSIM4SOI model, is a function of VK , VG , VS , VB and VX . The impact ionization current due to the channel region (Iii1 ) is also calculated using the BSIM4SOI model. Iii1 is a function of IKS , VKS , VGS and VX . B. Drift region modeling In the drift region dominant mode of operation, the HVMOSFETs shows two important effects: (i) quasi saturation (as the drain current compression in the output characteristics) and (ii) the impact ionization in the drift region (as a second hump in the body current variation with gate voltage). a) Quasi saturation: Attempts to model quasi saturation accurately with JFET and a bias-dependent resistance are reported in literature [19][21]. However, to have a scalable model, bias-dependent resistance is more popular. In our work, a scalable bias-dependent drift region resistance (RDRIF T ) model is based on the equations used in the industry standard compact model HiSiM HV [22]. The modied equations for RDRIF T model are given as : RDRIF T = (RD LDR + f (VDS )) f (VGS ) f (VBS ) (1) where,
asat = VDS RDV D ( ( ) ) RDV G1 f (VGS ) = 1 + RDV G1 VGS RDV G2 f (VBS ) = 1 RDV B VBS ( ) RDV DS RDV D = RDV D 1 + SC (LGAT E 102 )RDV DSP

general body current equation due to the impact ionization in the drift region can be written as: LDR B Iii2 = alpha IDS exp( )dy (7) Ey 0 Eq. 7 can be approximated into a well known equation as given below [23]: ( ) B LDR Iii2 = alpha (VD VK ) IDS exp (8) (VD VK ) Here, VK is the potential at y=0 (at body-drift junction) and VD is the potential at y=LDR . As shown in Fig. 3, IB increases with gate voltage continuously until the device breaks down after the transistor enters the triode region. To model this behavior, Eq. 8 is modied as: ( ) B Iii2 = alpha (VD VK ) IDS exp Eef f where, Eef f = ( (VD VK ) (VGS VOF F )coef f 1 LDR ) (10) (9)

Model parameters in the current-controlled current source model (Eq. 9) are alpha, B, VOF F and coeff1. IV. R ESULTS AND DISCUSSION The model parameters of the developed compact model are extracted using a commercial extraction software package, ICCAP, after implementing the SPICE sub-circuit shown in Fig. 6 in Spectre [24]. The potential of the oating nodes K and B are calculated within the simulator using the in-built model, BSIM4SOI version 4, and the proposed subcircuit. Moreover, VB and VK are modeled through an inferred approach. And, to correctly model VB and VK , other correlation plots such as the output characteristics depicting the body bias and the drift resistance effect are used. Calculated VK and VB characteristics are shown in Fig. 7. Initially, after identifying the intrinsic MOSFET dominant regions, extraction of the BSIM4SOI model parameters is done for the scalable data. These are regions where VK increases with gate and drain biases. Next, to model VK correctly in the drift region dominant mode of operation, bias-dependent resistor model parameters are extracted for different channel and drift lengths. Fig. 7(a) shows that the calculated VK trend in the drift mode of operation is in complete agreement with the 2-D numerically simulated data. To model VB , which is crucial for modeling the kink behavior, the body current is accurately modeled for different channel lengths as shown in Fig. 8. Further, to accurately model the kink in the output characteristics, the effect of different body voltages (VB ) on the drain current is accurately modeled using Fig. 9 and 10. And, all body voltage dependent model parameters are extracted using the output characteristics and transfer characteristics for different body voltages, channel and drift lengths. The calculated results from the proposed model are calibrated with the 2-D numerically simulated characteristics of both the body contacted and oating body PD SOI DEMOS transistors for

f (VDS )

(2) (3) (4) (5) (6)

SC = LDR RDSC1 + RDSC2

Model parameters in this scalable bias-dependent drift resistance model are RD , asat, RDVG1, RDVG2, RDVB, RDVD, RDVDS, RDVDSP, RDSC1 and RDSC2. And, the extraction procedure for these model parameters and hence, the drift resistance is given in Appendix. B. b) Impact ionization in the drift region: The impact ionization current, in DEMOS devices, has contributions from both the channel-drift and the drift-drain junctions as shown in Fig. 3. As the BSIM4SOIs improved impact ionization model is only capable of modeling the impact ionization at the channel-drift junction using Iii1 , an extra current-controlled current source (Iii2 ) is added between external drain and body nodes to model the impact ionization at the drift-drain junction. Here, the derived equations for extra body current are physical as they involve VK , solved by the simulator. A

different dimensions. Fig. 10 shows that the calculated output characteristics of the body contacted transistor are in excellent agreement with the 2-D numerically simulated data for different channel and drift lengths. It is clear that the quasi saturation effect is well modeled using a scalable bias-dependent drift resistance model. The drift resistance model captures the increase in the drift resistance with increase in the drift length shown in Fig. 10(a) and Fig. 10(b). It also predicts a higher drain resistance at lower channel lengths to model the quasi saturation effect at lower gate biases for short channel devices as shown in Fig. 10(a) and Fig. 10(c). To accurately calculate the inferred body potential in the oating body PD SOI DEMOS, all the body current components such as impact ionization current, diode current and parasitic BJT currents need to be accurately modeled. Fig. 8 shows that the impact ionization current due to both channel and drift region is well modeled for different channel lengths. The impact ionization in the channel region is modeled using BSIM4SOI model parameters while impact ionization in the drift region is modeled using a currentcontrolled current source described in section III. Fig. 11(a) shows that the kink behavior in the quasi saturation regime is well captured by accurately modeling the impact ionization in the drift region. The output characteristics of a oating body PD SOI DEMOS transistor is accurately modeled across various channel and drift lengths, as shown in Fig. 11. This paper mainly focuses in modeling high voltage and oating body effects observed in PD SOI DEMOSFETs. Other second order effects such as self heating are not taken into account, but can easily be included by extracting the BSIM4SOI self heating model parameters. V. C ONCLUSION A scalable compact model for high voltage PD SOI devices is developed using a proposed sub-circuit approach. The developed compact model includes the high voltage and the oating body effects observed in PD SOI DEMOS devices. The relationship between the proposed sub-circuit modeling approaches and the physical mechanism of high voltage PD SOI MOS devices has also been discussed based on the device simulation results. Using the 2-D numerical simulator, ATLAS, a physical description of the specic dc behavior of partially depleted SOI DEMOSFETs is presented. The famous kink effect is studied for high-voltage oating body PD SOI devices. And, it is demonstrated that the kink effect disappears when the high voltage transistor enters deep quasi saturation regime. In the proposed modeling approach, the sub-circuit comprises of a intrinsic MOSFET and the drift region which are modeled using the BSIM4SOI model and a bias-dependent resistor respectively. Additionally, to model the impact ionization in the drift region, a current-controlled current source is added to the sub-circuit. The model performance is demonstrated for the 20-V DEMOS device by implementing the SPICE sub-circuit in Spectre (Cadence). Generally, the proposed compact model can be run on any SPICE simulator, since the model equations of the standard BSIM4SOI compact model are not changed. Therefore, the

developed compact model in this paper will enable the accurate design of complex circuits using PD SOI DEMOS devices based on SPICE simulation. ACKNOWLEDGMENT The authors would like to thank Y. S. Chauhan, A. Bandyopadhyay and folks at SRDC, Bangalore for their interesting comments. This work was sponsored by Semiconductor Research and Development Center, IBM, Bangalore, India. We are grateful to the reviewers for their careful and critical comments which have signicantly improved the readability and usefulness of the paper. R EFERENCES
[1] J. Mitros, C.-Y. Tsai, H. Shichijo, M. Kunz, A. Morton, D. Goodpaster, D. Mosher, and T. Eand, High-voltage drain extended MOS transistors for 0.18 m logic CMOS process, IEEE Transactions on Electron Devices, vol. 48, no. 8, pp. 1751-1755, Aug 2001. [2] M. Feng, S. Shyh-Chiang, D.C. Caruth, and J.J. Huang, Device technologies for RF front-end circuits in next-generation wireless communications, Proceedings of the IEEE , vol.92, no.2, pp. 354-375, Feb 2004. [3] J. G. Fiorenza and J. A. del Alamo, Experimental comparison of RF power LDMOSFETs on thin-lm SOI and bulk silicon, IEEE Trans. Electron Devices, vol. 49, no. 4, pp. 687-692, Apr. 2002. [4] Y. S. Chauhan, C. Anghel, F. Krummenacher, C. Maier, R. Gillon, B. Bakeroot, B. Desoete, S. Frere, A. B. Desormeaux, A. Sharma, M. Declercq and A. M. Ionescu, Scalable general high voltage MOSFET model including quasi-saturation and self-heating effects, Solid State Electron., vol. 50, no. 11/12, pp. 1801-1813, Nov./Dec. 2006. [5] Y. S. Chauhan, R. Gillon, B. Bakeroot, F. Krummenacher, M. Declercq, and A. M. Ionescu, An EKV-based high voltage MOSFET model with improved mobility and drift model, Solid State Electron., vol. 51, no. 11/12, pp. 1581-1588, Nov./Dec. 2007. [6] A. C. T. Aarts, N. DHalleweyn, and R. van Langevelde, A surface potential-based high-voltage compact LDMOS transistor model, IEEE Trans. Electron Devices, vol. 52, no. 5, pp. 999-1007, May 2005. [7] A. C. T. Aarts and W. J. Kloosterman, Compact modeling of highvoltage LDMOS devices including quasi-saturation, IEEE Trans. Electron Devices, vol. 53, no. 4, pp. 897-902, Apr. 2006. [8] H.J. Mattausch, T. Kajiwara, M. Yokomichi, T. Sakuda, Y. Oritsuki, M. Miyake, N. Sadachika, H. Kikuchihara, U. Feldmann, M. MiuraMattausch, HiSIM-HV: A compact model for simulation of highvoltage-MOSFET circuits, in International Conference on Solid-State and Integrated-Circuit Technology, Oct. 2008, pp.276-279. [9] N.V.T. DHalleweyn, J. Benson, W. Redman-White, K. Mistry and M. Swanenberg, MOOSE: a physically based compact DC model of SOI LD MOSFETs for analogue circuit simulation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.23, no.10, pp. 1399-1410, Oct. 2004. [10] J. Wang, R. Li, Y. Dong, X. Zou, L. Shao, and W. T. Shiau, Substrate current characterization and optimization of high voltage LDMOS transistors, Solid State Electron., vol. 52, no. 6, pp. 886-891, Jun. 2008. [11] D. Sinitsky, S. Tang, A. Jangity, F. Assaderaghi, G. Shahidi and C. Hu, Simulation of SOI devices and circuits using BSIM3SOI, IEEE Transactions on Electron Devices, vol. 19, no. 9, pp. 323-325, Sep 1998. [12] BSIM3SOI. [Online]. Disponible: http://www.device.eecs.berkeley.edu. [13] ATLAS Users Manual: Device Simulation Software. Santa Clara, CA: Silvaco Int., 2008. [14] J.G. Fiorenza, D.A. Antoniadis, J.A. del Alamo, RF power LDMOSFET on SOI, IEEE Electron Device Letters, vol.22, no.3, pp.139-141, Mar 2001. [15] L. Wang, J. Wang, C. Gao, J. Hu, P. Li, W. Li and S.H.Y.Yang, Physical Description of Quasi-Saturation and Impact-Ionization Effects in HighVoltage Drain-Extended MOSFETs, IEEE Transactions on Electron Devices, vol.56, no.3, pp.492-498, Mar. 2009. [16] C. Anghel, N. Hefyene, A. Ionescu, M. Vermandel, B. Bakeroot, J. Doutreloigne, R. Gillon, S. Frere, C. Maier, and Y. Mourier, Investigations and Physical Modelling of Saturation Effects in Lateral DMOS Transistor Architectures Based on the Concept of Intrinsic Drain Voltage, in IEEE European Solid-State Device Research Conference (ESSDERC), Sept. 2001, pp. 399-402.

[17] M.B. Willemsen and R. van Langevelde, High-voltage LDMOS compact model for RF applications, in IEDM Technical Digest., 2005, pp. 208-211. [18] M. Chan, P. Su, H. Wan, C.-H. Lin, S. K. H. Fung, A. M. Niknejad, C. Hu, and P. K. Ko, Modeling the oating-body effects of fully depleted, partially depleted, and body-grounded SOI MOSFETs, Solid State Electron., vol. 48, no. 6, pp. 969-978, Jun. 2004. [19] J. Jang, T. Amborg, Z. Yu and R.W. Dutton, Circuit Model for Power LDMOS including Quasi-Saturation, in Proc. SISPAD, 1999, pp. 15-18. [20] T. Lekshmi, A.K. Mittal, A. DasGupta, A. Chakravorty and N. DasGupta, Compact modeling of SOI-LDMOS including quasi-saturation effect, in Proc. IEDST, 2009, pp. 1-4. [21] N. Hefyene, E. Vestiel, B. Bakeroot, C. Anghel, S. Frere, A. Ionescu, and R. Gillon, Bias-dependent drift resistance modeling for accurate DC and AC simulation of asymmetric HV-MOSFET, in Proc. IEEE ESSDERC, Sep. 2002, pp. 203-206. [22] HiSIM HV 1.0.1 Users Manual, Copyright 2008, Hiroshima University and STARC, http://home.hiroshima-u.ac.jp/usdl/HiSIM HV/CCode/HiSIM HV 1.0.2 UsersManual.pdf. [23] N. Arora, MOSFET Models for VLSI Circuit Simulation: Theory and Practice. Secaucus, NJ, USA: Springer-Verlag New York, Inc., 1993. [24] Virtuoso Spectre Circuit Simulator, http://www.cadence.com/products/cic/spectre circuit.

A PPENDIX A C ALIBRATION P ROCEDURE To achieve sanity and self consistency in the data obtained using ATLAS for modeling purpose, the coefcients of the impact ionization model, in ATLAS, are found out using the calibration procedure described below. While, the other physical models, used in simulation by ATLAS, use the default value of coefcients. In our calibration, a device structure similar to the one used in [14] is created and simulated using ATLAS. Then, the output characteristics of SOI DMEOS transistor with and without the body contact are compared. Fig. 12(a) and 12(b) depict the measured output characteristics and those obtained using TCAD simulations primarily to show the off state breakdown voltage and the kink in the output characteristics. The calibrated device used for the TCAD simulation is not the exact replica of the experimental device. The main intention of showing the experimental data from [14] in Fig. 12 was merely as a guideline in order to come up with self consistent and meaningful data from device simulations which could then be used for the modeling part. However, the simulated data used in this paper is self-consistent which is shown by the presence of the kink in the output characteristics of the oating body device, the lower breakdown voltage of oating body device in comparison to the body contacted device and the scaling behavior with the channel and the drift length. In the end, the impact ionization model coefcients are optimized to best t the TCAD generated results such as the off-state breakdown voltage of SOI DEMOS device, with and without the body contact. A PPENDIX B D RIFT RESISTANCE EXTRACTION PROCEDURE The drift resistance equation is, based on the equations used in the industry standard compact model HiSiM HV, given by Eq. 1. The equation shows the drift resistance dependence on gate, drain and body bias along with the gate length. The extraction procedure for the model parameters used in these equations can be summarized in the following steps:

1) Firstly, a wide gate length device is chosen for extracting the model parameters used in RDRIF T equations such as RD , asat, RDVG1, RDVG2, RDVB and RDVD. At low drain biases, all the BSIM4SOI model parameters pertaining to the mobility, subthreshold slope, VT LIN and body effects are extracted. Using the IDLIN at higher gate biases, the RDRIF T at low drain bias is modeled using the parameter RD . This is followed by the medium and high drain bias modeling i.e. the output characteristics tting. The drain bias dependence of RDRIF T i.e. RDVD is extracted by tting the output characteristics slope and the quasi saturation regime. Similarly, the gate bias dependence of RDRIF T i.e. RDVG1 and RDVG2 and the body bias dependence i.e. RDVB are extracted. 2) Then, the deviations associated with the small geometries are taken into account by extracting the parameters RDVDS, RDVDSP, RDSC1 and RDSC2, following the step 1.

TABLE I D EVICE PARAMETERS USED IN THE SIMULATION , DERIVED FROM A REFERENCE DEVICE IN [14].

V (V)

Symbol tOX tSI tBOX Nch Ndr LCH LDR

Description Gate oxide thickness Silicon lm thickness Buried oxide thickness Channel doping (p-type) Drift region doping (n-type) S/D doping concentration Channel length Drift region length
Gate Source LCH P-Body Buried Oxide 0 Y X Substrate Drain tOX N+ N+

Value 30 nm 180 nm 1 m 1.5x1017 cm3 4x1016 cm3 1020 cm3 0.64 m 1 m

Mode I : Conventional MOSFET operation

Mode II : Drift dominant mode of operation

DS

1.5

=6.0 V 5.0 4.0 3.0

2.0

0.5

tSI tBOX

0 0

3
Gate Voltage(V)

Fig. 2. Variation of VK with gate bias for different drain biases obtained using ATLAS for a body contacted PD SOI DEMOS device.

Substrate
(a)

Gate Source tOX N+ LCH P-Body

LDR VK N-

Drain

N+

tSI tBOX
4
Impact ionization current same as conventional MOSFET Impact ionization in the drift region

Buried Oxide 0 Y X Substrate Substrate

(b)

Body Current (nA/m)

3
V =6.0 V

DS

2
5.5

Fig. 1. Cross sectional schematics of the n-channel devices. (a) A conventional oating body partially depleted SOI MOSFET. (b) A oating body partially depleted drain extended MOSFET (DEMOS).

1
5.0 4.0

0 0

Gate Voltage(V)

Fig. 3. Variation of the body current with gate bias for a body contacted PD SOI DEMOS device showing impact ionization in the drift region at higher gate biases, obtained using ATLAS.

300

Drain Current ( A/m)

200
V
GS

=5.0 V 4.5 4.0 3.5 3.0 2.0

100

1 0 0
VGS=2.0 V

0.8

Drain Voltage (V)

(a)
120

0.6
V (V)
B

0.4

GS

=5.0 V Drain Current ( A/m)

100 80 60 40 20 0 0
Mode II Mode I

VGS=5.0 V 4.5 4.0 3.5 3.0

0.2

in steps of 0.5 V

0 0

Drain Voltage(V)

(a)

2.0

0.8

3
Drain Voltage (V)

0.6
VGS=2.0 V VB(V)

(b)
3.0 4.5 5.0 4.0 3.5

0.4

Fig. 5. Output characteristics of the n-channel devices obtained using ATLAS. (a) A conventional oating body partially depleted SOI MOSFET. (b) A oating body partially depleted drain extended MOSFET (DEMOS).

0.2

0 0

3
(b)

6
R(VG,VD)

D Iii2=f(ID,VD,VK,VG) BSIM4SOI Model K Iii1 G B X

Drain Voltage(V)

Fig. 4. Body potential variation with drain bias obtained using ATLAS. (a) A conventional oating body partially depleted SOI MOSFET. (b) A oating body partially depleted drain extended MOSFET (DEMOS).

S
Fig. 6. model. SPICE sub-circuit implementation with the BSIM4SOI compact

2
5.0 4.0 VDS=6.0 V Body Current (nA/m)

4 2D numerical simulation model 3

V
DS

1.5
VK(V) 3.0 2.0

=6.0 V

2
5.5

0.5 2D numerical simulation modeled 0 3 3.5 4 4.5 5 5.5 6

Gate Voltage(V)

1
5.0 4.0

0 0

Gate Voltage(V)

(a)
1 0.8
Body Current (nA/m)

(a)
1.2 1 0.8 0.6
5.5

2D numerical simulation modeled

2D numerical simulation model

VDS=6.0 V

VB(V)

0.6
V
GS

=2.0 V 5.0 3.0 4.5 3.5 4.0

0.4 0.2 0 0

0.4
5.0

0.2
4.0

Drain Voltage(V)

0 0

Gate Voltage(V)

(b) Fig. 7. (symbols) 2-D numerically simulated and (solid lines) calculated VK and VB characteristics of (a) Body contacted PD SOI DEMOS and (b) Floating body PD SOI DEMOS using BSIM4SOI approach for LCH =0.64 m and LDR =1 m

(b) Fig. 8. (symbols) 2-D numerically simulated and (solid lines) calculated body current characteristics of PD SOI DEMOS using BSIM4SOI approach for (a) LCH =0.64 m and LDR =1 m. (b) LCH =3 m and LDR =1 m.

120 Drain Current ( A/m) 100

Drain Current ( A/m)

2D numerical simulation modeled VGS=4.0, 4.5, 5.0 V 3.5

120 100 80 60 40 20
2.0

2D numerical simulation modeled

GS

=5.0 V 4.5 4.0 3.5 3.0

80 3.0 60 40 2.0 20 0 0 1 2 3 4 Drain Voltage (V) 5 6

0 0

Drain Voltage (V)

(a)
80 2D numerical simulation modeled Drain Current ( A/m) Drain Current ( A/m) 60 VGS=3.5, 4.0, 4.5, 5.0 V 40 2.0 20 3.0

(a)
80 2D numerical simulation modeled 60
V
GS

=4.0, 4.5, 5.0 V 3.5

40

3.0

20
2.0

0 0

2 3 4 Drain Voltage (V)

0 0

Drain Voltage (V)

(b)
80 2D numerical simulation modeled Drain Current ( A/m) 60

(b)
60
VGS=5.0 V 4.5

2D numerical simulation modeled

Drain Current ( A/m) V
GS

=5.0 V

40
4.5 4.0

40

4.0 3.5

20

20

3.0 2.0

3.5 3.0 2.0

0 0

2 3 4 Drain Voltage (V)

0 0

Drain Voltage (V)

(c) Fig. 9. (symbols) 2-D numerically simulated and (solid lines) calculated output characteristics of a body contacted PD SOI DEMOS using BSIM4SOI approach at VB = 0.7 V for (a) LCH =0.64 m and LDR =1 m. (b) LCH =0.64 m and LDR =3 m. (c) LCH =3 m and LDR =1 m.

(c) Fig. 10. (symbols) 2-D numerically simulated and (solid lines) calculated output characteristics of a body contacted PD SOI DEMOS using BSIM4SOI approach for (a) LCH =0.64 m and LDR =1 m. (b) LCH =0.64 m and LDR =3 m. (c) LCH =3 m and LDR =1 m.

10

120 100
Drain Current ( A/m)

2D numerical simulation modeled

GS

=5.0 V 4.5 4.0 3.5

80 60 40

3.0

2.0

20 0 0 1 2 3 4 5 6

Drain Voltage (V)

(a)
80 2D numerical simulation modeled
Drain Current ( A/m)

60

GS

=4.0, 4.5, 5.0 V

3.5 3.0

40
2.0

(a)
200
with body contact without body contact

20

Drain Current ( A/m)

0 0

150
BV
off

Drain Voltage (V)

(b)
60 2D numerical simulation modeled VGS=5.0 V
Drain Current ( A/m)

100

50

40

4.5 4.0 3.5

0 0

10

15

20

25

Drain Voltage (V)

(b) Fig. 12. Measured and TCAD generated output characteristics of a SOI DEMOS device with and without body contact. (a) Measured output characteristics [14] and (b) Output characteristics obtained using ATLAS at VGS =3.5, 3.0, 2.5, 2.0, 1.5, 0 V .
6

20

3.0 2.0

0 0

Drain Voltage (V)

(c) Fig. 11. (symbols) 2-D numerically simulated and (solid lines) calculated output characteristics of a oating body PD SOI DEMOS using BSIM4SOI approach for (a) LCH =0.64 m and LDR =1 m. (b) LCH =0.64 m and LDR =3 m. (c) LCH =3 m and LDR =1 m.

11

Tarun Kumar Agarwal was born in Aligarh, Uttar Pradesh, India. He received the B.Tech degree in Electronic and communication Engineering from Z.H.C.E.T., Aligarh in 2008 and the M.Tech. degree in VLSI Design Tools and Technology from Indian Institute of Technology Delhi, India in 2010. His research interest includes compact modeling of power semiconductor devices, nano-scale MOSFETs and low-power circuit design.

Amit Ranjan Trivedi was born in Agra, India, in 1984. He received the B.Tech and M.Tech degrees in Electrical Engineering from Indian Institute of Technology, Kanpur (IITK). He pursued his masters thesis in Developing Numerical Techniques to Calculate Band Strucutre of Self Assembled Quantum Dots. In 2008, he joined IBM Semiconductor Research and Development Center (SRDC) in Bangalore, India. His research interest includes compact modeling of MOSFET, high voltage devices such as LDMOS, and nano-electronic devices.

M. Jagadesh Kumar was born in Mamidala, Andhra Pradesh, India. He received the M.S. and Ph.D. degrees in electrical engineering from the Indian Institute of Technology (IIT), Madras, India. From 1991 to 1994, he performed a postdoctoral research on the modeling and processing of highspeed bipolar transistors with the Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada. While with the University of Waterloo, he also did research on amorphous-silicon thin-lm transistors. From July 1994 to December 1995, he was initially with the Department of Electronics and Electrical Communication Engineering, IIT, Kharagpur, India, and then, he was with the Department of Electrical Engineering, IIT, New Delhi, India, where he became an Associate Professor in July 1997 and has been a Full Professor in January 2005. He is currently the Chair Professor of the NXP (Philips) (currently, NXP Semiconductors India Pvt. Ltd.) established at IIT Delhi by Philips Semiconductors, The Netherlands. He is the Coordinator of the Very Large Scale Integration (VLSI) Design, Tools, and Technology interdisciplinary program at IIT Delhi. He is also a Principal Investigator of the Nano-scale Research Facility at IIT Delhi. His research interests include nanoelectronic devices, device modeling and simulation for nanoscale applications, integrated-circuit technology, and power semiconductor devices. He has published extensively in these areas of research with three book chapters and more than 145 publications in refereed journals and conferences. His teaching has often been rated as outstanding by the Faculty Appraisal Committee, IIT Delhi. Dr. Kumar is a fellow of the Indian National Academy of Engineering, The National Academy of Sciences, India and the Institution of Electronics and Telecommunication Engineers (IETE), India. He is recognized as a Distinguished Lecturer of the IEEE Electron Devices Society (EDS). He is a member of the EDS Publications Committee and the EDS Educational Activities Committee. He is an Editor of the IEEE TRANSACTIONS ON ELECTRON DEVICES. He was the lead Guest Editor for the following: 1) the joint special issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES and the IEEE TRANSACTIONS ON NANOTECHNOLOGY (November 2008 issue) on Nanowire Transistors: Modeling, Device Design, and Technology and 2) the special issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on Light Emitting Diodes (January 2010 issue). He is the Editor-in-Chief of the IETE Technical Review and an Associate Editor of the Journal of Computational Electronics. He is also on the editorial board of Recent Patents on Nanotechnology, Recent Patents on Electrical Engineering, Journal of Low Power Electronics, and Journal of Nanoscience and Nanotechnology. He has reviewed extensively for different international journals. He was a recipient of the 29th IETE Ram LalWadhwa GoldMedal for his distinguished contribution in the eld of semiconductor device design and modeling. He was also the rst recipient of the India Semiconductor Association-VLSI Society of India TechnoMentor Award given by the India Semiconductor Association to recognize a distinguished Indian academician for playing a signicant role as a Mentor and Researcher. He is also a recipient of the 2008 IBM Faculty Award. He was the Chairman of the Fellowship Committee of The Sixteenth International Conference on VLSI Design (January 4-8, 2003, New Delhi, India), the Chairman of the Technical Committee for High Frequency Devices of the International Workshop on the Physics of Semiconductor Devices (December 13-17, 2005, New Delhi), the Student Track Chairman of the 22nd International Conference on VLSI Design (January 5-9, 2009, New Delhi), and the Program Committee Chairman of the Second International Workshop on Electron Devices and Semiconductor Technology (June 1-2, 2009, Mumbai, India).

Vaidyanathan Subramanian received his Bachelors Degree in Materials Science and Engineering from IIT Chennai in 2000 and his Masters Degree in Electrical and Electronics Engineering from Penn State University, USA. From 2003 to 2008, he was a researcher at IMEC Belgium where he worked on aspects of technology, characterization and modeling of deep sub-micron CMOS devices. In 2008 he obtained his Ph.D. from KU Leuven, Belgium on the topic Analog/RF performance of Multiple Gate MOSFETs. Since 2008, he is working at IBM SRDC, Bangalore, India on aspects of RF SOI FET modeling for Industry Process Design Kits (PDKs). He has (co)-authored more than 25 papers.