361 Electronics II Analog Switch Laboratory #3 Name: Daniyar Kassenov Date Submitted: 10/6/2011 Program: Telecomm Lab Partner:

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Abstract: The objective of this lab was to gain experience in an application where Pinch-off and the Ohmic regions of a JFET are used. Since In normal application VGG helps to figure if Vload = Vin or Vload = 0V, the first part of the lab we built a circuit with RL = 10K and set VGG = 0 (DC). To measure the Vin and Vload (sine wave) an oscilloscope was used with the amplitude the same as peak voltage. By changing the values of VGG we measured the Vin and Vload again. Having known that with a small Vds the transistor is in the ohmic region and that the On Resistance (ro) when VGS = 0, is the resistance between the drain and source when the transistor is in the Ohmic region, again using the settings provided in circuit #1 for Vin but changing RL = 1K, we measured Vload and Vin first with VGG=0 and 1 respectively. Finally, in the last part of the lab procedure we put the transistor in pinch-off mode when |VGS| > |VP|. In this case the transistor has a very large resistance between drain and source. As previously, Vin and Vload were measured with new values of VGG= 10V and RL= 1MEG. Ohmic region of a JFET are used. Confirmation of Vin voltage

Voltage across the load at Vgg=0V

Voltage across the load at Vgg=10V

Vin and Voltage across the load of 1K (ohmic region) and Vgg=0V

Vin=980mV Vload=810mV RL=1K RJFET=209.87ohm Vload=(Vin*RL)/(RL+ RJFET)

Vin and Voltage across the load of 1K (ohmic region) and Vgg=1V

Vin=990mV Vload=750mV RL=1K RJFET=320ohm Vload=(Vin*RL)/(RL+ RJFET)

Vin and Voltage across the load of 1M (saturation) and Vgg=10V

Vin=1.03V Vload=48mV RL=1M RJFET=20458833ohm=20Meg Vload=(Vin*RL)/(RL+ RJFET)

Data tables table 1 (pre-lab) Vgs = 0V Vgs = -0.5V Vgs = Vp

VGG=0V on-resistor 209.87ohm Vgg=10V

VGG=1V 320ohm ohmic

pinched 0ff-resistance 20Meg off

Initially when drain-source voltage Vds is zero, there is no attracting potential at the drain, so no current flows despite the fact that the channel is fully open. This gives drain current ID = 0. For small applied voltage, it acts as a simple resistor, and the drain current increases linearly with the increase in Vds, up to some point. This region of the curve to the left of that point is called the Ohmic region, because in this region the FET behaves like an ordinary resistor. It is to be noted that in the pinch-off region the channel resistance increases in proportion to increase in Vds and so keeps the drain current almost constant and the reverse bias required by the gate-channel junction is supplied by the voltage drop across the channel resistance due to flow of ID and not by the external bias because VGS = 0.

Analysis The main idea of this lab was to measure the voltage across the load with different VGG values. Also, I noticed that the more the voltage VGG, the less the voltage across the load. At VGG =10V, Vload = 0V, because the circuit acts as an open switch. Also it was noticed, that in the Ohmic region, when Vds is very small, the on-resistance is 209.87 ohms. In Ohmic region JFET acts like a resistor. In the Ohmic region both VGS and Vds control the channel current. However, when in pinched off region, the transistor has a very large resistance and very small current flowing through the drain-to-source and also, off-ressistance is very large=20Meg. According to the data, as we increase the gate voltage, the on-resistance also increases. Conclusion: The objective of this lab was to gain experience in an application where Pinch-off and the Ohmic regions of a JFET are used. In the first part of the lab we learned how VGG determines if Vload = Vin or Vload = 0V using different values for VGG. Next part of the lab comprised measurement of Vload and Vin when the transistor was in Ohmic region (Vds is very small). Finally, in the last part of the lab procedure we put the transistor in pinch-off mode whereit has a very large resistance between drain and source and measured Vload and Vin. I definitely gained a huge amount of experience in application of JFET with different modes (Pinch off or Ohmic), which in turn indicates that the objectives were met in all 3 parts of this lab session.