MOTOROLA Order this document

by MJE13007/D
SEMICONDUCTOR TECHNICAL DATA

MJE13007
 
    MJF13007
SWITCHMODE
NPN Bipolar Power Transistor
POWER TRANSISTOR
For Switching Power Supply Applications 8.0 AMPERES
400 VOLTS
The MJE/MJF13007 is designed for high–voltage, high–speed power switching
80/40 WATTS
inductive circuits where fall time is critical. It is particularly suited for 115 and 220 V
switchmode applications such as Switching Regulators, Inverters, Motor Controls,
Solenoid/Relay drivers and Deflection circuits.
• VCEO(sus) 400 V
• Reverse Bias SOA with Inductive Loads @ TC = 100°C
• 700 V Blocking Capability
• SOA and Switching Applications Information
• Two Package Choices: Standard TO–220 or Isolated TO–220
• MJF13007 is UL Recognized to 3500 VRMS, File #E69369

MAXIMUM RATINGS
Rating Symbol MJE13007 MJF13007 Unit
Collector–Emitter Sustaining Voltage VCEO 400 Vdc
Collector–Emitter Breakdown Voltage VCES 700 Vdc
Emitter–Base Voltage VEBO 9.0 Vdc
Collector Current — Continuous IC 8.0 Adc
Collector Current — Peak (1) ICM 16
Base Current — Continuous IB 4.0 Adc
Base Current — Peak (1) IBM 8.0
Emitter Current — Continuous IE 12 Adc
Emitter Current — Peak (1) IEM 24
RMS Isolation Voltage VISOL V CASE 221A–06
(for 1 sec, R.H. < 30%, TA = 25°C) TO–220AB
Test No. 1 Per Fig. 15 — 4500 MJE13007
Test No. 2 Per Fig. 16 — 3500
Test No. 3 Per Fig. 17 — 1500
Proper strike and creepage distance must
be provided
Total Device Dissipation @ TC = 25°C PD 80 40* Watts
Derate above 25°C 0.64 0.32 W/°C
Operating and Storage Temperature TJ, Tstg – 65 to 150 °C

THERMAL CHARACTERISTICS
Thermal Resistance RθJC °1.56° °3.12° °C/W
CASE 221D–02
— Junction to Case RθJA °62.5° °62.5°
ISOLATED TO–220 TYPE
— Junction to Ambient
UL RECOGNIZED
Maximum Lead Temperature for Soldering TL 260 °C MJF13007
Purposes: 1/8″ from Case for 5 Seconds
(1) Pulse Test: Pulse Width = 5.0 ms, Duty Cycle ≤ 10%.
*Measurement made with thermocouple contacting the bottom insulated mountign surface of the
*package (in a location beneath the die), the device mounted on a heatsink with thermal grease applied
*at a mounting torque of 6 to 8•lbs.

Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.

Designer’s and SWITCHMODE are trademarks of Motorola, Inc.

 Motorola, Inc. 1995 1

Motorola Bipolar Power Transistor Device Data
  
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
*OFF CHARACTERISTICS
Collector–Emitter Sustaining Voltage VCEO(sus) 400 — — Vdc
(IC = 10 mA, IB = 0)

Collector Cutoff Current ICES mAdc

(VCES = 700 Vdc) — — 0.1
(VCES = 700 Vdc, TC = 125°C) — — 1.0
Emitter Cutoff Current IEBO — — 100 µAdc
(VEB = 9.0 Vdc, IC = 0)

SECOND BREAKDOWN
Second Breakdown Collector Current with Base Forward Biased IS/b See Figure 6
Clamped Inductive SOA with Base Reverse Biased — See Figure 7
*ON CHARACTERISTICS
DC Current Gain hFE —
(IC = 2.0 Adc, VCE = 5.0 Vdc) 8.0 — 40
(IC = 5.0 Adc, VCE = 5.0 Vdc) 5.0 — 30
Collector–Emitter Saturation Voltage VCE(sat) Vdc
(IC = 2.0 Adc, IB = 0.4 Adc) — — 1.0
(IC = 5.0 Adc, IB = 1.0 Adc) — — 2.0
(IC = 8.0 Adc, IB = 2.0 Adc) — — 3.0
(IC = 5.0 Adc, IB = 1.0 Adc, TC = 100°C) — — 3.0
Base–Emitter Saturation Voltage VBE(sat) Vdc
(IC = 2.0 Adc, IB = 0.4 Adc) — — 1.2
(IC = 5.0 Adc, IB = 1.0 Adc) — — 1.6
(IC = 5.0 Adc, IB = 1.0 Adc, TC = 100°C) — — 1.5

DYNAMIC CHARACTERISTICS
Current–Gain — Bandwidth Product fT 4.0 14 — MHz
(IC = 500 mAdc, VCE = 10 Vdc, f = 1.0 MHz)

Output Capacitance Cob — 80 — pF

(VCB = 10 Vdc, IE = 0, f = 0.1 MHz)

Collector to Heatsink Capacitance, MJF13007 Cc–hs — 3.0 — pF

SWITCHING CHARACTERISTICS
Resistive Load (Table 1)
Delay Time td — 0.025 0.1 µs
Rise Time (VCC = 125 Vdc, IC = 5.0 A, tr — 0.5 1.5
IB1 = IB2 = 1.0 A, tp = 25 µs,
Storage Time Duty Cycle ≤ 1.0%) ts — 1.8 3.0
Fall Time tf — 0.23 0.7
Inductive Load, Clamped (Table 1)
Voltage Storage Time VCC = 15 Vdc, IC = 5.0 A TC = 25°C tsv — 1.2 2.0 µs
Vclamp = 300 Vdc TC = 100°C — 1.6 3.0

Crossover Time IB(on) = 1.0 A, IB(off) = 2.5 A TC = 25°C tc — 0.15 0.30 µs

LC = 200 µH TC = 100°C — 0.21 0.50

Fall Time TC = 25°C tfi — 0.04 0.12 µs

TC = 100°C — 0.10 0.20
* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.

2 Motorola Bipolar Power Transistor Device Data

  

VCE(sat), COLLECTOR–EMITTER SATURATION

1.4 10
VBE(sat), BASE–EMITTER SATURATION
IC/IB = 5 5 IC/IB = 5
1.2
2

VOLTAGE (VOLTS)
VOLTAGE (VOLTS)

1
1
0.5

TC = – 40°C 0.2
0.8 TC = – 40°C
25°C 0.1
25°C
0.6 0.05
100°C
100°C
0.02
0.4 0.01
0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10
IC, COLLECTOR CURRENT (AMPS) IC, COLLECTOR CURRENT (AMPS)

Figure 1. Base–Emitter Saturation Voltage Figure 2. Collector–Emitter Saturation Voltage

3
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS)

TJ = 25°C
2.5

1.5 IC = 8 A

IC = 5 A
1
IC = 3 A

0.5 IC = 1 A

0
0.01 0.02 0.05 0.1 0.2 0.5 1 2 3 5 10
IB, BASE CURRENT (AMPS)

Figure 3. Collector Saturation Region

100 10000

Cib TJ = 25°C
TJ = 100°C
hFE , DC CURRENT GAIN

C, CAPACITANCE (pF)

1000
25°C

10 40°C
Cob

VCE = 5 V 100

1 10
0.01 0.1 1 10 0.1 1 10 100 1000
IC, COLLECTOR CURRENT (AMPS) VR, REVERSE VOLTAGE (VOLTS)

Figure 4. DC Current Gain Figure 5. Capacitance

Motorola Bipolar Power Transistor Device Data 3

  
100 10
50 Extended SOA @ 1 µs, 10 µs
20
IC, COLLECTOR CURRENT (AMPS)

IC, COLLECTOR CURRENT (AMPS)

8
10 1 µs
5 10 µs
2 TC = 25°C 6 TC ≤ 100°C
DC 1 ms
1 GAIN ≥ 4
5 ms LC = 500 µH
0.5 4
0.2 VBE(off)
BONDING WIRE LIMIT
0.1 THERMAL LIMIT
2 –5 V
0.05 SECOND BREAKDOWN LIMIT
CURVES APPLY BELOW
0.02 RATED VCEO
0 0V –2 V
0.01
10 20 30 50 70 100 200 300 500 1000 0 100 200 300 400 500 600 700 800
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) VCEV, COLLECTOR–EMITTER CLAMP VOLTAGE (VOLTS)

Figure 6. Maximum Forward Bias Figure 7. Maximum Reverse Bias Switching

Safe Operating Area Safe Operating Area

1 There are two limitations on the power handling ability of a

transistor: average junction temperature and second break-
SECOND BREAKDOWN down. Safe operating area curves indicate IC — VCE limits of
0.8
DERATING
POWER DERATING FACTOR

the transistor that must be observed for reliable operation;

i.e., the transistor must not be subjected to greater dissipa-
0.6 tion than the curves indicate.
The data of Figure 6 is based on TC = 25°C; TJ(pk) is vari-
THERMAL
0.4
able depending on power level. Second breakdown pulse
DERATING
limits are valid for duty cycles to 10% but must be derated
when T C ≥ 25°C. Second breakdown limitations do not der-
0.2 ate the same as thermal limitations. Allowable current at the
voltages shown on Figure 6 may be found at any case tem-
perature by using the appropriate curve on Figure 8.
0 At high case temperatures, thermal limitations will reduce
20 40 60 80 100 120 140 160
the power that can be handled to values less than the limita-
TC, CASE TEMPERATURE (°C)
tions imposed by second breakdown.
Figure 8. Forward Bias Power Derating Use of reverse biased safe operating area data (Figure 7)
is discussed in the applications information section.
r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1
0.7
D = 0.5
0.5

D = 0.2
0.2
D = 0.1
0.1
RθJC(t) = r(t) RθJC
0.07 D = 0.05 P(pk) RθJC = 1.56°C/W MAX
0.05 D CURVES APPLY FOR POWER
D = 0.02 t1
PULSE TRAIN SHOWN
t2 READ TIME AT t1
0.02
D = 0.01 DUTY CYCLE, D = t1/t2 TJ(pk) – TC = P(pk) RθJC(t)
SINGLE PULSE
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 10 k
t, TIME (msec)

Figure 9. Typical Thermal Response for MJE13007

4 Motorola Bipolar Power Transistor Device Data

  

r(t), TRANSIENT THERMAL RESISTANCE (NORMALIZED)

1
D = 0.5
0.5

0.3 D = 0.2
0.2
D = 0.1
RθJC(t) = r(t) RθJC
0.1 P(pk) RθJC = 3.12°C/W MAX
D = 0.05 t1 D CURVES APPLY FOR POWER
0.05 PULSE TRAIN SHOWN
t2 READ TIME AT t1
0.03 SINGLE PULSE DUTY CYCLE, D = t1/t2 TJ(pk) – TC = P(pk) RθJC(t)
0.02

0.01
0.01 0.02 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 30 50 100 200 300 500 1K 2K 3K 5K 10K 20K 30K 50K 100K
t, TIME (msec)

Figure 10. Typical Thermal Response for MJF13007

SPECIFICATION INFORMATION FOR SWITCHMODE APPLICATIONS

INTRODUCTION 25°C and 100°C. Increasing the reverse bias will give some
improvement in device blocking capability.
The primary considerations when selecting a power
The sustaining or active region voltage requirements in
transistor for SWITCHMODE applications are voltage and
switching applications occur during turn–on and turn–off. If
current ratings, switching speed, and energy handling
the load contains a significant capacitive component, high
capability. In this section, these specifications will be
current and voltage can exist simultaneously during turn–on
discussed and related to the circuit examples illustrated in
Table 2.(1) and the pulsed forward bias SOA curves (Figure 6) are the
proper design limits.
VOLTAGE REQUIREMENTS For inductive loads, high voltage and current must be
sustained simultaneously during turn–off, in most cases, with
Both blocking voltage and sustaining voltage are important the base to emitter junction reverse biased. Under these
in SWITCHMODE applications. conditions the collector voltage must be held to a safe level
Circuits B and C in Table 2 illustrate applications that at or below a specific value of collector current. This can be
require high blocking voltage capability. In both circuits the
accomplished by several means such as active clamping,
switching transistor is subjected to voltages substantially
RC snubbing, load line shaping, etc. The safe level for these
higher than VCC after the device is completely off (see load
devices is specified as a Reverse Bias Safe Operating Area
line diagrams at IC = Ileakage ≈ 0 in Table 2). The blocking
(Figure 7) which represents voltage–current conditions that
capability at this point depends on the base to emitter
can be sustained during reverse biased turn–off. This rating
conditions and the device junction temperature. Since the
is verified under clamped conditions so that the device is
highest device capability occurs when the base to emitter
never subjected to an avalanche mode.
junction is reverse biased (VCEV), this is the recommended
and specified use condition. Maximum ICEV at rated VCEV is (1) For detailed information on specific switching applications, see
specified at a relatively low reverse bias (1.5 Volts) both at (1) Motorola Application Note AN719, AN873, AN875, AN951.

Motorola Bipolar Power Transistor Device Data 5

  
Table 1. Test Conditions For Dynamic Performance
RESISTIVE
REVERSE BIAS SAFE OPERATING AREA AND INDUCTIVE SWITCHING
SWITCHING

VCC
+15 V
1 µF 150 Ω 100 Ω MTP8P10
100 µF L +125
3W 3W MTP8P10
TEST CIRCUITS

MUR8100E V
MPF930
RC
MUR105 RB1
MPF930 IC Vclamp = 300 Vdc
RB TUT
+10 V IB
MJE210 A SCOPE
RB2 IB
5.1 k
50 Ω 150 Ω D1
COMMON TUT VCE
3W
500 µF 51
MTP12N10 –4V
Voff
1 µF

Inductive
V(BR)CEO(sus) Switching RBSOA
VALUES
CIRCUIT

L = 10 mH L = 200 mH L = 500 mH VCC = 125 V

RC = 25 Ω
RB2 = 8 RB2 = 0 RB2 = 0
D1 = 1N5820 OR EQUIV.
VCC = 20 Volts VCC = 15 Volts VCC = 15 Volts
IC(pk) = 100 mA RB1 selected for RB1 selected for
desired IB1 desired IB1

TYPICAL
tf CLAMPED t1 ADJUSTED TO
WAVEFORMS 25 µs
IC
tf UNCLAMPED ≈ t2
TEST WAVEFORMS

OBTAIN IC +11 V
Lcoil (ICM)
ICM t1 ≈ VCE PEAK
VCC
t
t1 tf VCE 0
Lcoil (ICM)
t2 ≈
VCE Vclamp
IB1 9V
VCEM Vclamp tr, tf < 10 ns
TEST EQUIPMENT IB DUTY CYCLE = 1.0%
t SCOPE — TEKTRONIX RB AND RC ADJUSTED
TIME t2 475 OR EQUIVALENT FOR DESIRED IB AND IC
IB2

VOLTAGE REQUIREMENTS (continued)
In the four application examples (Table 2) load lines are
shown in relation to the pulsed forward and reverse biased
SOA curves.
In circuits A and D, inductive reactance is clamped by the
diodes shown. In circuits B and C the voltage is clamped by
the output rectifiers, however, the voltage induced in the pri-
mary leakage inductance is not clamped by these diodes and
could be large enough to destroy the device. A snubber net-
work or an additional clamp may be required to keep the
turn–off load line within the Reverse Bias SOA curve.
Load lines that fall within the pulsed forward biased SOA
curve during turn–on and within the reverse bias SOA curve
during turn–off are considered safe, with the following as-
sumptions:
(1) The device thermal limitations are not exceeded.
(2) The turn–on time does not exceed 10 µs (see standard
pulsed forward SOA curves in Figure 6).
(3) The base drive conditions are within the specified limits
shown on the Reverse Bias SOA curve (Figure 7).
CURRENT REQUIREMENTS
An efficient switching transistor must operate at the re-
quired current level with good fall time, high energy handling
capability and low saturation voltage. On this data sheet,
these parameters have been specified at 5.0 amperes which
represents typical design conditions for these devices. The
current drive requirements are usually dictated by the
VCE(sat) specification because the maximum saturation volt-
age is specified at a forced gain condition which must be du-
plicated or exceeded in the application to control the
saturation voltage.
SWITCHING REQUIREMENTS
In many switching applications, a major portion of the
transistor power dissipation occurs during the fall time (tfi).
For this reason considerable effort is usually devoted to
reducing the fall time. The recommended way to accomplish
this is to reverse bias the base–emitter junction during turn–
off. The reverse biased switching characteristics for inductive
loads are shown in Figures 13 and 14 and resistive loads in
Figures 11 and 12. Usually the inductive load components
will be the dominant factor in SWITCHMODE applications
and the inductive switching data will more closely represent
the device performance in actual application. The inductive
switching characteristics are derived from the same circuit
used to specify the reverse biased SOA curves, (see Table 1)
providing correlation between test procedures and actual
use conditions.

6 Motorola Bipolar Power Transistor Device Data

  
SWITCHING TIME NOTES An enlarged portion of the turn–off waveforms is shown in
Figure 13 to aid in the visual identity of these terms. For the
In resistive switching circuits, rise, fall, and storage times designer, there is minimal switching loss during storage time
have been defined and apply to both current and voltage and the predominant switching power losses occur during the
waveforms since they are in phase. However, for inductive crossover interval and can be obtained using the standard
loads which are common to SWITCHMODE power supplies equation from AN222A:
and any coil driver, current and voltage waveforms are not in PSWT = 1/2 VCCIC(tc) f
phase. Therefore, separate measurements must be made on Typical inductive switching times are shown in Figure 14. In
each waveform to determine the total switching time. For this general, trv + tfi ≅ tc. However, at lower test currents this rela-
reason, the following new terms have been defined. tionship may not be valid.
As is common with most switching transistors, resistive
tsv = Voltage Storage Time, 90% IB1 to 10% Vclamp switching is specified at 25°C and has become a benchmark
trv = Voltage Rise Time, 10–90% Vclamp for designers. However, for designers of high frequency con-
tfi = Current Fall Time, 90–10% IC verter circuits, the user oriented specifications which make
tti = Current Tail, 10–2% IC this a “SWITCHMODE” transistor are the inductive switching
tc = Crossover Time, 10% Vclamp to 10% IC speeds (tc and tsv) which are guaranteed at 100°C.

SWITCHING PERFORMANCE

10000 10000
VCC = 125 V 7000 VCC = 125 V
IC/IB = 5 5000 ts IC/IB = 5
IB(on) = IB(off) IB(on) = IB(off)
TJ = 25°C TJ = 25°C
1000 tr PW = 25 µs
PW = 25 µs 2000
t, TIME (ns)

t, TIME (ns)

1000
700
100 500

tf
td 200

10 100
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
IC, COLLECTOR CURRENT (AMP) IC, COLLECTOR CURRENT (AMP)

Figure 11. Turn–On Time (Resistive Load) Figure 12. Turn–Off Time (Resistive Load)

10000
IC IC/IB = 5
Vclamp 5000
90% Vclamp 90% IC IB(off) = IC/2
Vclamp = 300 V tsv
tsv trv tfi tti 2000
LC = 200 µH
tc 1000 VCC = 15 V
t, TIME (ns)

500 TJ = 25°C
Vclamp
10% 10% 200 tc
Vclamp IC
IB 90% IB1 2%
IC 100
tfi
50

20
10
0.1 0.2 0.3 0.5 0.7 1 2 3 5 7 10
TIME
IC, COLLECTOR CURRENT (AMP)

Figure 13. Inductive Switching Measurements Figure 14. Typical Inductive Switching Times

Motorola Bipolar Power Transistor Device Data 7

  
Table 2. Applications Examples of Switching Circuits
CIRCUIT LOAD LINE DIAGRAMS TIME DIAGRAMS

SERIES SWITCHING 16 A TURN–ON (FORWARD BIAS) SOA

REGULATOR ton ≤ 10 µs
IC
DUTY CYCLE ≤ 10%
TC = 100°C

COLLECTOR CURRENT
PD = 3200 W 2
ton toff
300 V TURN–OFF (REVERSE BIAS) SOA
1.5 V ≤ VBE(off) ≤ 9 V
A 8A t
TURN–ON DUTY CYCLE ≤ 10% TIME
VCE
VCC VO TURN–OFF

VCC
400 V 1 700 V 1
+
VCC
COLLECTOR VOLTAGE t
Notes: TIME
1 See AN569 for Pulse Power Derating Procedure.

FLYBACK TURN–ON (FORWARD BIAS) SOA

16 A ton ≤ 10 µs IC
INVERTER
DUTY CYCLE ≤ 10%
TC = 100°C PD = 3200 W 2 toff
COLLECTOR CURRENT

VCC VO
TURN–OFF (REVERSE BIAS) SOA ton
300 V
N 1.5 V ≤ VBE(off) ≤ 9 V t
B 8A
TURN–OFF DUTY CYCLE ≤ 10% VCE
LEAKAGE SPIKE

VCC +
TURN–ON VCC + N (Vo) N (Vo)
+ LEAKAGE
SPIKE VCC
+ VCC
400 V 1 700 V 1
VCC + N (Vo) COLLECTOR VOLTAGE
Notes: t
1 See AN569 for Pulse Power Derating Procedure.

PUSH–PULL TURN–ON (FORWARD BIAS) SOA IC

INVERTER/CONVERTER 16 A ton ≤ 10 µs
DUTY CYCLE ≤ 10%
toff
TC = 100°C PD = 3200 W 2 ton
COLLECTOR CURRENT

t
300 V TURN–OFF (REVERSE BIAS) SOA
1.5 V ≤ VBE(off) ≤ 9 V VCE
C VO 8A
TURN–ON DUTY CYCLE ≤ 10% 2 VCC

VCC VCC
2 VCC
TURN–OFF
+
VCC 400 V 1 700 V 1 t
COLLECTOR VOLTAGE
Notes:
1 See AN569 for Pulse Power Derating Procedure.

TURN–ON (FORWARD BIAS) SOA

SOLENOID DRIVER 16 A ton ≤ 10 µs
IC
DUTY CYCLE ≤ 10%
TC = 100°C PD = 3200 W 2 toff
VCC ton
COLLECTOR CURRENT

300 V TURN–OFF (REVERSE BIAS) SOA

1.5 V ≤ VBE(off) ≤ 9 V t
SOLENOID 8A
D DUTY CYCLE ≤ 10%
VCE
TURN–OFF
VCC
TURN–ON

+ VCC 400 V 1 700 V 1

t
COLLECTOR VOLTAGE
Notes:
1 See AN569 for Pulse Power Derating Procedure.

8 Motorola Bipolar Power Transistor Device Data

  
TEST CONDITIONS FOR ISOLATION TESTS*

MOUNTED MOUNTED MOUNTED

FULLY ISOLATED FULLY ISOLATED FULLY ISOLATED
CLIP PACKAGE CLIP PACKAGE PACKAGE
0.107” MIN 0.107” MIN
LEADS LEADS LEADS

HEATSINK HEATSINK HEATSINK

0.110” MIN

Figure 15. Screw or Clip Mounting Position Figure 16. Clip Mounting Position Figure 17. Screw Mounting Position
for Isolation Test Number 1 for Isolation Test Number 2 for Isolation Test Number 3

* Measurement made between leads and heatsink with all leads shorted together

MOUNTING INFORMATION

4–40 SCREW CLIP

PLAIN WASHER

HEATSINK

COMPRESSION WASHER

NUT HEATSINK

Figure 18. Typical Mounting Techniques

for Isolated Package

Laboratory tests on a limited number of samples indicate, when using the screw and compression washer mounting technique, a screw
torque of 6 to 8 in . lbs is sufficient to provide maximum power dissipation capability. The compression washer helps to maintain a constant
pressure on the package over time and during large temperature excursions.
Destructive laboratory tests show that using a hex head 4–40 screw, without washers, and applying a torque in excess of 20 in . lbs will
cause the plastic to crack around the mounting hole, resulting in a loss of isolation capability.
Additional tests on slotted 4–40 screws indicate that the screw slot fails between 15 to 20 in . lbs without adversely affecting the package.
However, in order to positively ensure the package integrity of the fully isolated device, Motorola does not recommend exceeding 10 in . lbs
of mounting torque under any mounting conditions.

** For more information about mounting power semiconductors see Application Note AN1040.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola Bipolar Power Transistor Device Data 9

  
PACKAGE DIMENSIONS

SEATING
B F –T– PLANE

C
4 T S NOTES: INCHES MILLIMETERS
1. DIMENSIONING AND TOLERANCING PER ANSI
DIM MIN MAX MIN MAX
Y14.5M, 1982.
A 0.570 0.620 14.48 15.75
Q A 2. CONTROLLING DIMENSION: INCH.
B 0.380 0.405 9.66 10.28
3. DIMENSION Z DEFINES A ZONE WHERE ALL
1 2 3 BODY AND LEAD IRREGULARITIES ARE C 0.160 0.190 4.07 4.82
ALLOWED. D 0.025 0.035 0.64 0.88
H U F 0.142 0.147 3.61 3.73
G 0.095 0.105 2.42 2.66
K H 0.110 0.155 2.80 3.93
Z J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
L 0.045 0.060 1.15 1.52
N 0.190 0.210 4.83 5.33
L Q 0.100 0.120 2.54 3.04
V R R 0.080 0.110 2.04 2.79
S 0.045 0.055 1.15 1.39
G J T 0.235 0.255 5.97 6.47
U 0.000 0.050 0.00 1.27
D V 0.045 ––– 1.15 –––
N Z ––– 0.080 ––– 2.04
STYLE 1:
PIN 1. BASE
2. COLLECTOR
3. EMITTER
4. COLLECTOR

CASE 221A–06
TO–220AB
ISSUE Y

–T– SEATING
PLANE
–B– C NOTES:
F 1. DIMENSIONING AND TOLERANCING PER ANSI
S Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
Q
U INCHES MILLIMETERS
A DIM MIN MAX MIN MAX
A 0.621 0.629 15.78 15.97
1 2 3 B 0.394 0.402 10.01 10.21
C 0.181 0.189 4.60 4.80
H D 0.026 0.034 0.67 0.86
–Y– F 0.121 0.129 3.08 3.27
K G 0.100 BSC 2.54 BSC
H 0.123 0.129 3.13 3.27
J 0.018 0.025 0.46 0.64
K 0.500 0.562 12.70 14.27
G J L 0.045 0.060 1.14 1.52
N R N 0.200 BSC 5.08 BSC
Q 0.126 0.134 3.21 3.40
L R 0.107 0.111 2.72 2.81
D 3 PL S 0.096 0.104 2.44 2.64
U 0.259 0.267 6.58 6.78
0.25 (0.010) M B M Y STYLE 2:
PIN 1. BASE
2. COLLECTOR
3. EMITTER

CASE 221D–02
ISOLATED TO–220 TYPE
ISSUE D

How to reach us:

USA / EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298

10 Motorola Bipolar Power Transistor Device Data

*MJE13007/D*
◊ MJE13007/D