Sizing CMOS Circuits by Means of The G Methodology and A Compact Model

MOS-AK workshop 13 Dec.
2008
Sizing CMOS circuits by means of the gm/ID methodology and a compact model.
P.G.A. Jespers Universit Catholique de Louvain

paul.jespers@uclouvain.be
1
MOS-AK workshop, Dec 13, 2008. P.G.A. Jespers
sizing.... find D.C. currents and transistor sizes meeting : a prescribed gain-bandwidth product minimal power consumption minimal area large gain . short channel devices,.. low- voltage, low-power MOS circuits low-voltage, low-powercircuits
BWRC, Dec 12, 2008. P.G.A. Jespers
Outline Sizing... the Intrinsic Gain Stage (I.G.S.) gm/ID semi-empirical methodology gm/ID compact model methodology L-V, L-P, short channel I.G.S. the Miller Op. Amp. Conclusion
The Intrinsic Gain Stage (I.G.S.)
gain-bandwidth sizing: find ID and W/L achieving T
W/L Vin
ID (sat) C
Vout
A (dB)
gm = T.C
gm .V ID A
- 20 dB/decade
gm T = C
log
4
1) (strong inversion)
# " = Cox
ID Vout Vin W/L (sat) C
W L
gm =
$ ID 2 " ID = $ VG n
gm = "T C
!
?
n ( "T C ) 1 W = $ # L 2 Cox ID
! A = gm V = A
ID
2" VA nID
ID
power decreases, gain increases
!
2) weak inversion)
" VG % ID = Io exp$ ' nUT & #
Vout Vin W/L (sat) C
ID
gm =
ID nUT
gm = "T C
!
W ! L
Amax = "
VA nUT
!
sizing in moderate inversion?
!
ID
I D = n UT ! T C
what does gm/ID represent ?

ID
10-3 10-4 10-5 10-6 10-7 10-8 10 10

-9
W.I. approx (expon)
" gm % 1 ( ID ( = = log ( ID ) $ ' # ID & ID (VGS (VGS
-10
10-11 10-12
!
gm/ID
10-13
S.I. approx (quadratic)

0 0.5 1 1.5 2 2.5 3
VG
35
30
25
20
15
10
0.5
1.5
2.5
VG
why gm/ID?
gm/ID does not depend on the transistor width gm and ID are proportional to W gm/ID bridges a small signal and a large signal quantity
gm
" ID
gm/ID controls gain, power consumption ...
!
gm A = VA ID
9
The gm/ID sizing methodology (semi-empirical)
gm = "T C
gm " gm % $ ' # ID &
measurements reconstructed data (BSIM, PSP...) model E.K.V...
W ref
ID (VGS ) =
" log I (V ) ! ( Dref GS ) "VGS
I (V ) ! W (VGS ) = D GS (W ) ref ID ref (VGS )
monitors the mode of operation of the MOS transistor
10
Example
W/L
parasitic drain junction
mobility degradation
ID
fT = 1 GHz; Co = 1 pf; L = 120 nm; VS = 0; VDS = 0.6 V; Wmax = 1 m;
11
(A)
First paper
A gm/ID Based Methodology for the Design of CMOS Analog Circuits and Its Application to the Synthesis of a Silicon-on-Insulator Micropower OTA F. Silveira, D. Flandre, P.G.A. Jespers
IEEE JOURNAL OF SOLID STATE CIRCUITS, VOL. 31, NO. 9, SEPTEMBER 1996 p. 1314 ...
12
13
The ACM and EKV compact models + continuous model (saturation, weak to strong inversion) + few parameters: n subthreshold slope factor ISu unary specific current VTo threshold voltage - uniformly doped substrate, no mobility degradation, - gradual channel approximation (1D)
A.C.M.
- An MOS transistor model for analog circuit design Ana I. Cunha, M.C. Schneider, C. G. Montoro. IEEE JSSC,vol 33,n10,oct, 1998.
E.K.V.
- An analytical MOS transistor model valid in all regions of operation and dedicated to Low-Voltage and Low-current applications. Chr. C.Enz, F. Krummenacher, E. A. Vittoz. Analog Integrated Circuits and Signal Processing, Kluwer Ac. Publ. 1995.
14
The compact model (1) drain current normalization
normalized drain current
i=
ID IS
64 744 4 8 ! W 1 W 2 2 specific current " 2nUT Cox " nUT Cox 1 24 L 4 3 2 L EKV ACM ISu ! ! unary specific current (W = L)
!
15
The compact model (2) norm. drain current (saturation)
i = q2 + q
normalized mobile charge density
q=" Qi# # 2nUT Cox
!
channel voltage
VP " V = UT [2(q "1) +! (q)] log
pinch - off voltage
!
gate voltage
VG " VTo VP = n
16
The compact model (3)
ID
VD
=
sat
IDForward - IDReverse
sat
VG VS
VG VS VD
VP " VS = UT [2(qF "1) + log(qF )]
VP " VD = UT [2(qR "1) + log(qR )]
2 2 i = qF + qF - (qR + qR )
17
example : IDu(VG) of grounded source (VS = 0 V) saturated (q => qF) transistor parametric method
2 i = qF + qF
IDu = i ISu
VG = nVP + VTo
qF
!
VP = UT (2(qF "1) + logqF ) !
IDu (A)
% data UT = .026; n =! 1.2; Isu = 1e-6; VTo = 0.4; % compute qF = logspace(-4,1.2,50); i = qF.^2 + qF; ID = i*Isu; VP = UT*(2*(qF-1) + log(qF)); VG = n*VP + VTo; % plot semilogy(VG,ID); grid
S.I.
W.I. VTo VG (V)

18
gm/ID of the saturated transistor
gm d log(i) = ID dVG
d log(i) = and
di 2qF + 1 = dqF i i
" 1% 2q + 1 dVG = n dVP = nUT $ 2 + ' dqF = nUT F dqF qF & qF #
!
!
gm 1 qF 1 1 = = ID nUT i nUT qF + 1
!
19
sizing the Intrinsic Gain Stage by means of the E.K.V. model

% data fT = 1e8; C = 1e-12; n = 1.2; Isu = 1e-6; VTo = 0.4;
specs
E.K.V. param
gm/ID sizing
% compute UT = .026; T = 2*pi*fT; gm = T*C; qF = logspace(-4,1.5,50); gmoverID = 1./(n*UT*(1+qF)); ID = gm./gmoverID; IDu = Isu*(qF.^2 + qF); WsL = ID./IDu; VP = UT*(2*(qF+1) + log(qF)); VG = n*VP + VTo; % plot loglog(ID,WsL,'b',ID,VG,'r');
20
sizing the Intrinsic Gain Stage by means of the E.K.V. model
strong inversion approx.
W/L
fT C
= 100 = 1
MHz pF
gm/ID sizing
VGS (V) ID (A)
weak inversion approx.

21
The basic EKV / ACM model does not apply to short channel devices! Real ID(VGS) characteristics however look very similar.
ID (A)
VDS = 1.2 V VDS = 0.2 V
L = 500 nm
L = 100 nm 90 nm technology N channel W = 10 m VSB = 0 V VGS (V)

22
The spatial distribution of electrical fields in the substrate boils down to a 2D problem controlled mainly by L, VSB, VDS, little by VGS. The inversion layer confines to a 1D problem controlled by VGS and L, VSB, VDS. Is it possible to model ID(VG) characteristics by means of the EKV / ACM model with parameters that are functions of L, VS and VD.?
gate
poly
silicide
drain
source
nn+
to
x
p
23
E.K.V. Identification to be performed in the

common source configuration
log(ID)
S.I. W.I. M.I. VGS gm/ID 1/nUT

80 to 70 %
mobility degradation
For L, VS and VDS
VGS VTo
24
Isu (specific current)
VGS " VTo = VP # q n ! !
IDu (VGS ) = ISu (VGS ) i (A)
ISuo
2 " ISu = 2nUT oCox # (i) 14 4 2 3 I Suo
polynomial fit
VGS (V)
mobility degradation factor For L, VS and VDS

25
Verification : Iu(VGS) reconstruction
n,VTo and ISuo
IDu (A) n slope factor experm. data +++ n,Vto, Isuo and (i) VGS (V)
N-channel; L = 100 nm; VDS = 0.6 V; VSB = 0.6 V.
26
gm/ID (V-1)
edge conductance effect ?
mob. degradation VDS = 0.6 V VSB = 0 V L = 100 nm
VGS (V)
experimental model model (no mob degradation)
+++++
27
28
gm ID
does not depend on W as long as W >> Wmin (true for most analogue circuits) depends on L, VDS and VSB for - VT roll-off - D.I.B.L. - C.L.M. - mobility degradation - .
29
fT = 1 GHz; Co = 1 pf; L = 120 nm; VS = 0; VDS = 0.6 V;
W/L strong inversion approx. n, VTo and Isuo no mobilty degradation: = 1
VGS (V) ID weak inversion approx.

(A)
30
fT = 1 GHz; Co = 1 pf; L = 120 nm; VS = 0; VDS = 0.6 V;
W/L strong inversion approx. n, VTo and Isuo with mobilty degradation: ()
VGS (V) ID weak inversion approx.

(A)
31
Add drain junction cap. to Co

W/L
partitioning
VGS (V) ID
(A)
32
Comparison with semi-empirical method (+++ )

W/L
partitioning
VGS (V) ID
(A)
33
Param. dependence on VDS 1) n small 2) VTo
L m 0.100 0.110 0.120 0.130 0.140 0.160 0.500 1.000 4.000
VSB = 0 V.
D.I.B.L. VDS (V)
34
Param. dependence on VDS 1) n small ISu (A) 2) VTo 3) ISu

channel length ! modulation mobility degradation (vert)
mobility (longitudinal) Desaturation
VDS VGS
(V)
(V)
VSB = 0 V.
35
Param. dependence on VDS 1) n small 2) VTo 3) ISuo

VSB = 0 V.
L m 0.100 0.110 0.120 0.130 0.140 0.160 0.500 1.000 4.000
C.M.L.
36
Param. dependence on VDS 1) n small e ld 2) VTo a l fi ic 3) Isuo v e rt 4) (i)
VSB = 0 V.
lo n
g itu
d in
al f
ie ld
not sat. sat.
37
Verification : IDu(VDS) reconstruction (S.I.)

X 10-5 experimental model model (no mob degradation)
+++++
VGS
0.7 V
0.6 V
0.5 V
38
Verification : IDu(VDS) reconstruction (W.I.)

X 10-9 0.10 V +++++ experimental model model (no mob degradation)
VGS
D.I.B.L.
0.05 V
0.00 V
39
40
1) fix NDPole and Zero with respect to T to meet phase margin

V DD Bias Q5 Q4
2 ID1
Q1b +
ID2
node 2
vin / 2
Q1a
v in / 2
Cm
vout
C2
"T
z
g = m1 Cm g = m2 = Z"T Cm
2 gm2 Cm = NDP"T Cm (C1+C2)Cm + C1C2
node 3
node1
Q2
Q3a C3
Q3b C1
V SS
" ndp =
e.g. Z = 10 and NDP = 4 5 for phase margin of approx. 60

41
2) Size the A transistors.

spec. initial guess
V DD Bias Q5
2 ID1
Q1b +
Q4
ID2
node 2
gm1 = "T Cm
I D1 g = ! m1$ g # m& #I & " D %1
vin / 2
Q1a
v in / 2
Cm
vout
C2
node 3
node1
Q2
qF1
Q3a C3
Q3b C1
V SS
W1 = ID1 L1 IDu 1
gm2 = Z gm1
g I D2 = ! m2 gm $ # & #I & " D %2
qF2
W2 = ID2 L2 IDu 2
42
3) Size the B transistors.

more constraints
V DD Bias Q5
zero systematic offset
2 ID1
Q1b +
Q4
ID2
node 2
VG3 = VG2
"W % ID1 $ ' = # L &3 IDu2
vin / 2
Q1a
v in / 2
Cm
vout
C2
node 3
node1
Q2
Q3a C3
Q3b C1
V SS
! Q5 are in strong inversion
choose bias so that Q4 and
IDu4 = IDu5
!
"W % ID 2 $ ' = # L &4 IDu4

"W % 2 ID1 = $ ' # L &5 IDu4
43
4) Estimate C1, C2, C3 and compute Cm Choose L1 medium (voltage gain) L2 min. size L3 large for min 1/f noise (beware from doublet!) L4 matching + size L5 matching + common mode rejection the parasitic cap. are estimated knowing Ws and Ls + techno. data a new Cm is extracted from inverted NDP equation
NDP " Cm = 0.5 ! $C1 + C2 + Z #
% Z (C1 + C2 ) + 4 C1 C2 ' NDP &

reiterate until Cm gets constant
44
example
qF1 = 0.0316 --> 3.16 qF2 = 0.10 --> 2 qF4 = 2,90 Spec: fT = 50 MHz; C = 1 pF; VDD = 1.2 V; Z = 10 NDP = 4 L1 L2 L3 L4 L5 = 1 m = 0.5 = 1 m = 0.5 = 1 m
qF exploration space
phase margin
1.2 V
Q 5 Q1
2 ID1
Q4 Cm
ID2
node 2
C2 Q2
m m
node 3
Q3
node1
0V
C3
C1
45
W1
W2
VG2 W3
VG1 W4
46
constant active area (m2) 47
constant supply (A) constant active area (m2) 48
constant gain (dB) constant supply (A) constant active area (m2) 49
constant gain (dB) constant supply (A) constant active area (m2) 50
The selected point qF VGS (V) I (A) W (m) L gain (dB)

1.2 V
Q 5 Q1
Q1
0.433 0.29 2 x 8.1 67.3 1 45.1
Q2
1.065 0.40 143.7 47.5 0.5 39.2
Q3
1.236 0.40 2 x 8.1 2.23 1
Q4
2.90 0.49
Q5
2.90 0.49
57.83 0.5
7.69 1
2 ID1
Q4 Cm
ID2
node 2
C2 Q2
0.1965 1.0375 0.0576 0.6242 C1 C2 C3 Cm pF pF pF pF
node 3
Q3
node1
gain = 81 dB power consump. = 191 W
0V
C3
C1
51
Conclusion
gm/ID relates a small signal param. to a large signal quantity does not vary with transistor widths controls the mode of operation, power consump, gain ...
paves the way for sizing CMOS circuits semi-empirically (look-up tables : ID, gm, gd, ..) by means of the E.K.V./A.C.M. model (parameters look-up tables or fitting functions) simple expressions of ID, gm/ID, gd/ID qF monitors mode of operation increased physical insight suitable for sub-micron low-voltage low-power circuits
52
gm/ID sizing methodology for low-power/voltage CMOS circuits

by P.G A. Jespers
to be published 2009 by Springer
paul.jespers@uclouvain.be
53
A list of references concerning the gm/ID methodology: 1) A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-insulator micropower OTA. F. Silveira, D. Flandre and P.G.A. Jespers IEEE Journal of Solid-State Circuits, vol 31, n 9, sept 1996, p. 1314 - 1319. (the first reference) 2) A CAD methodology for optimizing transistor current and sizing in analog CMOS design. D.M. Binkley, C.E. Hopper, S.D. Tucker, B.C. Moss, J.M. Rochelle and D.P. Foty. IEEE Trans. on computer-aided design of integrated circuits and systems, vol 22, n 2, Febr. 2003. 3) gm/ID-based mosfet modeling and modern analog design. D. Foty, D. Binkley, Matthias Bucher. Presented at MIXDES, Wroclaw, Poland, 20 June 2002. 4) Une mthodologie de conception des amplificateurs oprationnels faible consommation P. Jespers. FTFC2001 records, mai-juin, Paris, p.99-106 5) Automated design methodology for CMOS analog circuit blocks in complex systems. R. Ionita, A. Vladimirescu and P.G.A. Jespers. contact Prof Vladimirescu, UCBerkeley, BWRC,2208 Allston Way, Berkeley, CA 94704. 6) Sizing of MOS transistors for amplifier design. R.L. Oliveira Pinto, M.C. Schneider and C.G. Montoro. ISCAS 2000. 7) A behavioral model of a 1.8-V flash A/D converter based on device parameters. M. Hasan, H.H.P. Shen, D.R. Allee, M. Pennell. IEEE Trans. on computer-aided design of integrated circuits and systems, vol 19, n 1, Jan 2000, p 69-82
54

Sizing CMOS Circuits by Means of The G Methodology and A Compact Model

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Sizing CMOS Circuits by Means of The G Methodology and A Compact Model

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MOS-AK workshop 13 Dec.

P.G.A. Jespers Universit Catholique de Louvain

MOS-AK workshop, Dec 13, 2008. P.G.A. Jespers

BWRC, Dec 12, 2008. P.G.A. Jespers

The Intrinsic Gain Stage (I.G.S.)

gain-bandwidth sizing: find ID and W/L achieving T

BWRC, Dec 12, 2008. P.G.A. Jespers

BWRC, Dec 12, 2008. P.G.A. Jespers

what does gm/ID represent ?

10-3 10-4 10-5 10-6 10-7 10-8 10 10

W.I. approx (expon)

" gm % 1 ( ID ( = = log ( ID ) $ ' # ID & ID (VGS (VGS

S.I. approx (quadratic)

BWRC, Dec 12, 2008. P.G.A. Jespers

gm/ID controls gain, power consumption ...

The gm/ID sizing methodology (semi-empirical)

measurements reconstructed data (BSIM, PSP...) model E.K.V...

" log I (V ) ! ( Dref GS ) "VGS

I (V ) ! W (VGS ) = D GS (W ) ref ID ref (VGS )

monitors the mode of operation of the MOS transistor

BWRC, Dec 12, 2008. P.G.A. Jespers

parasitic drain junction

BWRC, Dec 12, 2008. P.G.A. Jespers

BWRC, Dec 12, 2008. P.G.A. Jespers

BWRC, Dec 12, 2008. P.G.A. Jespers

The compact model (1) drain current normalization

normalized drain current

The compact model (2) norm. drain current (saturation)

VP " V = UT [2(q "1) +! (q)] log

pinch - off voltage

BWRC, Dec 12, 2008. P.G.A. Jespers

The compact model (3)

VP " VS = UT [2(qF "1) + log(qF )]

VP " VD = UT [2(qR "1) + log(qR )]

BWRC, Dec 12, 2008. P.G.A. Jespers

W.I. VTo VG (V)

BWRC, Dec 12, 2008. P.G.A. Jespers

gm/ID of the saturated transistor

" 1% 2q + 1 dVG = n dVP = nUT $ 2 + ' dqF = nUT F dqF qF & qF #

sizing the Intrinsic Gain Stage by means of the E.K.V. model

BWRC, Dec 12, 2008. P.G.A. Jespers

sizing the Intrinsic Gain Stage by means of the E.K.V. model

strong inversion approx.

VGS (V) ID (A)

weak inversion approx.

VDS = 1.2 V VDS = 0.2 V

L = 100 nm 90 nm technology N channel W = 10 m VSB = 0 V VGS (V)

BWRC, Dec 12, 2008. P.G.A. Jespers

E.K.V. Identification to be performed in the

S.I. W.I. M.I. VGS gm/ID 1/nUT

For L, VS and VDS

Isu (specific current)

VGS " VTo = VP # q n ! !

IDu (VGS ) = ISu (VGS ) i (A)

2 " ISu = 2nUT oCox # (i) 14 4 2 3 I Suo

mobility degradation factor For L, VS and VDS

Verification : Iu(VGS) reconstruction

n,VTo and ISuo

mob. degradation VDS = 0.6 V VSB = 0 V L = 100 nm

BWRC, Dec 12, 2008. P.G.A. Jespers

BWRC, Dec 12, 2008. P.G.A. Jespers

fT = 1 GHz; Co = 1 pf; L = 120 nm; VS = 0; VDS = 0.6 V;