lpc1763 lpc1764 lpc1765 lpc1766 lpc1767 lpc1768 lpc1769

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LPC1769/68/67/66/65/64/63
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32-bit ARM Cortex-M3 microcontroller; up to 512 kB flash and 64 kB SRAM with Ethernet, USB 2.0 Host/Device/OTG, CAN
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Rev. 6.01 11 March 2011
Product data sheet

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1. General description
The LPC1769/68/67/66/65/64/63 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration. The LPC1768/67/66/65/64/63 operate at CPU frequencies of up to 100 MHz. The LPC1769 operates at CPU frequencies of up to 120 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals. The ARM Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branching. The peripheral complement of the LPC1769/68/67/66/65/64/63 includes up to 512 kB of flash memory, up to 64 kB of data memory, Ethernet MAC, USB Device/Host/OTG interface, 8-channel general purpose DMA controller, 4 UARTs, 2 CAN channels, 2 SSP controllers, SPI interface, 3 I2C-bus interfaces, 2-input plus 2-output I2S-bus interface, 8-channel 12-bit ADC, 10-bit DAC, motor control PWM, Quadrature Encoder interface, four general purpose timers, 6-output general purpose PWM, ultra-low power Real-Time Clock (RTC) with separate battery supply, and up to 70 general purpose I/O pins. The LPC1769/68/67/66/65/64/63 are pin-compatible to the 100-pin LPC236x ARM7-based microcontroller series.
2. Features and benefits

ARM Cortex-M3 processor, running at frequencies of up to 100 MHz (LPC1768/67/66/65/64/63) or of up to 120 MHz (LPC1769). A Memory Protection Unit (MPU) supporting eight regions is included. ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC). Up to 512 kB on-chip flash programming memory. Enhanced flash memory accelerator enables high-speed 120 MHz operation with zero wait states. In-System Programming (ISP) and In-Application Programming (IAP) via on-chip bootloader software. On-chip SRAM includes: 32/16 kB of SRAM on the CPU with local code/data bus for high-performance CPU access.
NXP Semiconductors
LPC1769/68/67/66/65/64/63
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32-bit ARM Cortex-M3 microcontroller

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Two/one 16 kB SRAM blocks with separate access paths for higher throughput. These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as for general purpose CPU instruction and data storage. Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer matrix that can be used with SSP, I2S-bus, UART, Analog-to-Digital and Digital-to-Analog converter peripherals, timer match signals, and for memory-to-memory transfers. Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and the USB interface. This interconnect provides communication with no arbitration delays. Split APB bus allows high throughput with few stalls between the CPU and DMA. Serial interfaces: Ethernet MAC with RMII interface and dedicated DMA controller. (Not available on all parts, see Table 2.) USB 2.0 full-speed device/Host/OTG controller with dedicated DMA controller and on-chip PHY for device, Host, and OTG functions. (Not available on all parts, see Table 2.) Four UARTs with fractional baud rate generation, internal FIFO, and DMA support. One UART has modem control I/O and RS-485/EIA-485 support, and one UART has IrDA support. CAN 2.0B controller with two channels. (Not available on all parts, see Table 2.) SPI controller with synchronous, serial, full duplex communication and programmable data length. Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces can be used with the GPDMA controller. Three enhanced I2C bus interfaces, one with an open-drain output supporting full I2C specification and Fast mode plus with data rates of 1 Mbit/s, two with standard port pins. Enhancements include multiple address recognition and monitor mode. I2S (Inter-IC Sound) interface for digital audio input or output, with fractional rate control. The I2S-bus interface can be used with the GPDMA. The I2S-bus interface supports 3-wire and 4-wire data transmit and receive as well as master clock input/output. (Not available on all parts, see Table 2.) Other peripherals: 70 (100 pin package) General Purpose I/O (GPIO) pins with configurable pull-up/down resistors. All GPIOs support a new, configurable open-drain operating mode. The GPIO block is accessed through the AHB multilayer bus for fast access and located in memory such that it supports Cortex-M3 bit banding and use by the General Purpose DMA Controller. 12-bit Analog-to-Digital Converter (ADC) with input multiplexing among eight pins, conversion rates up to 200 kHz, and multiple result registers. The 12-bit ADC can be used with the GPDMA controller. 10-bit Digital-to-Analog Converter (DAC) with dedicated conversion timer and DMA support. (Not available on all parts, see Table 2) Four general purpose timers/counters, with a total of eight capture inputs and ten compare outputs. Each timer block has an external count input. Specific timer events can be selected to generate DMA requests. One motor control PWM with support for three-phase motor control.
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LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers.
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Product data sheet
Rev. 6.01 11 March 2011
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Quadrature encoder interface that can monitor one external quadrature encoder. One standard PWM/timer block with external count input. RTC with a separate power domain and dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. ARM Cortex-M3 system tick timer, including an external clock input option. Repetitive interrupt timer provides programmable and repeating timed interrupts. Each peripheral has its own clock divider for further power savings. Standard JTAG test/debug interface for compatibility with existing tools. Serial Wire Debug and Serial Wire Trace Port options. Emulation trace module enables non-intrusive, high-speed real-time tracing of instruction execution. Integrated PMU (Power Management Unit) automatically adjusts internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down. Single 3.3 V power supply (2.4 V to 3.6 V). Four external interrupt inputs configurable as edge/level sensitive. All pins on Port 0 and Port 2 can be used as edge sensitive interrupt sources. Non-maskable Interrupt (NMI) input. Clock output function that can reflect the main oscillator clock, IRC clock, RTC clock, CPU clock, and the USB clock. The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any priority interrupt that can occur while the clocks are stopped in deep sleep, Power-down, and Deep power-down modes. Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, Port 0/2 pin interrupt, and NMI). Brownout detect with separate threshold for interrupt and forced reset. Power-On Reset (POR). Crystal oscillator with an operating range of 1 MHz to 25 MHz. 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as a system clock. PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. USB PLL for added flexibility. Code Read Protection (CRP) with different security levels. Unique device serial number for identification purposes. Available as 100-pin LQFP (14 mm 14 mm 1.4 mm) and TFBGA1 (9 mm 9 mm 0.7 mm) package.
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1.
LPC1768 only.
All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
LPC1769_68_67_66_65_64_63
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3. Applications
eMetering Lighting Industrial networking Alarm systems White goods Motor control
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4. Ordering information
Table 1. Ordering information Package Name LPC1769FBD100 LPC1768FBD100 LPC1768FET100 LPC1767FBD100 LPC1766FBD100 LPC1765FBD100 LPC1764FBD100 LPC1763FBD100 LQFP100 LQFP100 TFBGA100 LQFP100 LQFP100 LQFP100 LQFP100 LQFP100 Description plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm plastic low profile quad flat package; 100 leads; body 14 14 1.4 mm Version SOT407-1 SOT407-1 SOT407-1 SOT407-1 SOT407-1 SOT407-1 SOT407-1 Type number
plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm SOT926-1
4.1 Ordering options

Table 2. Ordering options Flash SRAM in kB CPU AHB AHB Total SRAM0 SRAM1 LPC1769FBD100 512 kB 32 LPC1768FBD100 512 kB 32 LPC1768FET100 512 kB 32 LPC1767FBD100 512 kB 32 LPC1766FBD100 256 kB 32 LPC1765FBD100 256 kB 32 LPC1764FBD100 128 kB 16 LPC1763FBD100 256 kB 32 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 64 64 64 64 64 64 32 64 yes yes yes yes yes no yes no Device/Host/OTG 2 Device/Host/OTG 2 Device/Host/OTG 2 no no Device/Host/OTG 2 Device/Host/OTG 2 Device only no 2 no yes yes yes yes yes yes no yes Ethernet USB CAN I2S DAC Maximum CPU operating frequency yes yes yes yes yes yes no yes 120 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz 100 MHz Type number
LPC1769_68_67_66_65_64_63
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 6.01 11 March 2011
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5. Block diagram
debug port JTAG interface
XTAL1 XTAL2 RESET
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RMII pins
USB pins
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EMULATION TRACE MODULE
TEST/DEBUG INTERFACE ARM CORTEX-M3
LPC1769/68/67/ 66/65/64/63
ETHERNET CONTROLLER WITH DMA(1) master
USB PHY CLOCK GENERATION, POWER CONTROL, SYSTEM FUNCTIONS clocks and controls CLKOUT
DMA CONTROLLER master
USB HOST/ DEVICE/OTG CONTROLLER WITH DMA(1) master slave
I-code bus
D-code bus
system bus
MPU
ROM slave MULTILAYER AHB MATRIX SRAM 32/64 kB
P0 to P4
HIGH-SPEED GPIO
slave
slave AHB TO APB BRIDGE 0
slave AHB TO APB BRIDGE 1
slave
FLASH ACCELERATOR FLASH 512/256/128 kB
SCK1 SSEL1 MISO1 MOSI1 RXD0/TXD0 8 UART1 RD1/2 TD1/2 SCL0/1 SDA0/1 SCK/SSEL MOSI/MISO 2 MAT0/1 2 CAP0/1
APB slave group 0 SSP1
APB slave group 1 SSP0
SCK0 SSEL0 MISO0 MOSI0 RXD2/3 TXD2/3 3 I2SRX 3 I2STX TX_MCLK RX_MCLK SCL2 SDA2 4 MAT2 2 MAT3 2 CAP2 2 CAP3 EINT[3:0]
UART0/1 CAN1/2(1) I2C0/1 SPI0 TIMER 0/1 WDT
UART2/3
I2S(1)
I2C2 RI TIMER TIMER2/3 EXTERNAL INTERRUPTS SYSTEM CONTROL MOTOR CONTROL PWM DAC(1) QUADRATURE ENCODER
PWM1[7:0] PCAP1[1:0] AD0[7:0]
PWM1 12-bit ADC PIN CONNECT
P0, P2 RTCX1 RTCX2 VBAT
GPIO INTERRUPT CONTROL 32 kHz OSCILLATOR RTC
MCOA[2:0] MCOB[2:0] MCI[2:0] MCABORT AOUT PHA, PHB INDEX
BACKUP REGISTERS RTC POWER DOMAIN

= connected to DMA
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(1) Not available on all parts. See Table 2.
Fig 1.
Block diagram
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6. Pinning information
6.1 Pinning
100 76
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75
LPC176xFBD100
25 26 50 2 3 4 5 6 7
51
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Fig 2.
Pin configuration LQFP100 package
ball A1 index area 1 A B C D E F G H J K
LPC1768FET100
8 9 10
002aaf723
Transparent top view
Fig 3. Table 3. Row A 1 5 9 TDO/SWO P1[10]/ENET_RXD1 P0[7]/I2STX_CLK/ SCK1/MAT2[1] TMS/SWDIO 2 6 10 Pin allocation table
Pin configuration TFBGA100 package
Pin Symbol
Pin Symbol P0[3]/RXD0/AD0[6] P1[16]/ENET_MDC P0[9]/I2STX_SDA/ MOSI1/MAT2[3] RTCK
Pin Symbol 3 7 11 VDD(3V3) VDD(REG)(3V3) -
Pin Symbol 4 8 12 P1[4]/ENET_TX_EN P0[4]/I2SRX_CLK/ RD2/CAP2[0] -
Row B 1 2 3 VSS 4 P1[1]/ENET_TXD1
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Product data sheet
Rev. 6.01 11 March 2011
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Table 3. 5 9 1 5 9 1 5 9
Pin allocation table continued Pin Symbol 6 10 2 6 10 2 6 10 P1[17]/ ENET_MDIO P2[1]/PWM1[2]/RXD1 TRST P1[15]/ ENET_REF_CLK VDD(3V3) P0[25]/AD0[2]/ I2SRX_SDA/TXD3 P1[14]/ENET_RX_ER P2[5]/PWM1[6]/ DTR1/TRACEDATA[0] VDDA P4[29]/TX_MCLK/ MAT2[1]/RXD3 P2[8]/TD2/TXD2 RTCX1 P0[18]/DCD1/ MOSI0/MOSI P0[15]/TXD1/ SCK0/SCK VBAT P1[29]/MCOB2/ PCAP1[1]/MAT0[1] P0[19]/DSR1/SDA1 XTAL1 VDD(REG)(3V3) P0[22]/RTS1/TD1 Pin Symbol 7 11 3 7 11 3 7 11 VSS TDI P4[28]/RX_MCLK/ MAT2[0]/TXD3 P0[26]/AD0[3]/ AOUT/RXD3 P0[5]/I2SRX_WS/ TD2/CAP2[1] Pin Symbol 8 12 4 8 12 4 8 12
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Pin Symbol P1[9]/ENET_RXD0 P2[0]/PWM1[1]/TXD1 TCK/SWDCLK P1[8]/ENET_CRS VSS P0[24]/AD0[1]/ I2SRX_WS/CAP3[1] P1[0]/ENET_TXD0 P2[4]/PWM1[5]/ DSR1/TRACEDATA[1] VSSA P0[23]/AD0[0]/ I2SRX_CLK/CAP3[0] P2[7]/RD2/RTS1 VREFN P1[21]/MCABORT/ PWM1[3]/SSEL0 P0[17]/CTS1/ MISO0/MISO RTCX2 P1[25]/MCOA1/ MAT1[1] P0[20]/DTR1/SCL1 P1[30]/VBUS/ AD0[4] P1[24]/MCI2/ PWM1[5]/MOSI0 VDD(3V3)
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P0[6]/I2SRX_SDA/ SSEL1/MAT2[0] -
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Row C P0[2]/TXD0/AD0[7] P0[8]/I2STX_WS/ MISO1/MAT2[2] n.c. P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] -
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Row E 1 5 9 1 5 9 2 6 10 2 6 10 3 7 11 3 7 11 VREFP P2[3]/PWM1[4]/ DCD1/TRACEDATA[2] RESET P2[9]/USB_CONNECT/ RXD2 4 8 12 4 8 12 n.c. P2[6]/PCAP1[0]/ RI1/TRACECLK P1[31]/SCK1/ AD0[5] P0[16]/RXD1/ SSEL0/SSEL -
Row F
Row G 1 5 9 1 5 9 2 6 10 2 6 10 3 7 11 3 7 11 XTAL2 VSS P3[25]/MAT0[0]/ PWM1[2] P0[10]/TXD2/ SDA2/MAT3[0] 4 8 12 4 8 12 P0[30]/USB_D P0[21]/RI1/RD1 P1[18]/USB_UP_LED/ PWM1[1]/CAP1[0] P2[11]/EINT1/ I2STX_CLK -
Row H
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Table 3. Row J 1
Pin allocation table continued Pin Symbol 2 P0[27]/SDA0/ USB_SDA VSS Pin Symbol 3 P0[29]/USB_D+ Pin Symbol 4
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Pin Symbol P0[28]/SCL0/ USB_SCL P1[22]/MCOB0/ USB_PWRD/ MAT1[0] P2[13]/EINT3/ I2STX_SDA P3[26]/STCLK/ MAT0[1]/PWM1[3] P1[23]/MCI1/ PWM1[4]/MISO0 P0[11]/RXD2/ SCL2/MAT3[1]
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P1[19]/MCOA0/ USB_PPWR/ CAP1[1]
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P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] -
P0[1]/TD1/RXD3/SCL1
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P2[10]/EINT0/NMI
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12
Row K 1 5 2 6 VDD(3V3) P1[26]/MCOB1/ PWM1[6]/CAP0[0] P2[12]/EINT2/ I2STX_WS 3 7 VSS P1[27]/CLKOUT /USB_OVRCR/ CAP0[1] 4 8 P1[20]/MCI0/ PWM1[2]/SCK0 P0[0]/RD1/TXD3/SDA1
10
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6.2 Pin description

Table 4. Symbol P0[0] to P0[31] Pin description Pin Ball Type I/O Description Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0] General purpose digital input/output pin. RD1 CAN1 receiver input. (LPC1769/68/66/65/64 only). TXD3 Transmitter output for UART3. SDA1 I2C1 data input/output. (This is not an I2C-bus compliant open-drain pin). P0[1] General purpose digital input/output pin. TD1 CAN1 transmitter output. (LPC1769/68/66/65/64 only). RXD3 Receiver input for UART3. SCL1 I2C1 clock input/output. (This is not an I2C-bus compliant open-drain pin). P0[2] General purpose digital input/output pin. TXD0 Transmitter output for UART0. AD0[7] A/D converter 0, input 7. P0[3] General purpose digital input/output pin. RXD0 Receiver input for UART0. AD0[6] A/D converter 0, input 6.
P0[0]/RD1/TXD3/ SDA1
46[1]
K8[1]
I/O I O I/O
P0[1]/TD1/RXD3/ SCL1
47[1]
J8[1]
I/O O I I/O
P0[2]/TXD0/AD0[7] 98[2]
C4[2]
I/O O I
P0[3]/RXD0/AD0[6]
99[2]
A2[2]
I/O I I
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Table 4. Symbol
Pin description continued Pin 81[1] Ball A8[1] Type I/O I/O Description P0[4] General purpose digital input/output pin.
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P0[4]/ I2SRX_CLK/ RD2/CAP2[0]
I2SRX_CLK Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). RD2 CAN2 receiver input. (LPC1769/68/66/65/64 only). CAP2[0] Capture input for Timer 2, channel 0. P0[5] General purpose digital input/output pin. I2SRX_WS Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). TD2 CAN2 transmitter output. (LPC1769/68/66/65/64 only). CAP2[1] Capture input for Timer 2, channel 1. P0[6] General purpose digital input/output pin. I2SRX_SDA Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). SSEL1 Slave Select for SSP1. MAT2[0] Match output for Timer 2, channel 0. P0[7] General purpose digital input/output pin.
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I I P0[5]/ I2SRX_WS/ TD2/CAP2[1] 80[1] D7[1] I/O I/O
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O I P0[6]/ I2SRX_SDA/ SSEL1/MAT2[0] 79[1] B8[1] I/O I/O
I/O O P0[7]/ I2STX_CLK/ SCK1/MAT2[1] 78[1] A9[1] I/O I/O
I2STX_CLK Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). SCK1 Serial Clock for SSP1. MAT2[1] Match output for Timer 2, channel 1. P0[8] General purpose digital input/output pin. I2STX_WS Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). MISO1 Master In Slave Out for SSP1. MAT2[2] Match output for Timer 2, channel 2. P0[9] General purpose digital input/output pin. I2STX_SDA Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). MOSI1 Master Out Slave In for SSP1. MAT2[3] Match output for Timer 2, channel 3. P0[10] General purpose digital input/output pin. TXD2 Transmitter output for UART2. SDA2 I2C2 data input/output (this is not an open-drain pin). MAT3[0] Match output for Timer 3, channel 0. P0[11] General purpose digital input/output pin. RXD2 Receiver input for UART2. SCL2 I2C2 clock input/output (this is not an open-drain pin). MAT3[1] Match output for Timer 3, channel 1.
I/O O P0[8]/ I2STX_WS/ MISO1/MAT2[2] 77[1] C8[1] I/O I/O
I/O O P0[9]/ I2STX_SDA/ MOSI1/MAT2[3] 76[1] A10[1] I/O I/O
I/O O P0[10]/TXD2/ SDA2/MAT3[0] 48[1] H7[1] I/O O I/O O P0[11]/RXD2/ SCL2/MAT3[1] 49[1] K9[1] I/O I I/O O
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Table 4. Symbol
Pin description continued Pin 62[1] Ball F10[1] Type I/O O I/O I/O Description P0[15] General purpose digital input/output pin. TXD1 Transmitter output for UART1. SCK0 Serial clock for SSP0. SCK Serial clock for SPI. P0[16] General purpose digital input/output pin. RXD1 Receiver input for UART1. SSEL0 Slave Select for SSP0. SSEL Slave Select for SPI. P0[17] General purpose digital input/output pin. CTS1 Clear to Send input for UART1. MISO0 Master In Slave Out for SSP0. MISO Master In Slave Out for SPI. P0[18] General purpose digital input/output pin. DCD1 Data Carrier Detect input for UART1. MOSI0 Master Out Slave In for SSP0. MOSI Master Out Slave In for SPI. P0[19] General purpose digital input/output pin. DSR1 Data Set Ready input for UART1.
R A FT D
R A F D
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P0[15]/TXD1/ SCK0/SCK
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P0[16]/RXD1/ SSEL0/SSEL
63[1]
F8[1]
I/O I I/O I/O
P0[17]/CTS1/ MISO0/MISO
61[1]
F9[1]
I/O I I/O I/O
P0[18]/DCD1/ MOSI0/MOSI
60[1]
F6[1]
I/O I I/O I/O
P0[19]/DSR1/ SDA1
59[1]
G10[1]
I/O I I/O
SDA1 I2C1 data input/output (this is not an I2C-bus compliant open-drain pin). P0[20] General purpose digital input/output pin. DTR1 Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. SCL1 I2C1 clock input/output (this is not an I2C-bus compliant open-drain pin). P0[21] General purpose digital input/output pin. RI1 Ring Indicator input for UART1. RD1 CAN1 receiver input. (LPC1769/68/66/65/64 only). P0[22] General purpose digital input/output pin. RTS1 Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. TD1 CAN1 transmitter output. (LPC1769/68/66/65/64 only). P0[23] General purpose digital input/output pin. AD0[0] A/D converter 0, input 0. I2SRX_CLK Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). CAP3[0] Capture input for Timer 3, channel 0.
P0[20]/DTR1/SCL1 58[1]
G9[1]
I/O O I/O
P0[21]/RI1/RD1
57[1]
G8[1]
I/O I I
P0[22]/RTS1/TD1
56[1]
H10[1]
I/O O O
P0[23]/AD0[0]/ I2SRX_CLK/ CAP3[0]
9[2]
E5[2]
I/O I I/O
LPC1769_68_67_66_65_64_63
Product data sheet
Rev. 6.01 11 March 2011
10 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
Table 4. Symbol
Pin description continued Pin 8[2] Ball D1[2] Type I/O I I/O Description P0[24] General purpose digital input/output pin. AD0[1] A/D converter 0, input 1.
R A FT D
R A F D
A FT
P0[24]/AD0[1]/ I2SRX_WS/ CAP3[1]
I2SRX_WS Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). CAP3[1] Capture input for Timer 3, channel 1. P0[25] General purpose digital input/output pin. AD0[2] A/D converter 0, input 2.
R A FT D R
A FT D A FT D R A
I P0[25]/AD0[2]/ I2SRX_SDA/ TXD3 7[2] D2[2] I/O I I/O
I2SRX_SDA Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). TXD3 Transmitter output for UART3. P0[26] General purpose digital input/output pin. AD0[3] A/D converter 0, input 3. AOUT DAC output (LPC1769/68/67/66/65/63 only). RXD3 Receiver input for UART3. P0[27] General purpose digital input/output pin. Output is open-drain. SDA0 I2C0 data input/output. Open-drain output (for I2C-bus compliance). USB_SDA USB port I2C serial data (OTG transceiver, LPC1769/68/66/65 only). P0[28] General purpose digital input/output pin. Output is open-drain. SCL0 I2C0 clock input/output. Open-drain output (for I2C-bus compliance). USB_SCL USB port I2C serial clock (OTG transceiver, LPC1769/68/66/65 only). P0[29] General purpose digital input/output pin. USB_D+ USB bidirectional D+ line. (LPC1769/68/66/65/64 only). P0[30] General purpose digital input/output pin. USB_D USB bidirectional D line. (LPC1769/68/66/65/64 only). Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0] General purpose digital input/output pin. ENET_TXD0 Ethernet transmit data 0. (LPC1769/68/67/66/64 only). P1[1] General purpose digital input/output pin. ENET_TXD1 Ethernet transmit data 1. (LPC1769/68/67/66/64 only). P1[4] General purpose digital input/output pin. ENET_TX_EN Ethernet transmit data enable. (LPC1769/68/67/66/64 only). P1[8] General purpose digital input/output pin. ENET_CRS Ethernet carrier sense. (LPC1769/68/67/66/64 only).
O P0[26]/AD0[3]/ AOUT/RXD3 6[3] D3[3] I/O I O I P0[27]/SDA0/ USB_SDA 25[4] J2[4] I/O I/O I/O P0[28]/SCL0/ USB_SCL 24[4] J1[4] I/O I/O I/O P0[29]/USB_D+ P0[30]/USB_D P1[0] to P1[31] 29[5] 30[5] J3[5] G4[5] I/O I/O I/O I/O I/O
P1[0]/ ENET_TXD0 P1[1]/ ENET_TXD1 P1[4]/ ENET_TX_EN P1[8]/ ENET_CRS

LPC1769_68_67_66_65_64_63
95[1] 94[1] 93[1]
D5[1] B4[1] A4[1]
I/O O I/O O I/O O
92[1]
C5[1]
I/O I
Product data sheet
Rev. 6.01 11 March 2011
11 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
Table 4. Symbol
Pin description continued Pin 91[1] 90[1] 89[1] 88[1] Ball B5[1] A5[1] D6[1] C6[1] Type I/O I I/O I I/O I I/O I 87[1] 86[1] A6[1] B6[1] I/O O I/O I/O 32[1] H4[1] I/O O Description P1[9] General purpose digital input/output pin. P1[10] General purpose digital input/output pin. P1[14] General purpose digital input/output pin.
R A FT D
R A F D
A FT
P1[9]/ ENET_RXD0 P1[10]/ ENET_RXD1 P1[14]/ ENET_RX_ER P1[15]/ ENET_REF_CLK P1[16]/ ENET_MDC P1[17]/ ENET_MDIO P1[18]/ USB_UP_LED/ PWM1[1]/ CAP1[0]
ENET_RXD0 Ethernet receive data. (LPC1769/68/67/66/64 only).
ENET_RXD1 Ethernet receive data. (LPC1769/68/67/66/64 only). ENET_RX_ER Ethernet receive error. (LPC1769/68/67/66/64 only). P1[15] General purpose digital input/output pin. ENET_REF_CLK Ethernet reference clock. (LPC1769/68/67/66/64 only). P1[16] General purpose digital input/output pin. ENET_MDC Ethernet MIIM clock (LPC1769/68/67/66/64 only). P1[17] General purpose digital input/output pin. ENET_MDIO Ethernet MIIM data input and output. (LPC1769/68/67/66/64 only). P1[18] General purpose digital input/output pin. USB_UP_LED USB GoodLink LED indicator. It is LOW when device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. (LPC1769/68/66/65/64 only). PWM1[1] Pulse Width Modulator 1, channel 1 output. CAP1[0] Capture input for Timer 1, channel 0. P1[19] General purpose digital input/output pin. MCOA0 Motor control PWM channel 0, output A. USB_PPWR Port Power enable signal for USB port. (LPC1769/68/66/65 only). CAP1[1] Capture input for Timer 1, channel 1. P1[20] General purpose digital input/output pin. MCI0 Motor control PWM channel 0, input. Also Quadrature Encoder Interface PHA input. PWM1[2] Pulse Width Modulator 1, channel 2 output. SCK0 Serial clock for SSP0. P1[21] General purpose digital input/output pin. MCABORT Motor control PWM, LOW-active fast abort. PWM1[3] Pulse Width Modulator 1, channel 3 output. SSEL0 Slave Select for SSP0. P1[22] General purpose digital input/output pin. MCOB0 Motor control PWM channel 0, output B. USB_PWRD Power Status for USB port (host power switch, LPC1769/68/66/65 only). MAT1[0] Match output for Timer 1, channel 0.
R A FT D R
A FT D A FT D R A
O I P1[19]/MCOA0/ USB_PPWR/ CAP1[1] 33[1] J4[1] I/O O O I P1[20]/MCI0/ PWM1[2]/SCK0 34[1] K4[1] I/O I O I/O P1[21]/MCABORT/ 35[1] PWM1[3]/ SSEL0 F5[1] I/O O O I/O P1[22]/MCOB0/ USB_PWRD/ MAT1[0] 36[1] J5[1] I/O O I O
LPC1769_68_67_66_65_64_63
Product data sheet
Rev. 6.01 11 March 2011
12 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
Table 4. Symbol
Pin description continued Pin 37[1] Ball K5[1] Type I/O I O I/O Description P1[23] General purpose digital input/output pin.
R A FT D
R A F D
A FT
P1[23]/MCI1/ PWM1[4]/MISO0
R A FT D R
A FT
MCI1 Motor control PWM channel 1, input. Also Quadrature Encoder Interface PHB input. PWM1[4] Pulse Width Modulator 1, channel 4 output. MISO0 Master In Slave Out for SSP0. P1[24] General purpose digital input/output pin. MCI2 Motor control PWM channel 2, input. Also Quadrature Encoder Interface INDEX input. PWM1[5] Pulse Width Modulator 1, channel 5 output. MOSI0 Master Out Slave in for SSP0. P1[25] General purpose digital input/output pin. MCOA1 Motor control PWM channel 1, output A. MAT1[1] Match output for Timer 1, channel 1. P1[26] General purpose digital input/output pin. MCOB1 Motor control PWM channel 1, output B. PWM1[6] Pulse Width Modulator 1, channel 6 output. CAP0[0] Capture input for Timer 0, channel 0. P1[27] General purpose digital input/output pin. CLKOUT Clock output pin.
D A FT D R A
P1[24]/MCI2/ PWM1[5]/MOSI0
38[1]
H5[1]
I/O I O I/O
P1[25]/MCOA1/ MAT1[1] P1[26]/MCOB1/ PWM1[6]/CAP0[0]
39[1]
G5[1]
I/O O O
40[1]
K6[1]
I/O O O I
P1[27]/CLKOUT /USB_OVRCR/ CAP0[1]
43[1]
K7[1]
I/O O I I
USB_OVRCR USB port Over-Current status. (LPC1769/68/66/65 only). CAP0[1] Capture input for Timer 0, channel 1. P1[28] General purpose digital input/output pin. MCOA2 Motor control PWM channel 2, output A. PCAP1[0] Capture input for PWM1, channel 0. MAT0[0] Match output for Timer 0, channel 0. P1[29] General purpose digital input/output pin. MCOB2 Motor control PWM channel 2, output B. PCAP1[1] Capture input for PWM1, channel 1. MAT0[1] Match output for Timer 0, channel 1. P1[30] General purpose digital input/output pin. VBUS Monitors the presence of USB bus power. (LPC1769/68/66/65/64 only). Note: This signal must be HIGH for USB reset to occur. AD0[4] A/D converter 0, input 4. P1[31] General purpose digital input/output pin. SCK1 Serial Clock for SSP1. AD0[5] A/D converter 0, input 5. Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available.
P1[28]/MCOA2/ PCAP1[0]/ MAT0[0]
44[1]
J7[1]
I/O O I O
P1[29]/MCOB2/ PCAP1[1]/ MAT0[1]
45[1]
G6[1]
I/O O I O
P1[30]/VBUS/ AD0[4]
21[2]
H1[2]
I/O I
I P1[31]/SCK1/ AD0[5] P2[0] to P2[31] 20[2] F4[2] I/O I/O I I/O
LPC1769_68_67_66_65_64_63
Product data sheet
Rev. 6.01 11 March 2011
13 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
Table 4. Symbol
Pin description continued Pin 75[1] Ball B9[1] Type I/O O O 74[1] B10[1] I/O O I 73[1] D8[1] I/O O I O 70[1] E7[1] I/O O I O 69[1] D9[1] I/O O I O 68[1] D10[1] I/O O O O Description P2[0] General purpose digital input/output pin.
R A FT D
R A F D
A FT
P2[0]/PWM1[1]/ TXD1 P2[1]/PWM1[2]/ RXD1 P2[2]/PWM1[3]/ CTS1/ TRACEDATA[3]
R A FT
A FT
PWM1[1] Pulse Width Modulator 1, channel 1 output. TXD1 Transmitter output for UART1. P2[1] General purpose digital input/output pin. PWM1[2] Pulse Width Modulator 1, channel 2 output. RXD1 Receiver input for UART1. P2[2] General purpose digital input/output pin. PWM1[3] Pulse Width Modulator 1, channel 3 output. CTS1 Clear to Send input for UART1. TRACEDATA[3] Trace data, bit 3. P2[3] General purpose digital input/output pin. PWM1[4] Pulse Width Modulator 1, channel 4 output. DCD1 Data Carrier Detect input for UART1. TRACEDATA[2] Trace data, bit 2. P2[4] General purpose digital input/output pin. PWM1[5] Pulse Width Modulator 1, channel 5 output. DSR1 Data Set Ready input for UART1. TRACEDATA[1] Trace data, bit 1. P2[5] General purpose digital input/output pin. PWM1[6] Pulse Width Modulator 1, channel 6 output. DTR1 Data Terminal Ready output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. TRACEDATA[0] Trace data, bit 0. P2[6] General purpose digital input/output pin. PCAP1[0] Capture input for PWM1, channel 0. RI1 Ring Indicator input for UART1. TRACECLK Trace Clock. P2[7] General purpose digital input/output pin. RD2 CAN2 receiver input. (LPC1769/68/66/65/64 only).
D R A FT D
R A
P2[3]/PWM1[4]/ DCD1/ TRACEDATA[2]
P2[4]/PWM1[5]/ DSR1/ TRACEDATA[1]
P2[5]/PWM1[6]/ DTR1/ TRACEDATA[0]
P2[6]/PCAP1[0]/ RI1/TRACECLK
67[1]
E8[1]
I/O I I O
P2[7]/RD2/ RTS1
66[1]
E9[1]
I/O I O
RTS1 Request to Send output for UART1. Can also be configured to be an RS-485/EIA-485 output enable signal. P2[8] General purpose digital input/output pin. TD2 CAN2 transmitter output. (LPC1769/68/66/65/64 only). TXD2 Transmitter output for UART2. P2[9] General purpose digital input/output pin. USB_CONNECT Signal used to switch an external 1.5 k resistor under software control. Used with the SoftConnect USB feature. (LPC1769/68/66/65/64 only). RXD2 Receiver input for UART2.
P2[8]/TD2/ TXD2 P2[9]/ USB_CONNECT/ RXD2
65[1]
E10[1]
I/O O O
64[1]
F7[1]
I/O O
LPC1769_68_67_66_65_64_63
Product data sheet
Rev. 6.01 11 March 2011
14 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
Table 4. Symbol
Pin description continued Pin 53[6] Ball J10[6] Type I/O I I Description
R A FT D
R A F D
A FT
P2[10]/EINT0/NMI
P2[10] General purpose digital input/output pin. A LOW level on this pin during reset starts the ISP command handler.
FT D
FT
EINT0 External interrupt 0 input. NMI Non-maskable interrupt input. P2[11] General purpose digital input/output pin. EINT1 External interrupt 1 input.
R A FT D
P2[11]/EINT1/ I2STX_CLK
52[6]
H8[6]
I/O I I/O
R A
I2STX_CLK Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[12] General purpose digital input/output pin. EINT2 External interrupt 2 input. I2STX_WS Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). P2[13] General purpose digital input/output pin. EINT3 External interrupt 3 input. I2STX_SDA Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. (LPC1769/68/67/66/65/63 only). Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25] General purpose digital input/output pin. MAT0[0] Match output for Timer 0, channel 0. PWM1[2] Pulse Width Modulator 1, output 2. P3[26] General purpose digital input/output pin. STCLK System tick timer clock input. MAT0[1] Match output for Timer 0, channel 1. PWM1[3] Pulse Width Modulator 1, output 3. Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28] General purpose digital input/output pin. RX_MCLK I2S receive master clock. (LPC1769/68/67/66/65 only). MAT2[0] Match output for Timer 2, channel 0. TXD3 Transmitter output for UART3. P4[29] General purpose digital input/output pin. TX_MCLK I2S transmit master clock. (LPC1769/68/67/66/65 only). MAT2[1] Match output for Timer 2, channel 1. RXD3 Receiver input for UART3. TDO Test Data out for JTAG interface. SWO Serial wire trace output.
P2[12]/EINT2/ I2STX_WS
51[6]
K10[6]
I/O I I/O
P2[13]/EINT3/ I2STX_SDA
50[6]
J9[6]
I/O I I/O
P3[0] to P3[31]
I/O
P3[25]/MAT0[0]/ PWM1[2] P3[26]/STCLK/ MAT0[1]/PWM1[3]
27[1]
H3[1]
I/O O O
26[1]
K1[1]
I/O I O O
P4[0] to P4[31]
I/O
P4[28]/RX_MCLK/ MAT2[0]/TXD3
82[1]
C7[1]
I/O I O O
P4[29]/TX_MCLK/ MAT2[1]/RXD3
85[1]
E6[1]
I/O I O I
TDO/SWO
1[1][7]
A1[1]
O O
LPC1769_68_67_66_65_64_63
Product data sheet
Rev. 6.01 11 March 2011
15 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
Table 4. Symbol TDI
Pin description continued Pin 2[1][8] 3[1][8] 4[1][8] 5[1][7] 100[1][7] 14 17[9] Ball C3[1][8] B1[1][8] C2[1][8] C1[1][7] B2[1][7] F3[9] Type I I I/O I I I O O I Description TDI Test Data in for JTAG interface. TMS Test Mode Select for JTAG interface. SWDIO Serial wire debug data input/output. TRST Test Reset for JTAG interface. TCK Test Clock for JTAG interface. SWDCLK Serial wire clock. RTCK JTAG interface control signal.
R A FT D R
R A F D R A FT
A FT A FT
TMS/SWDIO TRST TCK/SWDCLK RTCK RSTOUT RESET
D R A FT D
R A
RSTOUT This is a 3.3 V pin. LOW on this pin indicates the microcontroller being in Reset state. External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. Input to the oscillator circuit and internal clock generator circuits. Output from the oscillator amplifier. Input to the RTC oscillator circuit. Output from the RTC oscillator circuit. ground: 0 V reference.
XTAL1 XTAL2 RTCX1 RTCX2 VSS
22[10][11] 23[10][11] 16[10][12] 18[10]
H2[10][11] G3[10][11] F2[10][11] G1[10]
I O I O
31, 41, B3, B7, I 55, 72, C9, G7, 83, 97[10] J6, K3[10] 11[10] E1[10] I I
VSSA VDD(3V3)
analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. 3.3 V supply voltage: This is the power supply voltage for the I/O ports. 3.3 V voltage regulator supply voltage: This is the supply voltage for the on-chip voltage regulator only. analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. ADC positive reference voltage: This should be nominally the same voltage as VDDA but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. This pin should be tied to 3.3 V if the ADC and DAC are not used. ADC negative reference voltage: This should be nominally the same voltage as VSS but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. not connected.
28, 54, K2, H9, 71, 96[10] C10, A3[10]
VDD(REG)(3V3) VDDA
42, 84[10] H6, A7[10] I 10[10] E2[10] I
VREFP
12[10]
E3[10]
VREFN
15
F1
VBAT n.c.
[1] [2] [3]
19[10][12] 13
G2[10][12] D4, E4
I -
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant. 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled.
LPC1769_68_67_66_65_64_63
Product data sheet
Rev. 6.01 11 March 2011
16 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
[4]
Open-drain 5 V tolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin.
D R A
D R A
D R A R A FT
R A D R R A FT D D
A FT A FT D R D R A F R
FT
[5] [6] [7] [8] [9]
Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). This pad is not 5 V tolerant.
A FT D
FT D
5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. 5 V tolerant pad with TTL levels and hysteresis. Internal pull-up and pull-down resistors disabled. 5 V tolerant pad with TTL levels and hysteresis and internal pull-up resistor. 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis.
R A FT D R A
[10] Pad provides special analog functionality. [11] When the system oscillator is not used, connect XTAL1 and XTAL2 as follows: XTAL1 can be left floating or can be grounded (grounding is preferred to reduce susceptibility to noise). XTAL2 should be left floating. [12] When the RTC is not used, connect VBAT to VDD(REG)(3V3) and leave RTCX1 floating.
LPC1769_68_67_66_65_64_63
Product data sheet
Rev. 6.01 11 March 2011
17 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
7. Functional description
7.1 Architectural overview
Remark: In the following, the notation LPC17xx refers to all parts: LPC1769/68/67/66/65/64/63.
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus (see Figure 1). The I-code and D-code core buses are faster than the system bus and are used similarly to TCM interfaces: one bus dedicated for instruction fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for simultaneous operations if concurrent operations target different devices. The LPC17xx use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters.
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
7.2 ARM Cortex-M3 processor

The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. The ARM Cortex-M3 offers many new features, including a Thumb-2 instruction set, low interrupt latency, hardware divide, interruptible/continuable multiple load and store instructions, automatic state save and restore for interrupts, tightly integrated interrupt controller with wake-up interrupt controller, and multiple core buses capable of simultaneous accesses. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical Reference Manual that can be found on official ARM website.
7.3 On-chip flash program memory

The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash accelerator maximizes performance for use with the two fast AHB-Lite buses.
7.4 On-chip SRAM

The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main 32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. This architecture allows CPU and DMA accesses to be spread over three separate RAMs that can be accessed simultaneously.
7.5 Memory Protection Unit (MPU)

The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the reliability of an embedded system by protecting critical data within the user application.
LPC1769_68_67_66_65_64_63 All information provided in this document is subject to legal disclaimers. NXP B.V. 2011. All rights reserved.
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The MPU allows separating processing tasks by disallowing access to each other's data, disabling access to memory regions, allowing memory regions to be defined as read-only and detecting unexpected memory accesses that could potentially break the system.
The MPU separates the memory into distinct regions and implements protection by preventing disallowed accesses. The MPU supports up to 8 regions each of which can be divided into 8 subregions. Accesses to memory locations that are not defined in the MPU regions, or not permitted by the region setting, will cause the Memory Management Fault exception to take place.
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7.6 Memory map

The LPC17xx incorporates several distinct memory regions, shown in the following figures. Figure 4 shows the overall map of the entire address space from the user program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals. The APB peripheral area is 1 MB in size and is divided to allow for up to 64 peripherals. Each peripheral of either type is allocated 16 kB of space. This allows simplifying the address decoding for each peripheral.
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xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
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0x4010 0000 0x400F C000 0x400C 0000 0x400B C000 0x400B 8000 0x400B 4000 0x400B 0000 0x400A C000 0x400A 8000 0x400A 4000 0x400A 0000 0x4009 C000 0x4009 8000 0x4009 4000 0x4009 0000 0x4008 C000 0x4008 8000 0x4008 0000 15 14 13 11 10 9 8 7 6 5 4 3 2 31
APB1 peripherals system control 30 - 16 reserved QEI motor control PWM reserved reserved I2S(1) reserved I2C2 UART3 UART2 timer 3 timer 2 DAC(1) SSP0 1 - 0 reserved
4 GB reserved
0xFFFF FFFF 0xE010 0000 private peripheral bus reserved 0x5020 0000 AHB peripherals reserved 0x4400 0000 peripheral bit-band alias addressing reserved APB1 peripherals 0x4200 0000 0x4010 0000 0x4008 0000 0x4000 0000 0x2400 0000 AHB SRAM bit-band alias addressing 0x2200 0000 reserved 0x200A 0000 GPIO reserved 16 kB AHB SRAM1 (LPC1769/8/7/6/5) 0x2009 C000 0x2008 4000 0x2008 0000 0x2007 C000 0x1FFF 2000 0x1FFF 0000 0x1000 8000 0x1000 4000 0x1000 0000 0x0008 0000 512 kB on-chip flash (LPC1769/8/7) 16 kB AHB SRAM0 reserved 8 kB boot ROM reserved 32 kB local SRAM (LPC1769/8/7/6/5/3) 0x5000 0000 0xE000 0000
LPC1769/68/67/66/65/64/63
AHB peripherals 127- 4 reserved 3 2 1 0 USB controller(1) reserved GPDMA controller Ethernet controller(1) 0x5020 0000 0x5001 0000 0x5000 C000 0x5000 8000 0x5000 4000 0x5000 0000
12 repetitive interrupt timer
APB0 peripherals 31 - 24 reserved 23 I2C1 22 - 19 reserved 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAN2(1) CAN1(1) CAN common(1) CAN AF registers(1) CAN AF RAM(1) ADC SSP1 pin connect GPIO interrupts RTC + backup registers SPI reserved PWM1 reserved UART1 UART0 timer 1 timer 0 WDT
0x4008 0000 0x4006 0000 0x4005 C000 0x4004 C000 0x4004 8000 0x4004 4000 0x4004 0000 0x4003 C000
1 GB
APB0 peripherals reserved
LPC1769/68/67/66/65/64/63
0x4003 8000 0x4003 4000 0x4003 0000 0x4002 C000 0x4002 8000 0x4002 4000 0x4002 0000 0x4001 C000 0x4001 8000 0x4001 4000 0x4001 0000 0x4000 C000 0x4000 8000 0x4000 4000 0x4000 0000
002aad946
0.5 GB
D D D D D R R R R R A A A A A FT FT FT FT FT D D D D R R R R A A A A F F F T T T 32-bit ARM Cortex-M3 microcontroller FT D D D D R R R R A A A
I-code/D-code memory space
16 kB local SRAM (LPC1764) reserved
0x0000 0400 0x0000 0000 active interrupt vectors
+ 256 words 0 GB
0x0004 0000 0x0002 0000 0x0000 0000
256 kB on-chip flash (LPC1766/65/63) 128 kB on-chip flash (LPC1764)
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(1) Not available on all parts. See Table 2.
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Fig 4.
LPC17xx memory map
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7.7 Nested Vectored Interrupt Controller (NVIC)
The NVIC is an integral part of the Cortex-M3. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts.
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7.7.1 Features
A FT D
Controls system exceptions and peripheral interrupts In the LPC17xx, the NVIC supports 33 vectored interrupts 32 programmable interrupt priority levels, with hardware priority level masking Relocatable vector table Non-Maskable Interrupt (NMI) Software interrupt generation
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7.7.2 Interrupt sources

Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on Port 0 and Port 2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both.
7.8 Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. Most pins can also be configured as open-drain outputs or to have a pull-up, pull-down, or no resistor enabled.
7.9 General purpose DMA controller

The GPDMA is an AMBA AHB compliant peripheral allowing selected peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. The GPDMA controller allows data transfers between the USB and Ethernet controllers and the various on-chip SRAM areas. The supported APB peripherals are SSP0/1, all UARTs, the I2S-bus interface, the ADC, and the DAC. Two match signals for each timer can be used to trigger DMA transfers. Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The USB controller is available on parts LPC1769/68/66/65/64. The I2S-bus interface is available on parts LPC1769/68/67/66/65. The DAC is available on parts LPC1769/68/67/66/65/63.
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7.9.1 Features
Eight DMA channels. Each channel can support an unidirectional transfer. 16 DMA request lines. Single DMA and burst DMA request signals. Each peripheral connected to the DMA
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Controller can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the DMA Controller. peripheral-to-peripheral transfers are supported.
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Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and Scatter or gather DMA is supported through the use of linked lists. This means that Hardware DMA channel priority. AHB slave DMA programming interface. The DMA Controller is programmed by
writing to the DMA control registers over the AHB slave interface. request goes active. the source and destination areas do not have to occupy contiguous areas of memory.
One AHB bus master for transferring data. The interface transfers data when a DMA 32-bit AHB master bus width. Incrementing or non-incrementing addressing for source and destination. Programmable DMA burst size. The DMA burst size can be programmed to more
efficiently transfer data.
Internal four-word FIFO per channel. Supports 8, 16, and 32-bit wide transactions. Big-endian and little-endian support. The DMA Controller defaults to little-endian
mode on reset.
An interrupt to the processor can be generated on a DMA completion or when a DMA

error has occurred. prior to masking.
Raw interrupt status. The DMA error and DMA count raw interrupt status can be read 7.10 Fast general purpose parallel I/O
Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC17xx use accelerated GPIO functions:
GPIO registers are accessed through the AHB multilayer bus so that the fastest
possible I/O timing can be achieved. unchanged.
Mask registers allow treating sets of port bits as a group, leaving other bits
LPC1769_68_67_66_65_64_63
All GPIO registers are byte and half-word addressable. Entire port value can be written in one instruction. Support for Cortex-M3 bit banding. Support for use with the GPDMA controller.
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Additionally, any pin on Port 0 and Port 2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode.
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7.10.1 Features
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Bit level set and clear registers allow a single instruction to set or clear any number of
bits in one port.
Direction control of individual bits. All I/O default to inputs after reset. Pull-up/pull-down resistor configuration and open-drain configuration can be
programmed through the pin connect block for each GPIO pin.
7.11 Ethernet
Remark: The Ethernet controller is available on parts LPC1769/68/67/66/64. The Ethernet block supports bus clock rates of up to 100 MHz (LPC1768/67/66/64) or 120 MHz (LPC1769). See Table 2. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share the ARM Cortex-M3 D-code and system bus through the AHB-multilayer matrix to access the various on-chip SRAM blocks for Ethernet data, control, and status information. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus.
7.11.1 Features
Ethernet standards support:

Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. Fully compliant with IEEE standard 802.3. Fully compliant with 802.3x full duplex flow control and half duplex back pressure. Flexible transmit and receive frame options. Virtual Local Area Network (VLAN) frame support.
Memory management:
Independent transmit and receive buffers memory mapped to shared SRAM. DMA managers with scatter/gather DMA and arrays of frame descriptors. Memory traffic optimized by buffering and pre-fetching.
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Enhanced Ethernet features:

Receive filtering.
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Multicast and broadcast frame support for both transmit and receive. Optional automatic Frame Check Sequence (FCS) insertion with Cyclic Redundancy Check (CRC) for transmit. Selectable automatic transmit frame padding.
R A FT FT D R A FT D R A D
Over-length frame support for both transmit and receive allows any length frames. Promiscuous receive mode. Automatic collision back-off and frame retransmission. Includes power management by clock switching. Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter.
Physical interface:
Attachment of external PHY chip through standard RMII interface. PHY register access is available via the MIIM interface.
7.12 USB interface

Remark: The USB controller is available as device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764. The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and one or more (up to 127) peripherals. The host controller allocates the USB bandwidth to attached devices through a token-based protocol. The bus supports hot plugging and dynamic configuration of the devices. All transactions are initiated by the host controller. The USB interface includes a device, Host, and OTG controller with on-chip PHY for device and Host functions. The OTG switching protocol is supported through the use of an external controller. Details on typical USB interfacing solutions can be found in Section 14.1.
7.12.1 USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the on-chip SRAM. 7.12.1.1 Features

LPC1769_68_67_66_65_64_63
Fully compliant with USB 2.0 specification (full speed). Supports 32 physical (16 logical) endpoints with a 4 kB endpoint buffer RAM. Supports Control, Bulk, Interrupt and Isochronous endpoints. Scalable realization of endpoints at run time.
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Endpoint Maximum packet size selection (up to USB maximum specification) by

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software at run time.
Supports SoftConnect and GoodLink features. While USB is in the Suspend mode, the part can enter one of the reduced power
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A F R A FT D
FT D D FT
modes and wake up on USB activity.
R A FT D R A
Supports DMA transfers with all on-chip SRAM blocks on all non-control endpoints. Allows dynamic switching between CPU-controlled slave and DMA modes. Double buffer implementation for Bulk and Isochronous endpoints.
7.12.2 USB host controller
The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of a register interface, a serial interface engine, and a DMA controller. The register interface complies with the OHCI specification. 7.12.2.1 Features
OHCI compliant. One downstream port. Supports port power switching.

7.12.3 USB OTG controller
USB OTG is a supplement to the USB 2.0 specification that augments the capability of existing mobile devices and USB peripherals by adding host functionality for connection to USB peripherals. The OTG Controller integrates the host controller, device controller, and a master-only I2C-bus interface to implement OTG dual-role device functionality. The dedicated I2C-bus interface controls an external OTG transceiver. 7.12.3.1 Features
Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision
1.0a.
Hardware support for Host Negotiation Protocol (HNP). Includes a programmable timer required for HNP and Session Request Protocol
(SRP).
Supports any OTG transceiver compliant with the OTG Transceiver Specification
(CEA-2011), Rev. 1.0.
7.13 CAN controller and acceptance filters

Remark: The CAN controllers are available on parts LPC1769/68/66/65/64. See Table 2. The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications.
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7.13.1 Features
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Two CAN controllers and buses. Data rates to 1 Mbit/s on each bus. 32-bit register and RAM access. Compatible with CAN specification 2.0B, ISO 11898-1.
Global Acceptance Filter recognizes standard (11-bit) and extended-frame (29-bit) receive identifiers for all CAN buses. Standard Identifiers.
Acceptance Filter can provide FullCAN-style automatic reception for selected FullCAN messages can generate interrupts. 7.14 12-bit ADC
The LPC17xx contain a single 12-bit successive approximation ADC with eight channels and DMA support.
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7.14.1 Features
12-bit successive approximation ADC. Input multiplexing among 8 pins. Power-down mode. Measurement range VREFN to VREFP. 12-bit conversion rate: 200 kHz. Individual channels can be selected for conversion. Burst conversion mode for single or multiple inputs. Optional conversion on transition of input pin or Timer Match signal. Individual result registers for each ADC channel to reduce interrupt overhead. DMA support.
7.15 10-bit DAC

The DAC allows to generate a variable analog output. The maximum output value of the DAC is VREFP. Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2.
7.15.1 Features

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10-bit DAC Resistor string architecture Buffered output Power-down mode Selectable output drive Dedicated conversion timer DMA support
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7.16 UARTs
The LPC17xx each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface and support for RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz.
FT D R A FT D
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A FT
7.16.1 Features
Maximum UART data bit rate of 6.25 Mbit/s. 16 B Receive and Transmit FIFOs. Register locations conform to 16C550 industry standard. Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. control implementation.
Auto baud capabilities and FIFO control mechanism that enables software flow UART1 equipped with standard modem interface signals. This module also provides
full support for hardware flow control (auto-CTS/RTS).
Support for RS-485/9-bit/EIA-485 mode (UART1). UART3 includes an IrDA mode to support infrared communication. All UARTs have DMA support. 7.17 SPI serial I/O controller
The LPC17xx contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master.
7.17.1 Features
Maximum SPI data bit rate of 12.5 Mbit/s Compliant with SPI specification Synchronous, serial, full duplex communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate 8 bits to 16 bits per transfer
7.18 SSP serial I/O controller

The LPC17xx contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given
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data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data.
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FT
7.18.1 Features
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Maximum SSP speed of 50 Mbit/s (master) or 8 Mbit/s (slave) Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National
Semiconductor Microwire buses Master or slave operation 8-frame FIFOs for both transmit and receive 4-bit to 16-bit frame DMA transfers supported by GPDMA
FT D R A
Synchronous serial communication
7.19 I2C-bus serial I/O controllers

The LPC17xx each contain three I2C-bus controllers. The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and can be controlled by more than one bus master connected to it.
7.19.1 Features
I2C0 is a standard I2C compliant bus interface with open-drain pins. I2C0 also
supports Fast mode plus with bit rates up to 1 Mbit/s.
I2C1 and I2C2 use standard I/O pins with bit rates of up to 400 kbit/s (Fast I2C-bus). Easy to configure as master, slave, or master/slave. Programmable clocks allow versatile rate control. Bidirectional data transfer between masters and slaves. Multi-master bus (no central master). Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. one serial bus.
Serial clock synchronization allows devices with different bit rates to communicate via Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2C-bus can be used for test and diagnostic purposes. All I2C-bus controllers support multiple address recognition and a bus monitor mode.
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7.20 I2S-bus serial I/O controllers
Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2.

FT D
The I2S-bus provides a standard communication interface for digital audio applications.
The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S-bus connection has one master, which is always the master, and one slave. The I2S-bus interface provides a separate transmit and receive channel, each of which can operate as either a master or a slave.
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7.20.1 Features
The interface has separate input/output channels each of which can operate in master
or slave mode.
Capable of handling 8-bit, 16-bit, and 32-bit word sizes. Mono and stereo audio data supported. The sampling frequency can range from 16 kHz to 96 kHz (16, 22.05, 32, 44.1, 48,
96) kHz.
Support for an audio master clock. Configurable word select period in master mode (separately for I2S-bus input and
output).
Two 8-word FIFO data buffers are provided, one for transmit and one for receive. Generates interrupt requests when buffer levels cross a programmable boundary. Two DMA requests, controlled by programmable buffer levels. These are connected
to the GPDMA block.
Controls include reset, stop and mute options separately for I2S-bus input and I2S-bus
output.
7.21 General purpose 32-bit timers/external event counters

The LPC17xx include four 32-bit timer/counters. The timer/counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts, generate timed DMA requests, or perform other actions at specified timer values, based on four match registers. Each timer/counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt.
7.21.1 Features
A 32-bit timer/counter with a programmable 32-bit prescaler. Counter or timer operation. Two 32-bit capture channels per timer, that can take a snapshot of the timer value
when an input signal transitions. A capture event may also generate an interrupt. Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation.
Four 32-bit match registers that allow:
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Up to four external outputs corresponding to match registers, with the following

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capabilities:
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Set LOW on match. Set HIGH on match. Toggle on match. Do nothing on match.
D R A FT D
Up to two match registers can be used to generate timed DMA requests. 7.22 Pulse width modulator
The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC17xx. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge).
7.22.1 Features
One PWM block with Counter or Timer operation (may use the peripheral clock or one
of the capture inputs as the clock source).
Seven match registers allow up to 6 single edge controlled or 3 double edge

Continuous operation with optional interrupt generation on match. Stop timer on match with optional interrupt generation. Reset timer on match with optional interrupt generation.
controlled PWM outputs, or a mix of both types. The match registers also allow:
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Supports single edge controlled and/or double edge controlled PWM outputs. Single
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edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. or negative going pulses.
FT
Pulse period and width can be any number of timer counts. This allows complete
Double edge controlled PWM outputs can be programmed to be either positive going Match register updates are synchronized with pulse outputs to prevent generation of
erroneous pulses. Software must release new match values before they can become effective. if the PWM mode is not enabled.
May be used as a standard 32-bit timer/counter with a programmable 32-bit prescaler 7.23 Motor control PWM
The motor control PWM is a specialized PWM supporting 3-phase motors and other combinations. Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down. An abort input is also provided that causes the PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications.
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7.24 Quadrature Encoder Interface (QEI)

A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals. By monitoring both the number of pulses and the relative phase of the two signals, the user can track the position, direction of rotation, and velocity. In addition, a third channel, or index signal, can be used to reset the position counter. The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation. In addition, the QEI can capture the velocity of the encoder wheel.
7.24.1 Features

LPC1769_68_67_66_65_64_63
Tracks encoder position. Increments/decrements depending on direction. Programmable for 2 or 4 position counting. Velocity capture using built-in timer. Velocity compare function with less than interrupt. Uses 32-bit registers for position and velocity. Three position compare registers with interrupts. Index counter for revolution counting. Index compare register with interrupts. Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement.
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Digital filter with programmable delays for encoder input signals. Can accept decoded signal inputs (clk and direction). Connected to APB. 7.25 Repetitive Interrupt (RI) timer
The repetitive interrupt timer provides a free-running 32-bit counter which is compared to a selectable value, generating an interrupt when a match occurs. Any bits of the timer/compare can be masked such that they do not contribute to the match detection. The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals.
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7.25.1 Features
32-bit counter running from PCLK. Counter can be free-running or be reset by a

generated interrupt.
32-bit compare value. 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple compare.
7.26 ARM Cortex-M3 system tick timer

The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a 10 ms interval. In the LPC17xx, this timer can be clocked from the internal AHB clock or from a device pin.
7.27 Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to feed (or reload) the watchdog within a predetermined amount of time.
7.27.1 Features
Internally resets chip if not periodically reloaded. Debug mode. Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. Flag to indicate watchdog reset. Programmable 32-bit timer with internal prescaler. Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 232 4) in multiples of Tcy(WDCLK) 4. oscillator, the RTC oscillator, or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction
The Watchdog Clock (WDCLK) source can be selected from the Internal RC (IRC)
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conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring for increased reliability.
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Includes lock/safe feature. 7.28 RTC and backup registers
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The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC17xx is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up. When operating from a battery, the RTC will continue working down to 2.1 V. Battery power can be provided from a standard 3 V Lithium button cell. An ultra-low power 32 kHz oscillator will provide a 1 Hz clock to the time counting portion of the RTC, moving most of the power consumption out of the time counting function. The RTC includes a calibration mechanism to allow fine-tuning the count rate in a way that will provide less than 1 second per day error when operated at a constant voltage and temperature. A clock output function (see Section 7.29.4) makes measuring the oscillator rate easy and accurate. The RTC contains a small set of backup registers (20 bytes) for holding data while the main part of the LPC17xx is powered off. The RTC includes an alarm function that can wake up the LPC17xx from all reduced power modes with a time resolution of 1 s.
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7.28.1 Features
Measures the passage of time to maintain a calendar and clock. Ultra low power design to support battery powered systems. Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and
Day of Year.
Dedicated power supply pin can be connected to a battery or to the main 3.3 V. Periodic interrupts can be generated from increments of any field of the time registers. Backup registers (20 bytes) powered by VBAT. RTC power supply is isolated from the rest of the chip.
7.29 Clocking and power control

7.29.1 Crystal oscillators
The LPC17xx include three independent oscillators. These are the main oscillator, the IRC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the main PLL and ultimately the CPU. Following reset, the LPC17xx will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency.
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See Figure 5 for an overview of the LPC17xx clock generation.
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LPC17xx
MAIN OSCILLATOR
USB PLL USB CLOCK DIVIDER pllclk system clock select (CLKSRCSEL)
usbclk (48 MHz) USB BLOCK
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MAIN PLL
USB clock config USB PLL enable (USBCLKCFG) CPU CLOCK DIVIDER CPU clock config (CCLKCFG)
cclk
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main PLL enable
ARM CORTEX-M3
ETHERNET BLOCK DMA GPIO NVIC
INTERNAL RC OSCILLATOR
WATCHDOG TIMER
CCLK/8 32 kHz RTC OSCILLATOR pclkWDT rtclk = 1Hz PERIPHERAL CLOCK GENERATOR REAL-TIME CLOCK CCLK/6 CCLK/4 CCLK/2 CCLK APB peripherals
002aad947
Fig 5.
LPC17xx clocking generation block diagram
7.29.1.1
Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy over the entire voltage and temperature range. Upon power-up or any chip reset, the LPC17xx use the IRC as the clock source. Software may later switch to one of the other available clock sources.
7.29.1.2
Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator also provides the clock source for the dedicated USB PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the main PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.29.2 for additional information.
7.29.1.3
RTC oscillator The RTC oscillator can be used as the clock source for the RTC block, the main PLL, and/or the CPU.
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7.29.2 Main PLL (PLL0)
The PLL0 accepts an input clock frequency in the range of 32 kHz to 25 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and/or the USB block.
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The PLL0 input, in the range of 32 kHz to 25 MHz, may initially be divided down by a value N, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency.
Following the PLL0 input divider is the PLL0 multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value M, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL0 is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL0 is enabled by software only. The program must configure and activate the PLL0, wait for the PLL0 to lock, and then connect to the PLL0 as a clock source.
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7.29.3 USB PLL (PLL1)

The LPC17xx contain a second, dedicated USB PLL1 to provide clocking for the USB interface. The PLL1 receives its clock input from the main oscillator only and provides a fixed 48 MHz clock to the USB block only. The PLL1 is disabled and powered off on reset. If the PLL1 is left disabled, the USB clock will be supplied by the 48 MHz clock from the main PLL0. The PLL1 accepts an input clock frequency in the range of 10 MHz to 25 MHz only. The input frequency is multiplied up the range of 48 MHz for the USB clock using a Current Controlled Oscillators (CCO). It is insured that the PLL1 output has a 50 % duty cycle.
7.29.4 RTC clock output

The LPC17xx feature a clock output function intended for synchronizing with external devices and for use during system development to allow checking the internal clocks CCLK, IRC clock, main crystal, RTC clock, and USB clock in the outside world. The RTC clock output allows tuning the RTC frequency without probing the pin, which would distort the results.
7.29.5 Wake-up timer

The LPC17xx begin operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and
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whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up timer.
The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions.
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7.29.6 Power control

The LPC17xx support a variety of power control features. There are four special modes of processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. Integrated PMU (Power Management Unit) automatically adjust internal regulators to minimize power consumption during Sleep, Deep sleep, Power-down, and Deep power-down modes. The LPC17xx also implement a separate power domain to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small set of registers for storing data during any of the power-down modes. 7.29.6.1 Sleep mode When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep mode does not need any special sequence but re-enabling the clock to the ARM core. In Sleep mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.29.6.2 Deep-sleep mode In Deep-sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Deep-sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero.
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The Deep-sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Deep-sleep mode reduces chip power consumption to a very low value. Power to the flash memory is left on in Deep-sleep mode, allowing a very quick wake-up.
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On wake-up from Deep-sleep mode, the code execution and peripherals activities will resume after 4 cycles expire if the IRC was used before entering Deep-sleep mode. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. PLL and clock dividers need to be reconfigured accordingly. 7.29.6.3 Power-down mode Power-down mode does everything that Deep-sleep mode does, but also turns off the power to the IRC oscillator and the flash memory. This saves more power but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 s flash start-up time. When it times out, access to the flash will be allowed. Users need to reconfigure the PLL and clock dividers accordingly. 7.29.6.4 Deep power-down mode The Deep power-down mode can only be entered from the RTC block. In Deep power-down mode, power is shut off to the entire chip with the exception of the RTC module and the RESET pin. The LPC17xx can wake up from Deep power-down mode via the RESET pin or an alarm match event of the RTC. 7.29.6.5 Wake-up interrupt controller The Wake-up Interrupt Controller (WIC) allows the CPU to automatically wake up from any enabled priority interrupt that can occur while the clocks are stopped in Deep sleep, Power-down, and Deep power-down modes. The WIC works in connection with the Nested Vectored Interrupt Controller (NVIC). When the CPU enters Deep sleep, Power-down, or Deep power-down mode, the NVIC sends a mask of the current interrupt situation to the WIC.This mask includes all of the interrupts that are both enabled and of sufficient priority to be serviced immediately. With this information, the WIC simply notices when one of the interrupts has occurred and then it wakes up the CPU. The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings.
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7.29.7 Peripheral power control

A Power Control for Peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings.
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7.29.8 Power domains
The LPC17xx provide two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the backup Registers.
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On the LPC17xx, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(REG)(3V3) pin powers the on-chip voltage regulator which in turn provides power to the CPU and most of the peripherals. Depending on the LPC17xx application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(REG)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring on the fly while keeping the CPU and peripherals alive.
The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(REG)(3V3)). Having the on-chip voltage regulator powered independently from the I/O pad ring enables shutting down of the I/O pad power supply on the fly, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC domain. The RTC requires a minimum of power to operate, which can be supplied by an external battery. The device core power (VDD(REG)(3V3)) is used to operate the RTC whenever VDD(REG)(3V3) is present. Therefore, there is no power drain from the RTC battery when VDD(REG)(3V3) is available.
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LPC17xx
VDD(3V3) VSS VDD(REG)(3V3) REGULATOR to I/O pads to core to memories, peripherals, oscillators, PLLs
D R A FT D
MAIN POWER DOMAIN
VBAT
POWER SELECTOR
ULTRA LOW-POWER REGULATOR BACKUP REGISTERS
RTCX1 RTCX2
32 kHz OSCILLATOR RTC POWER DOMAIN
REAL-TIME CLOCK
DAC VDDA VREFP VREFN VSSA ADC POWER DOMAIN ADC
002aad978
Fig 6.
Power distribution
7.30 System control

7.30.1 Reset
Reset has four sources on the LPC17xx: the RESET pin, the Watchdog reset, power-on reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, causes the RSTOUT pin to go LOW and starts the wake-up timer (see description in Section 7.29.5). The wake-up timer ensures that reset remains asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. Once reset is de-asserted, or, in case of a BOD-triggered reset, once the voltage rises above the BOD threshold, the RSTOUT pin goes HIGH. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values.
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7.30.2 Brownout detection
The LPC17xx include 2-stage monitoring of the voltage on the VDD(REG)(3V3) pins. If this voltage falls below 2.2 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC17xx when the voltage on the VDD(REG)(3V3) pins falls below 1.85 V. This reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall reset. Both the 2.2 V and 1.85 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.2 V detection to reliably interrupt, or a regularly executed event loop to sense the condition.
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7.30.3 Code security (Code Read Protection - CRP)

This feature of the LPC17xx allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the users application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0.
CAUTION If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device.
7.30.4 APB interface

The APB peripherals are split into two separate APB buses in order to distribute the bus bandwidth and thereby reducing stalls caused by contention between the CPU and the GPDMA controller.
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7.30.5 AHB multilayer matrix
The LPC17xx use an AHB multilayer matrix. This matrix connects the instruction (I-code) and data (D-code) CPU buses of the ARM Cortex-M3 to the flash memory, the main (32 kB) static RAM, and the Boot ROM. The GPDMA can also access all of these memories. The peripheral DMA controllers, Ethernet, and USB can access all SRAM blocks. Additionally, the matrix connects the CPU system bus and all of the DMA controllers to the various peripheral functions.
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7.30.6 External interrupt inputs

The LPC17xx include up to 46 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode.
7.30.7 Memory mapping control

The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register contained in the NVIC. The vector table may be located anywhere within the bottom 1 GB of Cortex-M3 address space. The vector table must be located on a 128 word (512 byte) boundary because the NVIC on the LPC17xx is configured for 128 total interrupts.
7.31 Emulation and debugging

Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points.
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8. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol VDD(3V3) VDD(REG)(3V3) VDDA Vi(VBAT) Vi(VREFP) VIA VI Parameter supply voltage (3.3 V) regulator supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT input voltage on pin VREFP analog input voltage input voltage on ADC related pins 5 V tolerant I/O pins; only valid when the VDD(3V3) supply voltage is present other I/O pins IDD ISS Ilatch supply current ground current I/O latch-up current per supply pin per ground pin (0.5VDD(3V3)) < VI < (1.5VDD(3V3)); Tj < 125 C Tstg Ptot(pack) storage temperature total power dissipation (per package) based on package heat transfer, not device power consumption human body model; all pins
[6] [5] [2]
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Conditions external rail
Min 2.4 2.4 0.5
Max 3.6 3.6 +4.6 +4.6 +4.6 +5.1 +5.5
Unit V V V V V V V
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for the RTC
0.5 0.5 0.5 0.5
[2][3]
0.5 -
VDD(3V3) + 0.5 100 100 100
V mA mA mA
[4] [4]
65 -
+150 1.5
C W
VESD
[1]
electrostatic discharge voltage
4000
+4000
The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
[2] [3] [4] [5] [6]
Including voltage on outputs in 3-state mode. Not to exceed 4.6 V. The peak current is limited to 25 times the corresponding maximum current. Dependent on package type. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
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9. Thermal characteristics
The average chip junction temperature, Tj (C), can be calculated using the following equation:
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T j = T amb + ( P D R th ( j a ) )
(1)
A FT D R
Tamb = ambient temperature (C), Rth(j-a) = the package junction-to-ambient thermal resistance (C/W) PD = sum of internal and I/O power dissipation
The internal power dissipation is the product of IDD and VDD. The I/O power dissipation of the I/O pins is often small and many times can be negligible. However it can be significant in some applications.
Table 6. Thermal characteristics VDD = 2.4 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; Symbol Tj(max) Parameter maximum junction temperature Conditions Min Typ Max 125 Unit C
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FT
10. Static characteristics

Table 7. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Supply pins VDD(3V3) VDD(REG)(3V3) VDDA Vi(VBAT) Vi(VREFP) IDD(REG)(3V3) supply voltage (3.3 V) regulator supply voltage (3.3 V) analog 3.3 V pad supply voltage input voltage on pin VBAT input voltage on pin VREFP regulator supply current active mode; code (3.3 V) while(1){} executed from flash; all peripherals disabled; PCLK = CCLK 8 CCLK = 12 MHz; PLL disabled CCLK = 100 MHz; PLL enabled CCLK = 100 MHz; PLL enabled (LPC1769) CCLK = 120 MHz; PLL enabled (LPC1769) sleep mode deep sleep mode power-down mode deep power-down mode; RTC running IBAT battery supply current deep power-down mode; RTC running VDD(REG)(3V3) present VDD(REG)(3V3) not present IDD(IO) I/O supply current deep sleep mode power-down mode deep power-down mode
[10] [11] [4][5] [3]
R A FT D R
R A F D R A FT
A FT A FT D
Parameter
Conditions external rail

[2]
Min 2.4 2.4 2.7 2.1 2.7
Typ[1] 3.3 3.3 3.3 3.3 3.3
Max 3.6 3.6 3.6 3.6 VDDA
Unit V V V V V
R A FT D R A
7 42 50 67 2 240 31 630
mA mA mA mA mA A A nA
[4][5]
[4][6]
[4][6]
[4][7] [4][8] [4][8] [9]
530 1.1 40 40 10
nA A nA nA nA
[12] [12] [12]
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
Table 7. Static characteristics continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol IDD(ADC) Parameter ADC supply current Conditions active mode; ADC powered ADC in Power-down mode deep sleep mode power-down mode deep power-down mode II(ADC) ADC input current on pin VREFP deep sleep mode power-down mode deep power-down mode Standard port pins, RESET, RTCK IIL IIH LOW-level input current VI = 0 V; on-chip pull-up resistor disabled HIGH-level input current OFF-state output current input voltage output voltage HIGH-level input voltage LOW-level input voltage hysteresis voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current IOH = 4 mA IOL = 4 mA VOH = VDD(3V3) 0.4 V VOL = 0.4 V
[20] [16] [16] [16] [13][15] [13][14]
R A FT
R A F
A FT
Min -
Typ[1] 1.95 <0.2 38 38 24 100 100 100
Max -
Unit mA A nA nA nA nA nA nA
D R
R A FT D A FT D R A
FT D R
[13] [13] [13]
0.5 0.5
10 10
nA nA
VI = VDD(3V3); on-chip pull-down resistor disabled VO = 0 V; VO = VDD(3V3); on-chip pull-up/down resistors disabled pin configured to provide a digital function output active
[17][18] [19]
IOZ
0.5
10
nA
VI VO VIH VIL Vhys VOH VOL IOH IOL IOHS IOLS Ipd Ipu
0 0
5.0 VDD(3V3) -
V V V
0.7VDD(3V3) 0.4 VDD(3V3) 0.4 4 4 10 15 0 50 50 0
0.3VDD(3V3) V 0.4 45 50 150 85 0 V V V mA mA mA mA A A A
HIGH-level short-circuit VOH = 0 V output current LOW-level short-circuit output current pull-down current pull-up current VOL = VDD(3V3) VI = 5 V VI = 0 V VDD(3V3) < VI < 5 V
[20]
LPC1769_68_67_66_65_64_63
Product data sheet
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
Table 7. Static characteristics continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol I2C-bus VIH VIL Vhys VOL ILI Oscillator pins Vi(XTAL1) Vo(XTAL2) Vi(RTCX1) Vo(RTCX2) input voltage on pin XTAL1 output voltage on pin XTAL2 input voltage on pin RTCX1 output voltage on pin RTCX2 OFF-state output current bus supply voltage differential input sensitivity voltage differential common mode voltage range single-ended receiver switching threshold voltage LOW-level output voltage for low-/full-speed HIGH-level output voltage (driven) for low-/full-speed RL of 1.5 k to 3.6 V |(D+) (D)| includes VDI range 0 V < VI < 3.3 V
[2]
R A FT
R A F
A FT
Parameter pins (P0[27] and P0[28]) HIGH-level input voltage LOW-level input voltage hysteresis voltage LOW-level output voltage input leakage current
Conditions
Min
Typ[1]
Max -
Unit
D R
R A FT D
A FT D
0.7VDD(3V3) IOLS = 3 mA VI = VDD(3V3) VI = 5 V

[21]
R A FT D
0.05 VDD(3V3) 2 10 1.8 1.8 -
0.3VDD(3V3) V 0.4 4 22 1.95 1.95 3.6 3.6 V V A A V V V V
R A
0.5 0.5 0.5 0.5
USB pins (LPC1769/68/66/65/64 only) IOZ VBUS VDI VCM Vth(rs)se 0.2 0.8 0.8 10 5.25 2.5 2.0 A V V V V
[2] [2]
[2]
[2]
VOL
[2]
0.18
VOH
RL of 15 k to GND
[2]
2.8
3.5
Ctrans ZDRV
transceiver capacitance pin to GND driver output with 33 series resistor; impedance for driver steady state drive which is not high-speed capable
[2] [22][2]
36
20 44.1
pF
[1] [2] [3] [4]
Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. For USB operation 3.0 V VDD((3V3) 3.6 V. Guaranteed by design. The RTC typically fails when Vi(VBAT) drops below 1.6 V. VDD(REG)(3V3) = 3.3 V; Tamb = 25 C for all power consumption measurements.
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Product data sheet
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46 of 79
NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
[5] [6] [7] [8] [9]
Applies to LPC1768/67/66/65/64/63. Applies to LPC1769 only. IRC running at 4 MHz; main oscillator and PLL disabled; PCLK = CCLK 8. BOD disabled. On pin VDD(REG)(3V3). IBAT = 530 nA. VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C.
R A FT D R
R A F D R A FT
A FT A FT D R A
[10] On pin VBAT; IDD(REG)(3V3) = 630 nA; VDD(REG)(3V3) = 3.0 V; VBAT = 3.0 V; Tamb = 25 C. [11] On pin VBAT; VBAT = 3.0 V; Tamb = 25 C. [12] All internal pull-ups disabled. All pins configured as output and driven LOW. VDD(3V3) = 3.3 V; Tamb = 25 C.
FT D R A
[13] On pin VDDA; VDDA = 3.3 V; Tamb = 25 C. The ADC is powered if the PDN bit in the AD0CR register is set to 1 and in Power-down mode of the PDN bit is set to 0. [14] The ADC is powered if the PDN bit in the AD0CR register is set to 1. See LPC17xx user manual UM10360_1. [15] The ADC is in Power-down mode if the PDN bit in the AD0CR register is set to 0. See LPC17xx user manual UM10360_1. [16] Vi(VREFP) = 3.3 V; Tamb = 25 C. [17] Including voltage on outputs in 3-state mode. [18] VDD(3V3) supply voltages must be present. [19] 3-state outputs go into 3-state mode in Deep power-down mode. [20] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [21] To VSS. [22] Includes external resistors of 33 1 % on D+ and D.
10.1 Power consumption

400 IDD(Reg)(3V3) (A) 350 3.6 V 3.3 V 2.4 V 300
002aaf568
250
200 40
15
10
35
60 85 temperature (C)
Conditions: VDD(Reg)(3V3) = 3.3 V; BOD disabled.
Fig 7.
Deep-sleep mode: typical regulator supply current IDD(Reg)(3V3) versus temperature
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LPC1769/68/67/66/65/64/63

A
D R A
D R A
120 IDD(Reg)(3V3) (A)
002aaf569
D R A R A FT
A FT A FT D R D R A F R A FT D FT
FT
80
3.6 V 3.3 V 2.4 V
D R A
40
0 40
15
10
35
Conditions: VDD(Reg)(3V3) = 3.3 V; BOD disabled.
Fig 8.
Power-down mode: Typical regulator supply current IDD(Reg)(3V3) versus temperature
1.8 IBAT) (A) Vi(VBAT) = 3.6 V 3.3 V 3.0 V 2.4 V
002aag119
1.4
1.0
0.6 -40
-15
10
35
Conditions: VDD(REG)(3V3) floating; RTC running.
Fig 9.
Deep power-down mode: Typical battery supply current IBAT versus temperature
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Product data sheet
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
2.0 IDD(REG)(3V3)/IBAT (A) 1.6
002aag120
IDD(REG)(3V3)
D R A R A FT
A FT A FT D R D R A F R A FT D FT D R
FT
1.2
0.8
IBAT
0.4
0 -40
-15
10
35
Conditions: VBAT = 3.0 V; VDD(REG)(3V3) = 3.0 V; RTC running.
Fig 10. Deep power-down mode: Typical regulator supply current IDD(REG)(3V3) and battery supply current IBAT versus temperature
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Product data sheet
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
10.2 Peripheral power consumption
The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample at Tamb = 25 C. The peripheral clock PCLK = CCLK/4.
FT D R A FT D
Table 8. Peripheral Power consumption for individual analog and digital blocks Conditions Typical supply current in mA; CCLK = 12 MHz Timer UART PWM Motor control PWM I2C SPI SSP1 ADC PCLK = 12 MHz for CCLK = 12 MHz and 48 MHz; PCLK = 12.5 MHz for CCLK = 100 MHz PCLK = CCLK/6 PCLK = CCLK/6 PCLK = CCLK 0.03 0.07 0.05 0.05 0.02 0.02 0.04 2.12 48 MHz 0.11 0.26 0.20 0.21 0.08 0.06 0.16 2.09 100 MHz 0.23 0.53 0.41 0.42 0.16 0.13 0.32 2.07 Average current per I2C Average current per timer Average current per UART Notes
R A
A FT
CAN CAN0, CAN1, acceptance filter DMA QEI GPIO I2S USB and PLL1 Ethernet Ethernet connected
[1]
0.13 0.22 1.33 0.05 0.33 0.09 0.94
0.49 0.85 5.10 0.20 1.27 0.34 1.32 1.87 -
1.00 1.73 10.36 0.41 2.58 0.70 1.94 3.79 5.19
Average current per CAN Both CAN blocks and acceptance filter[1]
Ethernet block enabled in the PCONP register; Ethernet not connected. Ethernet initialized, connected to network, and running web server example.
0.49 -
The combined current of several peripherals running at the same time can be less than the sum of each individual peripheral current measured separately.
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
10.3 Electrical pin characteristics

3.6 VOH (V) 3.2
002aaf112
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT
T = 85 C 25 C 40 C
D R A
2.8
2.4
2.0 0 8 16 IOH (mA) 24
Conditions: VDD(REG)(3V3) = VDD(3V3) = 3.3 V; standard port pins.
Fig 11. Typical HIGH-level output voltage VOH versus HIGH-level output source current IOH
15 IOL (mA) 10 T = 85 C 25 C 40 C
002aaf111
0 0 0.2 0.4 VOL (V) 0.6
Fig 12. Typical LOW-level output current IOL versus LOW-level output voltage VOL
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LPC1769/68/67/66/65/64/63

A
D R A
D R A
10 Ipu (A) 10
002aaf108
D R A R A FT
FT
30 T = 85 C 25 C 40 C
50
70
4 VI (V)
Fig 13. Typical pull-up current Ipu versus input voltage VI
90 Ipd (A) 70
002aaf109
50
T = 85 C 25 C 40 C
30
10
10
4 VI (V)
Fig 14. Typical pull-down current Ipd versus input voltage VI
LPC1769_68_67_66_65_64_63
Product data sheet
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
11. Dynamic characteristics

11.1 Flash memory
Table 9. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Nendu tret ter tprog
[1] [2]
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R
Parameter endurance retention time erase time programming time
Conditions
[1]
Min 10000 10 20 95
[2]
Typ 100000 100 1
Max 105 1.05
Unit cycles years years ms ms
powered unpowered sector or multiple consecutive sectors
0.95
Number of program/erase cycles. Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in blocks of 256 bytes.
11.2 External clock

Table 10. Dynamic characteristic: external clock Tamb = 40 C to +85 C; VDD(3V3) over specified ranges.[1] Symbol fosc Tcy(clk) tCHCX tCLCX tCLCH tCHCL
[1] [2]
Parameter oscillator frequency clock cycle time clock HIGH time clock LOW time clock rise time clock fall time
Conditions
Min 1 40 Tcy(clk) 0.4 Tcy(clk) 0.4 -
Typ[2] -
Max 25 1000 5 5
Unit MHz ns ns ns ns ns
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
tCHCL
tCLCX Tcy(clk)
tCHCX tCLCH
002aaa907
Fig 15. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV)
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A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
11.3 Internal oscillators

Table 11. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V VDD(3V3) 3.6 V.[1] Symbol fosc(RC) fi(RTC)
[1] [2]
R A FT D R
R A F D R A FT
A FT A FT
Parameter internal RC oscillator frequency RTC input frequency
Conditions -
Min 3.96 -
Typ[2] 4.02 32.768
Max 4.04 -
Unit kHz
MHz
D R A FT D
R A
Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages.
4.036 fosc(RC) (MHz) 4.032
002aaf107
4.028
4.024
VDD(3V) = 3.6 V 3.3 V 3.0 V 2.7 V 2.4 V
4.020
4.016 40
15
10
35
Conditions: Frequency values are typical values. 4 MHz 1 % accuracy is guaranteed for 2.7 V VDD(3V3) 3.6 V and Tamb = 40 C to +85 C. Variations between parts may cause the IRC to fall outside the 4 MHz 1 % accuracy specification for voltages below 2.7 V.
Fig 16. Internal RC oscillator frequency versus temperature
11.4 I/O pins

Table 12. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; VDD(3V3) over specified ranges. Symbol tr tf
[1]
Parameter rise time fall time
Conditions pin configured as output pin configured as output
Min 3.0 2.5
Typ -
Max 5.0 5.0
Unit ns ns
Applies to standard I/O pins and RESET pin.
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
11.5 I2C-bus
Table 13. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.[2] Symbol fSCL Parameter SCL clock frequency fall time
[4][5][6][7]
R A FT D R
R A F D R A FT
A FT A FT
Conditions Standard-mode Fast-mode Fast-mode Plus of both SDA and SCL signals Standard-mode Fast-mode Fast-mode Plus
Min 0 0 0 -
Max 100 400 1 300
Unit kHz kHz
MHz ns
D R A FT D
R A
tf
20 + 0.1 Cb 4.7 1.3 0.5 4.0 0.6 0.26 0 0 0 250 100 50
300 120 -
ns ns s s s s s s s s s ns ns ns
tLOW
LOW period of the SCL clock HIGH period of the SCL clock data hold time
[3][4][8]
Standard-mode Fast-mode Fast-mode Plus Standard-mode Fast-mode Fast-mode Plus Standard-mode Fast-mode Fast-mode Plus
tHIGH
tHD;DAT
tSU;DAT
data set-up time
[9][10]
Standard-mode Fast-mode Fast-mode Plus
[1] [2] [3] [4] [5] [6]
See the I2C-bus specification UM10204 for details. Parameters are valid over operating temperature range unless otherwise specified. tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. Cb = total capacitance of one bus line in pF. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for this when considering bus timing. The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than the maximum of tVD;DAT or tVD;ACK by a transition time (see the I2C-bus specification UM10204). This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock. tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the acknowledge.
[7] [8]
[9]
[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I2C-bus specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
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NXP Semiconductors
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A
D R A
D R A
D R A R A FT
R A D R R A FT
FT
tf SDA 70 % 30 % tf 70 % 30 % 70 % 30 % tHD;DAT
tSU;DAT
D R A FT D
R A FT D A R
tVD;DAT tHIGH
FT D R A
SCL
70 % 30 %
70 % 30 % tLOW
70 % 30 %
1 / fSCL
002aaf425
Fig 17. I2C-bus pins clock timing
11.6 I2S-bus interface

Remark: The I2S-bus interface is available on parts LPC1769/68/67/66/65/63. See Table 2.
Table 14. Dynamic characteristics: I2S-bus interface pins Tamb = 40 C to +85 C. Symbol tr tf tWH tWL Parameter rise time fall time pulse width HIGH pulse width LOW on pins I2STX_CLK and I2SRX_CLK on pins I2STX_CLK and I2SRX_CLK Conditions
[1] [1] [1]
Min 0.495 Tcy(clk) -
Typ -
Max 35 35 0.505 Tcy(clk)
Unit ns ns ns
common to input and output
[1]
output tv(Q) input tsu(D) th(D)

[1]
data output valid time
on pin I2STX_SDA on pin I2STX_WS
[1] [1]
3.5 4.0
30 30 -
ns ns ns ns
data input set-up time data input hold time
on pin I2SRX_SDA on pin I2SRX_SDA
[1] [1]
CCLK = 20 MHz; peripheral clock to the I2S-bus interface PCLK = CCLK 4; I2S clock cycle time Tcy(clk) = 1600 ns, corresponds to the SCK signal in the I2S-bus specification.
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A R A FT
R A D R R A FT
FT
Tcy(clk)
tf
tr
D R A FT
R A FT
I2STX_CLK
D R A
tWH I2STX_SDA
tWL
FT D R A
tv(Q) I2STX_WS tv(Q)

002aad992
Fig 18. I2S-bus timing (output)
Tcy(clk)
tf
tr
I2SRX_CLK
tWH I2SRX_SDA
tWL
tsu(D)
th(D)
I2SRX_WS tsu(D) tsu(D)

002aae159
Fig 19. I2S-bus timing (input)
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NXP Semiconductors
LPC1769/68/67/66/65/64/63

A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
11.7 SSP interface

Table 15. Dynamic characteristic: SSP interface Tamb = 25 C; VDD(3V3) over specified ranges. Symbol tsu(SPI_MISO)
[1]
R A FT D R
R A F D R A FT
A FT A FT
Parameter SPI_MISO set-up time
Conditions measured in SPI Master mode; see Figure 20

[1]
Min 30
Typ
Max -
Unit ns
D R A
SSP interface
FT D R A
The peripheral clock for SSP is PCLK = CCLK = 20 MHz.
shifting edges
SCK
sampling edges
MOSI
MISO
tsu(SPI_MISO)
002aad326
Fig 20. MISO line set-up time in SSP Master mode
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NXP Semiconductors
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A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
11.8 USB interface
Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764.
FT
Table 16. Dynamic characteristics: USB pins (full-speed) CL = 50 pF; Rpu = 1.5 k on D+ to VDD(3V3); 3.0 V VDD(3V3) 3.6 V. Symbol tr tf tFRFM VCRS tFEOPT tFDEOP tJR1 tJR2 tEOPR1 Parameter rise time fall time differential rise and fall time matching output signal crossover voltage source SE0 interval of EOP source jitter for differential transition to SE0 transition receiver jitter to next transition receiver jitter for paired transitions EOP width at receiver 10 % to 90 % must reject as EOP; see Figure 21 must accept as EOP; see Figure 21
[1]
R A D R
R A F D R A FT
A FT A FT D R A
D FT D
Conditions 10 % to 90 % 10 % to 90 % tr / tf
Min 8.5 7.7 1.3
Typ -
Max 13.8 13.7 109 2.0 175 +5 +18.5 +9 -
Unit ns ns % V ns ns ns ns ns
R A
see Figure 21 see Figure 21
160 2 18.5 9 40
tEOPR2
EOP width at receiver
[1]
82
ns
[1]
Characterized but not implemented as production test. Guaranteed by design.
TPERIOD crossover point differential data lines
crossover point extended
source EOP width: tFEOPT differential data to SE0/EOP skew n TPERIOD + tFDEOP
receiver EOP width: tEOPR1, tEOPR2

002aab561
Fig 21. Differential data-to-EOP transition skew and EOP width
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NXP Semiconductors
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A
D R A
D R A
D R A
R A D R
A FT A FT D R
FT
11.9 SPI
Table 17. Dynamic characteristics of SPI pins Tamb = 40 C to +85 C. Symbol Tcy(PCLK) TSPICYC tSPICLKH tSPICLKL SPI master tSPIDSU tSPIDH tSPIQV tSPIOH SPI slave tSPIDSU tSPIDH tSPIQV tSPIOH
[1] [2]
R A FT D R
R A F D R A FT
A FT A FT
Parameter PCLK cycle time SPI cycle time SPICLK HIGH time SPICLK LOW time SPI data set-up time SPI data hold time SPI data output valid time SPI output data hold time SPI data set-up time SPI data hold time SPI data output valid time SPI output data hold time
[2] [2] [2] [2] [1]
Min 10 79.6 0.485 TSPICYC
Typ -
Max 0.515 TSPICYC -
Unit ns ns ns ns ns ns ns ns ns ns ns ns
D R A FT D
R A
0 2 Tcy(PCLK) 5 2 Tcy(PCLK) + 30 2 Tcy(PCLK) + 5 0 2 Tcy(PCLK) + 5 2 Tcy(PCLK) + 35 2 Tcy(PCLK) + 15
[2] [2] [2] [2]
TSPICYC = (Tcy(PCLK) n) 0.5 %, n is the SPI clock divider value (n 8); PCLK is derived from the processor clock CCLK. Timing parameters are measured with respect to the 50 % edge of the clock SCK and the 10 % (90 %) edge of the data signal (MOSI or MISO).
TSPICYC
tSPICLKH
tSPICLKL
SCK (CPOL = 0)
SCK (CPOL = 1) tSPIQV MOSI DATA VALID DATA VALID tSPIDSU MISO DATA VALID tSPIDH tSPIOH
DATA VALID
002aad986
Fig 22.
SPI master timing (CPHA = 1)
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A
D R A
D R A
D R A R A FT
R A D R R A FT
FT
TSPICYC
tSPICLKH
tSPICLKL
D R A FT
R A FT
SCK (CPOL = 0)
D R A FT
SCK (CPOL = 1) tSPIQV MOSI DATA VALID DATA VALID tSPIDSU DATA VALID tSPIDH tSPIOH
D R A
MISO
DATA VALID
002aad987
Fig 23.
SPI master timing (CPHA = 0)
TSPICYC
tSPICLKH
tSPICLKL
SCK (CPOL = 0)
SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPIQV MISO DATA VALID DATA VALID tSPIDH
DATA VALID tSPIOH
002aad988
Fig 24.
SPI slave timing (CPHA = 1)
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A
D R A
D R A
D R A R A FT
R A D R R A FT
FT
TSPICYC
tSPICLKH
tSPICLKL
D R A FT
R A FT
SCK (CPOL = 0)
D R A FT
SCK (CPOL = 1) tSPIDSU MOSI DATA VALID tSPIQV MISO DATA VALID DATA VALID tSPIDH
D R A
DATA VALID tSPIOH
002aad989
Fig 25.
SPI slave timing (CPHA = 0)
12. ADC electrical characteristics

Table 18. ADC characteristics (full resolution) VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 13 MHz; 12-bit resolution. Symbol VIA Cia ED EL(adj) EO EG ET Rvsi fclk(ADC) fc(ADC)
[1] [2] [3] [4] [5] [6] [7] [8] [9]
Parameter analog input voltage analog input capacitance differential linearity error integral non-linearity offset error gain error absolute error voltage source interface resistance ADC clock frequency ADC conversion frequency
Conditions
Min 0 [1][2] [3] [4][5] [6] [7] [8]
Typ -
Max VDDA 15 1 3 2 0.5 4 7.5 13 200
Unit V pF LSB LSB LSB % LSB k MHz kHz
[9]
The ADC is monotonic, there are no missing codes. The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 26. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 26. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 26. ADCOFFS value (bits 7:4) = 2 in the ADTRM register. See LPC17xx user manual UM10360. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 26. The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 26. See Figure 27. The conversion frequency corresponds to the number of samples per second.
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A
Table 19. ADC characteristics (lower resolution) Tamb = 40 C to +85 C unless otherwise specified; 12-bit ADC used as 10-bit resolution ADC. Symbol Parameter ED EL(adj) EO EG fclk(ADC) fc(ADC) differential linearity error integral non-linearity offset error gain error ADC clock frequency ADC conversion frequency 3.0 V VDDA 3.6 V 2.7 V VDDA < 3.0 V 3 V VDDA 3.6 V 2.7 V VDDA < 3.0 V
[1] [2] [3] [4] [5] [6] The ADC is monotonic, there are no missing codes.
[6] [6]
D R A
D R A
D R A R A FT
R A D R R A FT D D
FT
Conditions
[1][2] [3] [4] [5]
Min -
Typ 1 1.5 2 2 -
Max 33 25 500 400
Unit LSB LSB LSB MHz MHz kHz kHz LSB
A FT D R A
FT D FT D R A
The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 26. The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 26. The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 26. The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 26. The conversion frequency corresponds to the number of samples per second.
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A
D R A
D R A
offset error EO 4095
D R A R A
gain error EG
R A D R R A FT D D R A FT D R A FT
A FT A FT D R D R A F R A FT D FT D
FT
4094
R A
4093
4092
4091
4090
(2)
7 code out 6
(1)
5
(5)
4
(4)
3
(3)
1 LSB (ideal) 4090 4091 4092 4093 4094 4095 4096
0 1 offset error EO 2 3 4 5 6 7 VIA (LSBideal)
1 LSB =
VREFP VREFN 4096

002aad948
(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.
Fig 26. 12-bit ADC characteristics
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D R A
D R A
D R A R A FT
R A D R R A FT
FT
LPC17xx
C3 ADC COMPARATOR BLOCK 2.2 pF Ri1 2 k - 5.2 k Ri2 100 - 600
D R A FT
R A FT
AD0[n]
D R A FT
C1 750 fF
C2 65 fF
Cia
Rvsi
R A
VSS
VEXT
002aaf197
The values of resistor components Ri1 and Ri2 vary with temperature and input voltage and are process-dependent (see Table 20). Parasitic resistance and capacitance from the pad are not included in this figure.
Fig 27. ADC interface to pins AD0[n] Table 20. Ri1 Ri2 C1 C2 C3 ADC interface components Range 2 k to 5.2 k 100 to 600 750 fF 65 fF 2.2 pF Description Switch-on resistance for channel selection switch. Varies with temperature, input voltage, and process. Switch-on resistance for the comparator input switch. Varies with temperature, input voltage, and process. Parasitic capacitance from the ADC block level. Parasitic capacitance from the ADC block level. Sampling capacitor.
Component
13. DAC electrical characteristics

Remark: The DAC is available on parts LPC1769/68/67/66/65/63. See Table 2.
Table 21. DAC electrical characteristics VDDA = 2.7 V to 3.6 V; Tamb = 40 C to +85 C unless otherwise specified Symbol ED EL(adj) EO EG CL RL Parameter differential linearity error integral non-linearity offset error gain error load capacitance load resistance Conditions Min 1 Typ 1 1.5 0.6 0.6 200 Max Unit LSB LSB % % pF k
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D R A
D R A
D R A
R A D R
A FT A FT D R
FT
14. Application information

14.1 Suggested USB interface solutions
Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1769/68/66/65 and as device-only controller on part LPC1764.
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
VDD(3V3)
USB_UP_LED USB_CONNECT
LPC17xx
SoftConnect switch
R1 1.5 k
VBUS USB_D+ RS = 33 USB_D RS = 33 VSS

002aad939
USB-B connector
Fig 28. USB interface on a self-powered device
VDD(3V3)
R2
LPC17xx
USB_UP_LED VBUS USB_D+ RS = 33 USB_D RS = 33 VSS
R1 1.5 k
USB-B connector
002aad940
Fig 29. USB interface on a bus-powered device
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D R A
D R A
D R A R A FT
R A D R R A FT
FT
VDD
D R A FT D
R A FT D R
RSTOUT
RESET_N ADR/PSW VDD OE_N/INT_N SPEED SUSPEND
VBUS ID DP DM
33 33
A FT D R A
Mini-AB connector
ISP1302
VSS
LPC17xx
USB_SCL USB_SDA EINTn USB_D+ USB_D USB_UP_LED
SCL SDA INT_N
002aad941
VDD
Fig 30. USB OTG port configuration
VDD USB_UP_LED VSS USB_D+ USB_D

33 33 15 k 15 k
D+ D USB-A connector VDD
LPC17xx
USB_PWRD USB_OVRCR USB_PPWR 5V
VBUS
ENA IN
FLAGA
LM3526-L
OUTA
002aad942
Fig 31. USB host port configuration
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D R A
D R A
D R A R A FT
R A D R R A FT
FT
VDD USB_UP_LED
D R A FT D
R A FT D
VDD USB_CONNECT
R A FT D
LPC17xx
VSS USB_D+ USB_D VBUS
33 33
R A
D+ D VBUS USB-B connector
002aad943
Fig 32. USB device port configuration
14.2 Crystal oscillator XTAL input and component selection

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mV(RMS) is needed.
LPC1xxx
XTAL1
Ci 100 pF Cg
002aae835
Fig 33. Slave mode operation of the on-chip oscillator
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 33), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this configuration can be left unconnected. External components and models used in oscillation mode are shown in Figure 34 and in Table 22 and Table 23. Since the feedback resistance is integrated on chip, only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation (the fundamental frequency is represented by L, CL and RS). Capacitance CP in Figure 34 represents the parallel package capacitance and should not be larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal manufacturer.
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A
D R A
D R A
D R A R A FT
R A D R R A FT D D R
A FT A FT D R D R A F R
FT
LPC1xxx
L
A FT D R A
FT D
XTALIN
XTALOUT =
XTAL CL CP
FT D R A
RS CX1 CX2
002aaf424
Fig 34. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 22. Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): low frequency mode Crystal load capacitance CL 10 pF 20 pF 30 pF 5 MHz - 10 MHz 10 pF 20 pF 30 pF 10 MHz - 15 MHz 15 MHz - 20 MHz Table 23. 10 pF 20 pF 10 pF Maximum crystal series resistance RS < 300 < 300 < 300 < 300 < 200 < 100 < 160 < 60 < 80 External load capacitors CX1/CX2 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 57 pF, 57 pF 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF
Fundamental oscillation frequency FOSC 1 MHz - 5 MHz
Recommended values for CX1/CX2 in oscillation mode (crystal and external components parameters): high frequency mode Crystal load capacitance CL 10 pF 20 pF 10 pF 20 pF Maximum crystal series resistance RS < 180 < 100 < 160 < 80 External load capacitors CX1, CX2 18 pF, 18 pF 39 pF, 39 pF 18 pF, 18 pF 39 pF, 39 pF
Fundamental oscillation frequency FOSC 15 MHz - 20 MHz 20 MHz - 25 MHz
14.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines
The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible in
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A
order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout.
R A FT D
D R A
D R A
D R A
R A D R R A FT D FT R A
A FT A FT D R D R A F R A FT D
FT
14.4 Standard I/O pin configuration

Digital output driver: Open-drain mode enabled/disabled Digital input: Pull-up enabled/disabled Digital input: Pull-down enabled/disabled Digital input: Repeater mode enabled/disabled Analog input
Figure 35 shows the possible pin modes for standard I/O pins with analog input function:
D R A FT D
R A
The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors.
VDD open-drain enable pin configured as digital output driver output enable data output strong pull-down strong pull-up
VDD
ESD PIN ESD
VSS VDD weak pull-up pull-up enable repeater mode enable pull-down enable weak pull-down
pin configured as digital input
data input
select analog input pin configured as analog input analog input

002aaf272
Fig 35. Standard I/O pin configuration with analog input
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D R A
D R A
D R A
R A D R
A FT A FT D R
FT
14.5 Reset pin configuration

VDD VDD VDD
Rpu
R A FT D R
ESD
R A F D R A FT
A FT A FT D R A
D FT D R A
reset
20 ns RC GLITCH FILTER
PIN
ESD
VSS
002aaf274
Fig 36. Reset pin configuration
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D R A
D R A
D R A
R A D R
A FT A FT D R
FT
15. Package outline

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm
R A FT D R
R A F D R A FT
A FT A FT D R A
SOT407-1
D FT D R A
y X 75 76 51 50 ZE A
e E HE w M bp pin 1 index 100 1 ZD bp D HD w M B v M B 25 v M A 26 detail X L Lp A A2 (A 3)
A1
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 14.1 13.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.08 y 0.08 Z D (1) Z E (1) 1.15 0.85 1.15 0.85 7o o 0
16.25 16.25 15.75 15.75
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT407-1 REFERENCES IEC 136E20 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-02-01 03-02-20
Fig 37. Package outline SOT407-1 (LQFP100)

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A
D R A
TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 9 x 9 x 0.7 mm
D R A
D R A R A FT
R A D R R A FT D
SOT926-1
FT
D R A FT D
R A FT D A FT R
D R A
ball A1 index area
A2 E A A1
detail X
e1 e 1/2 e b v w
M M
C C A B C y1 C y
K J H G F E D C B A
e2 1/2 e
ball A1 index area
10
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max 1.2 A1 0.4 0.3 A2 0.8 0.65 b 0.5 0.4 D 9.1 8.9 E 9.1 8.9 e 0.8 e1 7.2 e2 7.2 v 0.15 w 0.05 y 0.08 y1 0.1
OUTLINE VERSION SOT926-1
REFERENCES IEC --JEDEC --JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-12-09 05-12-22
Fig 38. Package outline SOT926-1 (TFBGA100)

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D R A
D R A
D R A
R A D R
A FT A FT D R
FT
16. Abbreviations
Table 24. Acronym ADC AHB AMBA APB BOD CAN DAC DMA EOP GPIO IRC IrDA JTAG MAC MIIM OHCI OTG PHY PLL PWM RIT RMII SE0 SPI SSI SSP TCM TTL UART USB Abbreviations Description Analog-to-Digital Converter Advanced High-performance Bus Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Controller Area Network Digital-to-Analog Converter Direct Memory Access End Of Packet General Purpose Input/Output Internal RC Infrared Data Association Joint Test Action Group Media Access Control Media Independent Interface Management Open Host Controller Interface On-The-Go Physical Layer Phase-Locked Loop Pulse Width Modulator Repetitive Interrupt Timer Reduced Media Independent Interface Single Ended Zero Serial Peripheral Interface Serial Synchronous Interface Synchronous Serial Port Tightly Coupled Memory Transistor-Transistor Logic Universal Asynchronous Receiver/Transmitter Universal Serial Bus
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
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D R A
D R A
D R A
R A D R
A FT A FT D R
FT
17. Revision history

Table 25. Revision history Release date <tbd> Data sheet status Product data sheet Change notice Supersedes Document ID LPC1769_68_67_66_65_64_63 v.6.01 Modifications:
LPC1769_68_67_66_65_64 v.6
Pin description of pins P0[29] and P0[30] updated in Table note 5 of Table 4. Pins are not 5 V tolerant. Typical value for Parameter Nendu added in Table 9. Parameter Vhys for I2C bus pins: typical value corrected Vhys = 0.05VDD(3V3) in Table 7. Condition 3.0 V VDD(3V3) 3.6 V added in Table 16. Typical values for parameters IDD(REG)(3V3) and IBAT with condition Deep power-down mode corrected in Table 7 and Table note 9, Table note 10, and Table note 11 updated. For Deep power-down mode, Figure 9 updated and Figure 10 added. Product data sheet LPC1769_68_67_66_65_64 v.5 Part LPC1768TFBGA added. Section 7.30.2; BOD level corrected. Added Section 10.2. Product data sheet Product data sheet Product data sheet LPC1769_68_67_66_65_64 v.4 LPC1768_67_66_65_64 v.3 LPC1768_66_65_64 v.2 LPC1768_66_65_64 v.1 -
R A FT D R
R A F D R A FT
A FT A FT D R A
D FT D R A
LPC1769_68_67_66_65_64_63 v.6 20100825 Modifications:
LPC1769_68_67_66_65_64_63 v.5 20100716 LPC1769_68_67_66_65_64 v.4 LPC1768_67_66_65_64 v.3 LPC1768_66_65_64 v.2 LPC1768_66_65_64 v.1 20100201 20091119 20090211 20090115
Objective data sheet Objective data sheet -
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D R A
D R A
D R A
R A D R
A FT A FT D R
FT
18. Legal information

18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
R A FT D R
R A F D R A FT
A FT A FT D R
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
A FT D R A
Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Definitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customers sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customers applications and products planned, as well as for the planned application and use of customers third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customers applications or products, or the application or use by customers third party customer(s). Customer is responsible for doing all necessary testing for the customers applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customers third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customers general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
18.3 Disclaimers
Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or
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own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications.

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Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customers
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18.4 Trademarks
I2C-bus logo is a trademark of NXP B.V.
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
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19. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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20. Contents
1 2 3 4 4.1 5 6 6.1 6.2 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . 18 Architectural overview . . . . . . . . . . . . . . . . . . 18 ARM Cortex-M3 processor . . . . . . . . . . . . . . . 18 On-chip flash program memory . . . . . . . . . . . 18 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory Protection Unit (MPU). . . . . . . . . . . . 18 Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 19 Nested Vectored Interrupt Controller (NVIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.7.2 Interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 21 7.8 Pin connect block . . . . . . . . . . . . . . . . . . . . . . 21 7.9 General purpose DMA controller . . . . . . . . . . 21 7.9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.10 Fast general purpose parallel I/O . . . . . . . . . . 22 7.10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.11 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.12 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 24 7.12.1 USB device controller . . . . . . . . . . . . . . . . . . . 24 7.12.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7.12.2 USB host controller . . . . . . . . . . . . . . . . . . . . 25 7.12.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.12.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 25 7.12.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.13 CAN controller and acceptance filters . . . . . . 25 7.13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.14 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.15 10-bit DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.16 UARTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.17 SPI serial I/O controller. . . . . . . . . . . . . . . . . . 27 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.18 SSP serial I/O controller . . . . . . . . . . . . . . . . . 27 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.19 I2C-bus serial I/O controllers. . . . . . . . . . . . . . 28 7.19.1 7.20 7.20.1 7.21
Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S-bus serial I/O controllers . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . General purpose 32-bit timers/external event counters . . . . . . . . . . . . . . . . . . . . . . . . 7.21.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.22 Pulse width modulator . . . . . . . . . . . . . . . . . . 7.22.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.23 Motor control PWM . . . . . . . . . . . . . . . . . . . . 7.24 Quadrature Encoder Interface (QEI) . . . . . . . 7.24.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.25 Repetitive Interrupt (RI) timer. . . . . . . . . . . . . 7.25.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.26 ARM Cortex-M3 system tick timer . . . . . . . . . 7.27 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 7.27.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.28 RTC and backup registers . . . . . . . . . . . . . . . 7.28.1 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.29 Clocking and power control . . . . . . . . . . . . . . 7.29.1 Crystal oscillators . . . . . . . . . . . . . . . . . . . . . . 7.29.1.1 Internal RC oscillator . . . . . . . . . . . . . . . . . . . 7.29.1.2 Main oscillator . . . . . . . . . . . . . . . . . . . . . . . . 7.29.1.3 RTC oscillator . . . . . . . . . . . . . . . . . . . . . . . . 7.29.2 Main PLL (PLL0) . . . . . . . . . . . . . . . . . . . . . . 7.29.3 USB PLL (PLL1) . . . . . . . . . . . . . . . . . . . . . . 7.29.4 RTC clock output . . . . . . . . . . . . . . . . . . . . . . 7.29.5 Wake-up timer . . . . . . . . . . . . . . . . . . . . . . . . 7.29.6 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 7.29.6.1 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 7.29.6.2 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 7.29.6.3 Power-down mode . . . . . . . . . . . . . . . . . . . . . 7.29.6.4 Deep power-down mode . . . . . . . . . . . . . . . . 7.29.6.5 Wake-up interrupt controller . . . . . . . . . . . . . 7.29.7 Peripheral power control . . . . . . . . . . . . . . . . 7.29.8 Power domains . . . . . . . . . . . . . . . . . . . . . . . 7.30 System control . . . . . . . . . . . . . . . . . . . . . . . . 7.30.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.30.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 7.30.3 Code security (Code Read Protection - CRP) . . . . . . . . . . . 7.30.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 7.30.5 AHB multilayer matrix . . . . . . . . . . . . . . . . . . 7.30.6 External interrupt inputs . . . . . . . . . . . . . . . . . 7.30.7 Memory mapping control . . . . . . . . . . . . . . . . 7.31 Emulation and debugging . . . . . . . . . . . . . . . 8 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 9 Thermal characteristics . . . . . . . . . . . . . . . . .
continued >>
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10 10.1 10.2 10.3 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 12 13 14 14.1 14.2 14.3 14.4 14.5 15 16 17 18 18.1 18.2 18.3 18.4 19 20
Static characteristics. . . . . . . . . . . . . . . . . . . . Power consumption . . . . . . . . . . . . . . . . . . . . Peripheral power consumption . . . . . . . . . . . . Electrical pin characteristics . . . . . . . . . . . . . . Dynamic characteristics . . . . . . . . . . . . . . . . . Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . External clock . . . . . . . . . . . . . . . . . . . . . . . . . Internal oscillators. . . . . . . . . . . . . . . . . . . . . . I/O pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I2S-bus interface . . . . . . . . . . . . . . . . . . . . . . SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . USB interface . . . . . . . . . . . . . . . . . . . . . . . . SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC electrical characteristics . . . . . . . . . . . . DAC electrical characteristics . . . . . . . . . . . . Application information. . . . . . . . . . . . . . . . . . Suggested USB interface solutions . . . . . . . . Crystal oscillator XTAL input and component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL and RTCX Printed Circuit Board (PCB) layout guidelines . . . . . . . . . . . . . . . . . Standard I/O pin configuration . . . . . . . . . . . . Reset pin configuration . . . . . . . . . . . . . . . . . . Package outline . . . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.
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NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 11 March 2011 Document identifier: LPC1769_68_67_66_65_64_63

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Rev. 6.01 11 March 2011

Product data sheet

2. Features and benefits

32-bit ARM Cortex-M3 microcontroller

NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 6.01 11 March 2011

32-bit ARM Cortex-M3 microcontroller

Product data sheet

Rev. 6.01 11 March 2011

32-bit ARM Cortex-M3 microcontroller

4.1 Ordering options

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 6.01 11 March 2011

32-bit ARM Cortex-M3 microcontroller

EMULATION TRACE MODULE

TEST/DEBUG INTERFACE ARM CORTEX-M3

DMA CONTROLLER master

USB HOST/ DEVICE/OTG CONTROLLER WITH DMA(1) master slave

ROM slave MULTILAYER AHB MATRIX SRAM 32/64 kB

slave AHB TO APB BRIDGE 0

slave AHB TO APB BRIDGE 1

FLASH ACCELERATOR FLASH 512/256/128 kB

APB slave group 0 SSP1

APB slave group 1 SSP0

UART0/1 CAN1/2(1) I2C0/1 SPI0 TIMER 0/1 WDT

PWM1[7:0] PCAP1[1:0] AD0[7:0]

PWM1 12-bit ADC PIN CONNECT

P0, P2 RTCX1 RTCX2 VBAT

GPIO INTERRUPT CONTROL 32 kHz OSCILLATOR RTC

MCOA[2:0] MCOB[2:0] MCI[2:0] MCABORT AOUT PHA, PHB INDEX

BACKUP REGISTERS RTC POWER DOMAIN

(1) Not available on all parts. See Table 2.

Product data sheet

Rev. 6.01 11 March 2011

32-bit ARM Cortex-M3 microcontroller

Pin configuration LQFP100 package

ball A1 index area 1 A B C D E F G H J K

Transparent top view

Pin configuration TFBGA100 package

Pin Symbol P0[3]/RXD0/AD0[6] P1[16]/ENET_MDC P0[9]/I2STX_SDA/ MOSI1/MAT2[3] RTCK

Pin Symbol 3 7 11 VDD(3V3) VDD(REG)(3V3) -

Pin Symbol 4 8 12 P1[4]/ENET_TX_EN P0[4]/I2SRX_CLK/ RD2/CAP2[0] -

Row B 1 2 3 VSS 4 P1[1]/ENET_TXD1

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 6.01 11 March 2011

32-bit ARM Cortex-M3 microcontroller

Row C P0[2]/TXD0/AD0[7] P0[8]/I2STX_WS/ MISO1/MAT2[2] n.c. P2[2]/PWM1[3]/ CTS1/TRACEDATA[3] -

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 6.01 11 March 2011

32-bit ARM Cortex-M3 microcontroller

P1[19]/MCOA0/ USB_PPWR/ CAP1[1]

P1[28]/MCOA2/ PCAP1[0]/ MAT0[0] -

6.2 Pin description

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2011. All rights reserved.