k, = k M 5 - 8 =
(Ib)
0-7803-5471-0I99l$10.0001999 IEEE
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(M3,M7) and (M2,Ms). The voltages V,,V3 and V4 are the
inputs signals and the voltage Vc is the common mode
voltage which bias the transistors MS-8 in the linear
region. Solving the system of eqs.( 1a) and (1 b) we obtain
the current drawn each branch. These currents for the
four branches are given by the following equations
- -I
and k l , kz are the transconductance parameters of Figure 2. The circuit of the two-quadrant divider
transistors (MI-M4)and (M5-M,) respectively (see eq.( 1).
From eq.(2-5) the currents which draw each branch are It has a differential input voltage Vl-V2and a differential
functions of two voltages; the voltages at the gates of input current I,-&, while the differential voltage V,, -VOz
transistors which operate at the saturation and at the is the output of the circuit. Since the gates of transistors
linear region. M5,8and M6,, are tied to the drains of transistor and
Taking into account the first and the second order terms M2.4 , respectively, the transistor M5.8operate into the
of the Taylor’s series expansion, for a function of two linear region.
variables x, y around zero, the currents of each branch The constant current IC is the common mode input
(eq.(2)-(5)) is expanded as current of the differential input current which establishes
the common mode voltage of the differential output
voltage. The equation that relate the current IC with the
common mode voltage output V,, is :
2.2 Divider where Ia Iw are the two output currents of the CCII. The
CCII performs two follower operations, voltage and
The proposed divider circuit is shown in Fig.2. It current: VFV, and Zx= &=-Iw, where current Ix is the
consists of two parts; the fvst part is the voltage-variable current at port X. Thus the two output currents are given
resistance (the circuit in the dashed line fiame) and the by
second part is a second-generation current conveyor
(CCII).
The voltage-variable resistance (VVR) circuit is where V , is the input voltage at port Y of the CCII.
generated from the multiplier if V,, V4 voltages are tied Combining the eqs(10,12,13) the output voltage of the
to the corresponding output nodes V,I and V,2. two-quadrant divider circuit is given by
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OSV, 8KH2, while the voltage V, is a sinusoidal signal
of O.SV, 200KHz.The simulated -3dB bandwidth of the
where s= is the sensitivity of the divider . It is multiplier is up to 400MHz while the total harmonic
distortion level of the output voltage of the multiplier
clear from eq.( 14) that the output voltage is proportional circuit was found to be less than 0.3%.
to the quotient of two analogue voltage inputs; the
voltage V 2 , which is the numerator input and the voltage
VI is the denominator input. The proposed circuit, also
features independent control of the sensitivity by the
resistance R.
For easy tunability of the sensitivity the denominator
G . R in the expression of the sensitivity must take
considerably large values. Therefore, in order to use
reasonably small values of the resistance R, the constant 0 1 4- 1x1; '/7! .........
.! .! i fT i . .;....-.....
i...........i ...........+.....".j
i . .;; ........................i;.
:
i .
.
1 .
. T F
. . . I .
i
: . : . .: : . I
j
Figure 3. The microphotograph of the multiplier For the proposed divider circuit, the CCII circuit was
previously designed with only one current output Z [ 131
Fig.4a shows the experimental DC transfer and fabricated now on the same chip with the VVR
characteristics of the multiplier. It can be seen that the circuit with an additional current output W in order to
output voltage V, against the input voltage VI for implement the proposed quotient circuit. The
changes of VI from -0.75V to 0.75V and V2 from -0.5V measurement conditions are : power supply +/-2.5V,
to OSV with 250mV step. The experimental and the current Ic=600pA and R=lOKf2.
calculated data are displayed together. This multiplier The curves in Fig.5a show the output voltage V,-J against
has a linear differential input range up to k l V with a VI with V2 taking values from -1.2 to 1.2V with 0.3V
nonlinearity error less than 0.2%. To demonstrate its steps. The output voltage range is *1.5V whereas the
time-domain response, two signals are applied to the voltage VI varies from 0.05V to 1.4V with less than 1mV
proposed multiplier. FigAb shows the output voltage V, offset for V2=0. The experimental and the calculated data
and the input voltage VI. VI is a sinusoidal signal of are displayed together. The relative error is less than
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52.5% for -1.2V<V2<1.2V and 0.1V<V1<1.2V power supply of f 1 . 5 V and for the differential input
respectively,while the output voltage is -1.5V< V,< 1SV. range k 1 V has a linearity error less than 0.2%. The
Fig.5b shows the experimental waveforms at the output simulated -3dB bandwidth is up of 4OOMHz and the total
where the numerator is held constant V2=1 V and V, is a harmonic distortion level was computed less than 0.3%.
20KHz triangular wave varying between 0 and 1V. It is This multiplier is expected to be useful in many analog
obvious that the output voltage VO is proportional signal-processing applications. The divider offers the
facility of independent control of the sensitivity and has
acceptable precision useful in analog signal processing,
fuzzy control and instrumentation applications.
5. REFERENCES
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