8 Vlsi-Design

Code No: RR420203 Set No.
1
IV B.Tech II Semester Regular Examinations, Apr/May 2007
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Define threshold voltage of a MOS device and explain its significance.
(b) Explain the effect of threshold voltage on MOSFET current Equations. [8+8]
2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16]
3. Design a stick diagram for two input n-MOS NAND and NOR gates. [16]
4. Design a layout diagram for two input nMOS NAND gate. [16]
5. Two nMOS inverters are cascaded to drive a capacitive load CL =14Cg as shown in
Figure 5. Calculate the pair delay Vin to Vout in terms of τ for the given data.
Inverter -A
LP.U = 12λ , WP.U = 4 λ , LP.d = 1 λ , WP.d = 1 λ
Inverter -B
LP.U = 4λ , WP.U = 4 λ , LP.d = 2 λ , WP.d = 8 λ [16]
Figure 5
6. (a) What are the advantages and disadvantages of the reconfiguration.
(b) Mention different advantages of Anti fuse Technology. [8+8]
7. (a) What is the goal of VHDL synthesis step in design flow?

(b) Explain how register transfer level description provides optimized synthesis
netlist. [8+8]
8. (a) Mention the properties of the twin oxide.

(b) Clearly explain about ION implantation step in IC fabrication. [6+10]
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Code No: RR420203 Set No. 2
VLSI DESIGN
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1. A MOS Transistor in the active region measured to have a drain current of 20 µA

when VDS =Veff. When VDS is increased by 0.5V, ID increases to 23 µA. Estimate
the out impedance rds , and the out impedance constant λ. [16]
2. With neat sketches explain how npn transistor is fabricated in Bipolar process. [16]
3. Design a stick diagram for the PMOS logic shown below Y = (A + B).C [16]
4. (a) What do you mean by layout of a component.
(b) Draw neat layout diagrams for NMOS and PMOS transistor. [6+10]
5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 5, If n-channel sheet resistance is 5 × 104 Ω per square. [16]
Figure 5
6. Using PLA Implement Full-adder circuit. [16]
7. What is need for RTL simulation? Clearly explain RTL simulation flow in the
ASIC design flow and also mention few leading simulation tools. [16]
8. Explain about the following two oxidation methods.
(a) High pressure oxidation.
(b) Plasma oxidation. [8+8]
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VLSI DESIGN
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1. (a) With neat sketches explain the formation of the inversion layer in P-channel
Enhancement MOSFET.
(b) An NMOS Transistor is operated in the triode region with the following pa-
rameters VGS = 4V ; Vtn = 1V ; VDS = 2V ; W/L = 100; µnCox = 90 µA/V 2
Find its drain current and drain source resistance. [8+8]
2. With neat sketches explain how Diodes and Resistors are fabricated in pMOS
process. [16]
3. Design a stick diagram for the CMOS logic shown below Y = (A + B + C) [16]
4. Design a layout diagram for the PMOS logic shown below Y = (A + B).C [16]
5. Calculate the gate capacitance value of 1.2µm Technology minimum sized transistor
with gate to cannel capacitance value is16 × 10−4 pF/µm2 . [16]

7. What is need for RTL simulation? Clearly explain RTL simulation flow in the
ASIC design flow and also mention few leading simulation tools. [16]
8. With neat sketches explain Atmospheric- pressure chemical vapor deposition method.
[16]
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VLSI DESIGN
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1. (a) With neat sketches explain the formation of the inversion layer in P-channel
Enhancement MOSFET.
(b) An NMOS Transistor is operated in the triode region with the following pa-
rameters VGS = 4V ; Vtn = 1V ; VDS = 2V ; W/L = 100; µnCox = 90 µA/V 2
Find its drain current and drain source resistance. [8+8]
2. (a) Compare between CMOS and bipolar technologies.

(b) With neat sketches explain nMOS fabrication process. [8+8]
3. What is a stick diagram and explain about different symbols used for components
in stick diagram. [16]
4. Explain with suitable examples how design the layout of a gate to maximize per-
formance and minimize area. [16]
5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 5, If n-channel sheet resistance is 5 × 104 Ω per square. [16]
Figure 5
7. What are the different report files that are provided by the place and route tool
and discuss clearly about each report file. [16]
8. Explain about the following Die bandings.
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(a) Eutectic die bonding.
(b) Epoxy die bonding. [8+8]
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Code No: RR420203 Set No.

7. (a) What is the goal of VHDL synthesis step in design flow?

8. (a) Mention the properties of the twin oxide.

1. A MOS Transistor in the active region measured to have a drain current of 20 µA

6. (a) What are the advantages and disadvantages of the reconfiguration.

2. (a) Compare between CMOS and bipolar technologies.

8. Explain about the following Die bandings.

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