Lab Assignment: Computer Organization and Architecture (Course No: CS19001)

Date: 19/8/11

Class

Instruction Add Comp Arithmetic Add immediate Complement Immediate Logic AND XOR Shift left logical Shift right logical Shift Shift left logical variable Shift right logical Shift right arithmetic Shift right arithmetic variable Load Word Memory Store Word Unconditional branch Branch on minus Branch Branch on not minus Branch on zero Branch on not zero Branch on carry Branch on no carry Sub-routine Branch Register Call Branch and link

Usage add rs,rt comp rs,rt addi rs,imm compi rs,imm and rs,rt xor rs,rt shll rs, sh shrl rs, sh shllv rs, rt shrl rs, rt shra rs, sh shrav rs, rt lw rt,imm(rs) sw rt,imm,(rs) b L bm L bnm L bz L bnz L bcy L bncy L br rs bl L

Meaning rs (rs) + (rt) rs 2s Complement (rs) rs (rs) + imm rs 2s Complement (imm) rs (rs) (rt) rs (rs) (rt) rs (rs) left-shifted by sh rs (rs) right-shifted by sh rs (rs) left-shifted by (rt) rs (rs) right-shifted by (rt) rs (rs) arithmetic right-shifted by sh rs (rs) right-shifted by (rt) rt mem[(rs) + imm] mem[(rs) + imm] (rt) goto L if (Sign) then goto L if Sign then goto L if Zero then goto L if not Zero then goto L if Carry then goto L if Carry then goto L goto (rs) goto L; 31 (PC)+4

Our processor KGP-RISC has the above Instruction Set Architecture (ISA). Assume that the processor has a 32 bit word, with all the registers and memory elements having 32 bit data. The register le has 32 registers. The ALU along with performing the arithmetic and logic operations, also generates special ags, namely, Sign, Carry, Zero. The address line of the memory is also 32 bits. We are to develop rst the op-code format for the above instruction set, identify the data path element and design the data path along with the control signals. Subsequently, we shall rst develop a single-cycle instruction execution unit for KGP-RISC.

Unlike your previous experiments, you have to submit a (handwritten or otherwise) laboratory le depicting the design as it evolves along the following steps. In the following guideline, note that at various steps, schematic diagrams are asked for they are meant to be submitted in the laboratory le. You are also advised to designate the modules as indicate bold-faced below for uniformity of reference (by all of us) during the class sessions. You can of course use other submodules (for better modularity) with designations of your choice! Proceed step-by-step as follows: 1. For the above Instruction set, evolve a suitable instruction format. Clearly specify the elds of the opcode and mention how each of the above instructions are to be encoded. Keep in mind, while deciding the op-code, that you should keep provisions for adding more instructions to the ISA. 2. A single cycle data path design the data path module: (a) Examine the fetch operation and identify the instruction memoryCPU interface module; underline whether you need to store the instruction in a register or not, i. Give a neat schematic diagram of this part, ii. Give the RTL interpretation of the fetch operation and the corresponding control signals (in a table for documentation) let this table have three columns as indicated below: the rst column for the instruction, the Second column for the RTL interpretation of the instruction, i.e., the concurrent register transfer operations taking place, and the third column for the list of the control signals. Let us refer to this table as table 2(a)ii. iii. Give the Verilog structural encoding of this module (b) Examine the ALU instructions and identify i. the ALU architecture involving the operation control lines vis-a-vis the op-codes of these instructions and the decoder, ii. Give a neat schematic diagram depicting the ALU with its input and output signal names, iii. the Verilog structural encoding of the ALU module, iv. the communication between the register and the ALU (that is, the ALU buses and the general purpose register ports, v. the register bank structure vis-a-vis the rs and rt elds of the instructions, vi. give a neat schematic of the register bank (obviously not showing all the registers) clearly depicting the register select logic from the read (address) port(s) and the write (address) port(s), the connection of the input data lines (i.e., the ALU output bus) with the individual register inputs and the connection of the output data lines (i.e., the ALU input buses) with the individual register output lines, vii. the Verilog structural encoding of the register bank module viii. enter in table 2(a)ii the RTL interpretation of each of these instructions and list the corresponding control signals (c) Examine the Branch instructions and identify: i. the condition detector circuit (attached to the ALU output) give a schematic diagram of the logic circuit, ii. the Verilog structural encoding of the condition detection module,

iii. the condition ag registers the Verilog structural encoding of condition ag register module, iv. the condition select logic using the condition code specier eld of the instruction a clear logic schematic and the Verilog structural encoding of the condition select module, v. the branching logic, i.e., the PC update circuit, (do NOT take up the structural coding yet till the next two steps!) give a clear schematic diagram of this circuit arrived at up to this step, (d) Examine the subroutine call-return (bl, br) instructions and enhance the PC modier circuit: i. branch through register (br) instruction and the enhancement in PC update circuit ii. branch and link (bl) instruction and the enhancement needed modify the Verilog structural encoding of the register bank module accordingly iii. the Verilog structural encoding of the PC and its associated read/update circuit (PC-circuit module) iv. ll in table 2(a)ii, the RTL interpretation of the branch instructions and the subroutine call-return instructions and list the corresponding control signals. (e) Examine the load-store instructions and identify i. the need of separate data and instruction memory (for single cycle data paths), ii. the CPU-memory interface circuit comprising a unidirectional external address bus from CPU to memory, a bidirectional external data bus to and from CPU and memory, the bidirectional (tristate) driver circuit for the data bus, iii. Give a neat schematic and the Verilog structural encoding of the Bidirectional Bus Driver module iv. give a neat schematic of the CPU-data memory interface v. the Verilog structural encoding of the module. vi. ll in table 2(a)ii, the RTL interpretation of the load and store instructions and list the corresponding control signals. 3. Design the the instruction memory and the data memory modules (a) Design a 2 dimensional memory array with each cell comprising a 32 bit word (register) with 32 address lines compatible with the CPU-instruction memory interface identied in course of design of the data path. Thus, the memory has a two dimensional structure, with two separate address decoders to select a memory cell, using the column and row addresses. The memory is only word addressable, i.e., each memory cell has a data of width 32 bits. (b) give a neat schematic diagram and the Verilog structural encoding of the module memory array (c) Give the Verilog structural encoding of the Instruction Memory module (d) Design the data memory module. Note that it should have an internal Bidirectional Bus Driver module used in the CPU-data memory interface. 4. Write the truth table for the controller signals as a function of the opcode and the function code in the instruction format. Note that for a single cycle implementation of the controller there is no state and the design is purely

combinational. Instead of giving a monolithic single module for the controller, it is advised to give a hierarchical organization having submodules along the modules identied so far in the previous steps; specically, therefore, the submodules could be ALU control, register bank control, PC control, etc.