E E E 1999 International Conference on Power Electronics and Drive Systems, PEDS'99, July 1999, Hong Kong.

Analysis and Design of Modified Deadbeat Controller

for 3-Phase Uninterruptible Power Supply

Jun-Seok Cho, Seung-Yo Lee, Hyung-Soo Mok, Gyu-Ha Choe

Dept. of Electrical Eng., Kon-Kuk University
Mojin-dong 93-1, Kwang-jin Gu,Seoul 143-701, Korea
Phone +82-2-450-3486 Fax +82-2-447-9 186

Abstract-This paper proposes a modified deadbeat control scheme
of 3-phase PWM inverter with LC filter for uninterruptible power
supply(UPS). The deadbeat current and voltage controller are
used to obtain the fast transient response of UPS system in general.
However, conventional deadbeat controller has a defect to become
unstable. In this paper, to remove the defect which makes a system
unstable due to the same pole placement of conventional deadbeat
current and voltage controller, modified deadbeat algorithm,
which produces a first-order exponential response during one
input step, is proposed. Because the overall controller is
constructed by deadbeat control, the response of the proposed
control system is fast and the structure of controller is simple. In
addition, the full-order state and disturbance observer is
constructed to compensate the disturbances generated by a
sudden change of load currents. The proposed disturbance
observer estimates state values of load currents within a finite time,
and cancels the disturbances by adding feedforward compensation
loop in the control system. The validity of the modified deadbeat
control scheme is proved by the results of simulation and
experiment
modified deadbeat control algorithm is proposed. The modified
deadbeat algorithm produces a first-order exponential response
during one input step, which has an effect to separate the pole
of voltage control loop from that of current control loop. The
separate pole placement of voltage and current controller can
guarantee the robustness of control loop. In addition,
conventional method requires the information of load current
for compensation of disturbances, which is generated by abrupt
change of load currents. Hence, this control system needs the
load current sensors. In this paper, to estimate the load current
with other states, full order disturbance observer algorithm is
used. The presented disturbance observer estimates the load
current without the current sensor and cancels the disturbance
by adding feedforward compensating loop in voltage control
loop. By the proposed control algorithm, the THD of output
voltage of the UPS system is reduced and the transient response
of the controller is improved. Through the results of simulation
and experiment, the proposed scheme was verified

I. INTRODUCTION 11. DISCRETIZATION

OF STATE EQUATION
FOR UPS

In recent years, the various electronic machines as well as

computer systems have been increasingly used and hence the
reliance of the power source has been a more important matter.
If a power source shut down even for a short period, the
damage would be serious. Therefore, the demand of UPS
system to avoid damage is much more increased. The objective
of UPS system is to supply sinusoidal voltage with constant
amplitude and frequency to loads without any interruption in VX
all cases of power source failure. The quality of UPS can be Fig. 1 Overall configuration of UPS system.
evaluated by the total harmonic distortion(THD) value of
output voltage and characteristics of transient response. In Fig.1. shows overall configuration of UPS system which
general, the controllers of UPS have double control loop that consists of 3-phase inverter, LC ripple filter and dc-link
consists of voltage major loop and current minor loop. And, to batteries. By the relation of the system input and output, the
improve output voltage of UPS, digital controller has been following differential equations can be written for each phase.
adopted for a high performance.
Also it has been noted that deadbeat controller has very fast
transient response as the digital control system [1],[2]. But this
control method has a. tendency to make the system unstable,
due to the same pole placement of characteristic equations
which affect the performance of closed-loop current and
voltage controllers. So, to solve the defect of conventional
deadbeat control such as same pole placement problem, a

0-7803-5769-8/99/$10.0001999IEEE

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 Equations (1)-(3) can be transformed into state equation on k l l = k22 k12 = 4 2 1
the synchronous reference frame. Choosing the capacitor
111 = I 2 2 I12 = -121
voltage and inductor current as the state variables, the state
mll = m22 m12 = -m21
equation can tle represented like Eq. (4),(5). And which are the
d-q variables of voltage and current on the synchronous
Equation (10) is the state equation of the inverter current and
reference frame. ( 1 1 ) represents the state equation of the capacitor voltage loop.
A reference voltage fo; the output on the synchronous
reference frame will be given as Eq. (1 3).

111. MODIFEID
DEADBEAT
CONTROL

v,
0

Equation (4) 2nd ( 5 ) can be put into the following matrix form:

State vectors of the inverter current and the capacitor voltage

can be written IAqd = [IAq,zAd]', vcqd = [v,q.vCd]T respectively.
In the normalized form Eq. (6), the vector v is the disturbance
- + VOLTAGE
CONTROL
l+Tk
-
term that is induced into the loop of the control. I I
Fig. 2 The control block diagram with disturbance observer

'Aqd = Aqd -4- vAqd - vcqd (7) Fig.2. shows the proposed deadbeat control system with the
disturbance observer. The controller consists of the current
'Cqd = 'Cqd Aqd - (8) controller, the voltage controller and disturbance observer. The
structures of control block have double control loops, and
Assuming that V, and I , are constant during sampling especially the voltage controller is modified by using proposed
interval T s , Eq.(7) and (8) of the inverter current and the scheme, which is explained in followings.
capacitor voltage can be converted into the discrete-time state
equations of (10) , ( 1 1) and ZOH(Zero Order Hold) conversion
method is adopted for discretization A. Current Controller

The current controller is used as the conventional deadbeat

In normalized conversion form Eq. (9), I is a 2x2 unit matrix,
T, is the sampling time
control scheme. Equation (10) can be transformed into the
state equation of z domain as Eq. (14) and Fig.3 represents the
current control block diagram by using Eq. ( 1 4 ) . The used
current control loop includes the coupling term on each d-q
frame. Therefore, to decouple the coupling elements, the
decoupling matrix Ed and z d l of Eq. (15), (16) should be
included in the current control loop

1004
 (Assuming I , , >> I,, , in case of low sampling time)

Adopting PI controller like Fig.3, the open loop transfer

function of the current controller can be obtained as follows : But, this function tends to make the control loop unstable easily,
- because of the same pole placement of conventional deadbeat
~L - t ( N l z - N , )
N ~ z - N-- current and voltage controller on the origin of the z domain.
G,(z) = (17) Therefore, to get the more robust stability of the control
z-1 z - K z2-(K+l)z+K
system, the modified deadbeat control scheme is proposed in
this paper. The poles of modified deadbeat voltage controller
To get deadbeat control characteristic, the pole of the closed should be fiather from the origin than those of the current
loop transfer function need to be placed on the origin of the z
controller. To guarantee the robustness of system, the voltage
domain. The characteristic equation of closed-loop becomes controller must have much lower bandwidth than current
1+ Go( z ) = 0 . Therefore, the gain N , ,N , of the controller controller. But, to preserve a quasi-deadbeat characteristic,
kll + 1 ,N2 = -kl1 voltage controller has to be modified.
are set as N I = - The deadbeat controller by the modified algorithm produces a
11 1 11 1
finite first-order exponential response in one step of the input.
Here, an exponential function like Eq. (2 1) is used as the output

vcqdk-El
I I
of the voltage control loop. Then the output y ( t ) is transformed
into z domain like Eq. (22).

where a is the time constant, and T,is sampling time. The

value of a determines the bandwidth of voltage controller.
I I
Fig.3 Deadbeat current control loop

B. Modzjied Deadbeat Voltage Controller

kqd
Current ,
Equation (1 1) can be transformed into Eq. (18) by z-transform.
Similar to the former case of the current controller, the voltage
control loop also includes the coupling terms on the each d-q
frame. To decouple the coupling elements, decoupling matrix
Md and K d 2expressed as Eq. (19), (20) is added in the
voltage control loop. Fig. 4 shows the block diagram of voltage I I

tkqd
control loop. If current minor loop is assumed to be an ideal
Fig. 4 Simple block diagram of voltage control loop
current source, the feedforward loop of Fig. 4 will compensate
the disturbance caused by load current. In conventional case, From Fig. 4, a simple open loop transfer function of the voltage
the deadbeat controller has the proportional function (like P control loop is derived as follows:
controller).

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If the unit feadback loop transfer function is expressed like
G c ( z )of Eq. 1(24),the voltage controller D ( z ) in Fig. 4 can be
-
represented like (25) (26).
rbll b121

The observer equation derived by Eq(28) is written as follows:

Where the observer gain G and feedback matrix F.

By using the modified voltage controller, the instability of the
controller output is largely reduced and hence the robustness of
the control system is improved. As the effect of improved
rgll g121
characteristic:; of the controller, the rated dc-link voltage of the
PWM inverter can be reduced.

C. Disturbance Observer

Without current sensors, to compensate disturbances of load

currents a disturbance observer is designed. The state variables
x=[Vcq VCd 14 IM]' can be estimated by using a full order
observer. Elq. (26) and (27) represent the state equation of
voltage major loop, and that equation estimate not only the
next-sampled voltage but also the disturbance caused by load
current on d-q axes. The d-q variables of inverter current IAqd
and capacitor voltage vcqd are measurable, so disturbance term
IL, and ILd can be obtained by disturbance full order observer
simultaneously. The state equation for voltage control is
derived as follows:
X=Ax+Bu
y =cx
Because the matrix G can be chosen arbitrarily, G must be
designed by the pole placement method. To determine the
value of matrix G, the observer characteristic equation is used
as follows
w - FI = a4+ p,a3+ p2a2+ p3a+ p4
I (32)
First, the observer pole must be chosen to obtain gain G, and
the pole should be placed closer than voltage controller poles
on origin of z domain. Such pole location implies that the
transient response of observer is much faster than that of
voltage controller. If the poles of observer characteristic are
less than unit circle in z domain, the errors of estimated state
are converged into zero.

e(k + 1) = Fe(k) (33)

where e(k) = x ( k ) - i(k)

So, it is assumed that the disturbance caused by load current

can be compensated in voltage major loop, and disturbance
equation is obtain such as following state vector.

Eq. (27) can be transformed into discrete state equation (28) by

ZOH conversion method.

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 Iv. SIMULATION AND EXPERIMENT
RESULTS Fig.l7(a) shows the A-phase load current of diode rectifier
measured by sensor and Fig. 17@) represents the load current
The system parameters for simulation and experiment are estimated by using disturbance observer. Here, it is shown that
shown in Table 1. The sampling period for real time processing disturbance observer exactly can estimate the load currents.
is 100[usec] and the LC filter are designed in the view of the
performance of the controller and the THD value of the output
voltage. To prove the validity of the proposed algorithm,
e e- e
simulation and experiment was executed for R-L linear and
rectifier nonlinear load, respectively. The results the proposed 'I.

method are compared with the results by conventional one.

r
. .. .
n p m
Table 1. Svstem Parameter -
Y
m
Y
u
Y
*- --
I L, : Filter Inductance I 400CPHI I . I ,

I C, : Filtercapacitance I 400 [yF] 1 2-

'I
5-

'
1 v*
L
: Reference Peak Voltage I 179 [VI I 1
Vdc : Dc-link Voltage 360 [VI
(Change of the rated load power: from 0% to 100%)
T. : Sampling Period 100 [psecl
Dc Capacitor of Rectifier Load 4700 [yF]
Inductance of Load 2 [mHI
Rated Load 5 rkVAl

-
Fig. 5 7 shows the simulation results for R-L linear load and
represents the effect of disturbance observer. Fig. 5 shows the _-
2 %-

3-phase load current waveforms when the rated power of the m

Y a
W

load is changed from Or?] to loo[%]. Fig. 6 is the output

Y
.Y. *

voltage of the UPS in case that the disturbance compensation is

1.
not included in the control loop. Fig.7 represents the
simulation result by the proposed control method with =-
I< 0015 om o m DOT 0115 012
disturbance observer. (a) of Fig. 6 and Fig. 7 represent the (a) (b)
waveforms of the line-to-line output voltage and (b) shows the Fig. 6.0utput voltage(in case that the disturbancecompensation is not
d-q representation of the output voltage, respectively. It is included in the control loop)
(a) Line-to-line output voltage waveforms.
clear that the output voltage of the UPS controlled by proposed
(b)d-q representation of the output voltage.
control method is maintained constantly in spite of the load
change.
-
Fig. 8 10 show the simulation results for nonlinear rectifier
load. Fig. 8 depicts the A-phase load current generated due to
the diode rectifier load. In Fig. 8, it is shown that the rated load c
power is changed from O[%] to loo[%]. Fig. 9. shows the
simulation results which the load current are compensated by I-
using sensors and Fig. 10. represents the simulation results by
the proposed disturbance observer. In both cases, (a) is the line-
to-line inverter output voltage and (b) shows the reference
voltage and inverter output voltage to the value of d-q. It is
noticed that the compensating characteristics to compensate a x-
sudden change of load currents are similar in both cases.
-
Fig. 11 13 shows the experiment results for R-L linear load.
5' 8' 3iO1 L 1, !,,, L L' J. d, im
Ir.8- E
.0.m5 0.m
oim5'd,,
0.m 0.1,
L5 L?
0.115 O.l?

(4 (b)
Fig. 13 represents that proposed scheme compensates the Fig.7. Output voltage(in
voltage@ case that the disturbance compensation by proposed
disturbance caused by load current and guarantee the fast scheme is included in the control loop)
(a)Line-to-line output voltage waveforms.
transient response of output voltage. And THD of capacitor
(b)d-q representation of the output voltage.
voltage is less than 1%. Fig. 14-16 shows the experiment
results for nonlinear rectifier load. Fig.15 is the case that
disturbance is compensated by current sensor and Fig.16
represents that proposed observer compensates the disturbance.
The THD in nonlinear load is less than 2.5%

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 40 0 s !
001.
!
6103
!
0112
!O l i l l
011

Fig. 8. Diode rectifier nonlinear load currents on phase A Fig. 11 I DIV.]

(change of the rated load power : from O["/,] to 100) (Change of the rated load power: from O%to 100%)

(4
Fig.9. Output v,oltage(incase that the disturbance compensation by using (a) (b)
current sensors is included in the control loop) Fig. 12.0utput voltage(in case that the disturbance compensation is not
(a) Line-to-line output voltage waveforms. included in the control loop)
(b)d-q representation of the output voltage. (a) Line-to-line output voltage waveforms. [90V I DIV.]
(b)d-q representation of the output voltage. [60V I DIV.]

s
_._ o -
%
g E
y
..
,. * .

_ .
12 7- '$.OX &,E5 0.0s E.IS Q.ll5 I.!1

(a) (b) (4 (b)

Fig. 10.0utput voltage(in case that the disturbance compensation by using the Fig. 13. Output voltage(in case that the disturbance compensation by proposed
proposed observer is included in the control loop) scheme is included in the control loop)
(a) Line-to-line output voltage waveforms. (a) Line-to-line output voltage waveforms. [90V / DIV.]
(b)d-q representation of the output voltage. (b)d-q representation of the output voltage. [60V I DIV.]

1008
 (b

t i i" i i i ' i i i ' i I

Fig. 14. Diode rectifier nonlinear load currents[lOA / DIv.1 Fig.17. (a) Load current (b) Estimated load current
(.change of the rated load power. from 0[0/0] to 100)

V. CONCLUSION

In this paper, the modified deadbeat control scheme is proposed

to obtain more stable controller than the conventional one.
Also, to estimate the load currents, the disturbance observer is
constructed. Feedfonvard compensating loop constructed by
the designed observer compensates the disturbances generated
due to the change of the load current. Hence, the current
sensors to measure the load currents is not needed. In addition,
by using the modified deadbeat control, the instability in
conventional deadbeat controller can be reduced largely and
dc-link voltage is lower than that of conventional one.
Therefore the THD of the output voltage can be less than 3% in
linear or nonlinear load, and the transient response charac-
(a) (b) teristics of the controller are improved.
Fig.15. Output voltage(in case that the disturbance compensation by using
current sensors is included in the control loop)
(a) Line-to-line output voltage waveforms. [9OV / DIV.]
(b)d-q representation of the output voltage. [60V / DIV.] ACKNOWLEDGMENTS
This work was supported by a grant No. 962-0701-01-3 from
Korea Science and Engineering Foundation.

REFERENCES

1. T. Kawabata et al., "Dead Beat control Three Phase PWM Inverter",

IEEE Transaction Power Electronics. vol5. pp. 21-28 Jan. 1990.
2. T. Kawabata et al. "Digital Control of Three-phase PWM Inverter
with LC Filter", IEEE Transaction Power Electronics. vol 6. pp. 62-
72 Jan. 1991.
3. Youichi Ito et al., "Digital Control of Three-phase PWM Inverter for
UPSs Using Dead-beat Observer", PCC-Yokohama '93, pp. 79-84
1993.
4. K. P. Gokhale, A. Kawamura, and R. G. Hoft, "Deadbeat
microprocessor control of PWM inverter for sinusoidal output
waveform synthesis", in Proc. IEEE PESC., Toulouse, France, 1985,
pp. 28-36
(a) (b) 5. T. Yokoyama, A. Kawamura "Disturbance Observer Based Fully
Fig. 16. Output voItage(in case that the disturbance compensation by using the Digital controlled PWM Inverter for CVCF Operation", IEEE
proposed observer is included in the control loop) Transaction Power electronics. Vo1.9. N0.5. SEP, 1994.
(a) Line-to-line output voltage waveforms [90V / DIV.] 6. Osman Kukrer, "Deadbeat Control of a Three-phase Inverter with an
(b)d-q representation of the output voltage. [60V / DIV.] Output LC Filter", IEEE Transaction Power electronics. Vol.11. NO.
1. JAN,1996
7. J.G. Hwang, S.Y. Lee, G.H. Choe, "A Novel Detecting Noise
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