Anda di halaman 1dari 15

EECS240 Spring 2010

Lecture 3: MOS Models for Design

Elad Alon Dept. of EECS

Why Modeling?
Analog circuits more sensitive to detailed transistor behavior
Precise currents, voltages, etc. matter Digital circuits have much larger margin of error

Models allow us to reason about circuits


Provide window into the physical device and process Experiments with SPICE much easier to do

EECS240

Lecture 3

Levels of Abstraction
Best abstraction depends on questions you want to answer Digital functionality:
MOSFET is a switch

Digital performance:
MOSFET is a current source and a switch

Analog characteristics:
MOSFET described by BSIM with 100s of parameters? MOSFET described by measurement results?
EECS240 Lecture 3 3

Why Not Square Law?


Square law model most widely known:
I D , sat = 1 W 2 n Cox (VGS Vth ) 2 L

But, totally inadequate for short-channel behavior Also doesnt capture moderate inversion
(i.e., in between sub-threshold and strong inversion)

EECS240

Lecture 3

Square Law Model Assumptions


Charge density determined only by vertical field Drift velocity set only by lateral field Neglect diffusion currents (magic Vth) Constant mobility And many more

EECS240

Lecture 3

A Real Transistor
Gate Electrode
Gate Depletion Quantum Effect

Ultra-thin Gate Dielectric


Direct Tunneling Current Quantum Effects

S/D Engineering
S/D resistances S/D leakage

Short Channel Effects


Velocity Saturation and Overshoot Source-end Velocity Limit

Retrograde Doping
Body effect

Pocket Implant
Reverse short channel effect Slower output resistance scaling with L

EECS240

Lecture 3

To Make Matters Worse


Run-to-run parameter variations:
E.g. implant doses, layer thickness, dimensions Affect VTH, , Cox, R ,

In SPICE use device corners: nominal / slow / fast parameters (tt, ss, ff)
E.g. fast: low VTH, high , high Cox, low R Combine with supply & temperature extremes Pessimistic but numerically tractable improves chances for working Silicon
EECS240 Lecture 3 7

Corner example: VTH


Corners just shift Vth
Probably not real (PMOS doesnt look real anyways)

Variations probably bigger than reality too


Fab wants you to buy everything they make

EECS240

Lecture 3

Now What?
Rely purely on simulator to tell us how devices behave?
Models not always based on real measurements Model extraction is hard Models inherently compromise accuracy for speed

Need to know about important effects


So that know what to look for Model might be wrong, or doesnt automatically include some effects E.g., gate leakage

EECS240

Lecture 3

VTH: Halo Doping

Source: R. Dutton and C.-H. Choi

EECS240

Lecture 3

10

VTH: Reverse Short-Channel Effect

EECS240

Lecture 3

11

ID: Velocity Saturation

Drift velocity initially increases linearly with field Eventually carriers hit a speed limit In the limit, ID (VGS-Vth)
EECS240 Lecture 3 12

ID: Vertical Field Mobility Reduction


Mobility actually depends on gate field
Hard to run when there is wind blowing you sideways (into a wall)

More technical explanation:


E-field pushes carriers close to the surface Enhanced scattering lowers mobility

EECS240

Lecture 3

13

ID: Sub-Threshold Region


Current doesnt really go to 0 at VGS = Vth Lateral BJT:

log(

EECS240

Lecture 3

14

ID: Weak Inversion Channel Potential


Base controlled through capacitive divider

Non-ideality factor of channel control n > 1:

(n varies somewhat with bias const. approx. usually OK)


EECS240 Lecture 3 15

ID: Weak Inversion Current

Current set by diffusion borrow BJT equation:

EECS240

Lecture 3

16

ID: Operating in Weak Inversion


Usually considered slow:
large CGS for little current drive (see later)

But, weak (or moderate) inversion becoming more common:


Low power Submicron L means high speed even in weak inversion

Not well modeled, matching poor:


VTH mismatch amplified exponentially Avoid in mirrors
EECS240 Lecture 3 17

ID: Moderate Inversion

weak

Moderate inversion: both drift and diffusion contribute to the current. Closed form equations for this region dont really exist.
EECS240 Lecture 3 18

moderate inversion

strong

ID: Patching Models?


Have good models for weak inversion and strong inversion.
Why not just interpolate in between?

Example (EKV):

EECS240

Lecture 3

19

Output Resistance: CLM


Channel Length Modulation
Depletion region varies with VDS Changes effective channel length

If perturbation is small:

EECS240

Lecture 3

20

Output Resistance: DIBL


Drain Induced Barrier Lowering

Drain controls the channel too


Charge gets imaged lowers effective Vth Model with Vth = Vth0 - VDS
EECS240 Lecture 3 21

Output Resistance: SCBE


Substrate Current Body Effect At high electric fields, get hot electrons
Have enough energy to knock electrons off Si lattice (impact ionization)

Extra e- - h+ pairs extra (substrate) current


Models usually empirical

EECS240

Lecture 3

22

Output Resistance Mechanisms


All effects active simultaneously CLM at relatively low fields DIBL dominates for high fields SCBE at very high fields
Source: BSIM3v3 Manual

EECS240

Lecture 3

23

Comprehensive Model: BSIM


Berkeley Short-channel IGFET Model (BSIM)
Industry standard model for modern devices BSIM3v3 is model for this course

Typically 40-100+ parameters


Advanced software and expertise needed to perform extraction

EECS240

Lecture 3

24

BSIM Hand Calculation Model


Requires many, many, many assumptions Vertical mobility degradation:
Define:
ud = UA t ox

mobility degradation coefficient


u d 0 .5 V 1

for tox=10nm

Velocity saturation:
Define:
EC = 2v sat U0

critical E-field for velocity saturation


EC 2 10 4 V/cm

(typical value)
25

EECS240

Lecture 3

Strong Inversion Current


1 + ud (VG VT ) VDsat = (VG VT ) u + 1 (V V ) 1 + d Ec L G T
1 1 W VD =I = 0Cox VG VT VD Dlin( long ) 2 L VD VD 1 + ud (VG VT ) + 1 + ud (VG VT ) + E L E L C C

I Dlin

I Dsat

(VG VT )2 1 W = 0Cox = I Dsat (long ) 2 L 1 + u + 1 (V V ) (V V ) 1 + ud + 1 d G T G T EC L EC L

EECS240

Lecture 3

26

Equations of Derivatives
g msat I Dsat I Dsat I Dsat 1 = 1 + = 1 + (VG VT ) I Dsat(long ) (VG VT ) 1 + u + 1 (V V ) d EC L G T

rout = =

{(VD VDsat ) + [1 + ud (VG VT )](VG VT )}L I Dsat(long )lPCLM [1 + ud (VG VT )]

2{(VD VDsat ) + [1 + ud (VG VT )](VG VT )}L2 0CoxWlP [1 + ud (VG VT )](VG VT )2 CLM

with l = 3tox x j
Required parameters

W, L, TOX, U0, UA, VSAT, VTH0, PCLM, XJ

EECS240

Lecture 3

27

Fitting Results
Comparison between full and simplified model
6.00 5.00 4.00 3.00 2.00 2.00 1.00 VD=0.1V 0.00 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0 0.00 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2.0 1.00 VG=1.0V Full BSIM3 Hand calculation 7.00 6.00 VG=2.0V 5.00 Full BSIM3 Hand calculation

ID (mA)

ID (mA)

VD=1.8V

4.00 3.00

VG (V)

VD (V)

Parameter detail:

TSMC 0.18um process tox: 4.1nm, W=10mm, VT0=0.39V

EECS240

Lecture 3

28

Weakness of Model First Derivatives


6.00 Full BSIM3 5.00 Hand calculation 7.00 6.00 5.00 Full BSIM3 Hand calculation VG=2.0V

gm (mA/V)

4.00

Rout (kW)

VD=1.8V 3.00

linear region

4.00 VG=1.0V 3.00 2.00 linear region

2.00 VD=0.1V 1.00

1.00 0.00

0.00

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

VG (V)

VD (V)

EECS240

Lecture 3

29

Hand Model Conclusion


Even simple model is not convenient
ro is key for gain, but really hard to model Missing important regions such as moderate inversion

Hand models really best to build intuition But for design (i.e., how to choose W, L, etc.):
Will learn how to use the simulator as a calculator

EECS240

Lecture 3

30

Anda mungkin juga menyukai