Sanjay Banerjee
University of Texas at Austin
1
ITRS, 2003
2
3
Streetman and Banerjee, Solid State Electronic Devices, Prentice Hall
For LONG channel
W 1
ID = µ C 0 X (V G − V T ) V D − V D 2
L 2
W 1
I DSAT = µ C0 X (VG − VT )VDSAT − VDSAT 2
L 2
where[VDSAT = (VG − VT )]
W 1
I DSAT = µ C0 X VDSAT 2
L 2
For SHORT channel,
102 Metastable
101
100 0 20 40 7 60
Ge Conc. (%)
“Effective mass” !2
m =
*
d 2E
2
dk
eτ
3
µ=
m
* m*
g c (E ) = 4π (E − Ec )2
2 1
de
2
h −1
1 1 1
( )
1
m =
*
m1* m2* m3* 3 m = 3 * + * + *
*
m1 m2 m3
Bandstructure effective mass, m*, is inversely related to curvature of bands, and
depends on crystal orientation.
Density of states m* is related to geometric mean of bandstructure m*. Must
count number of “equivalent” valleys. 8
Conductivity m* is harmonic mean of bandstructure m*.
Si-based Strained Materials
CB
direction
direction
growth
growth
VB
Bulk Si CS-SiGe
E E
LH CB
k k
HH VB
LH HH TS-Si Relaxed
CS-SiGe TS-Si SiGe
9
Calculated Electron and Hole Mobility of Strained SiGe
Hole mobility with/without alloy scattering in plane and out-of-plane
Ge MOLE FRACTION
FM Bufler, P Graf, B Meinerzhagen, G Fischer, H Kibbel. Hole transport investigation in unstrained and 11
strained SiGe. J. Vac. Sci. Technol. B 16(3), pp. 1667-1669, 1998.
Ultra High Vacuum Chemical Vapor Deposition
14
Inversion Layer Mobility
Strained Si mobility
enhancement may be
due to reduced
surface roughness,
rather than
bandstructure
(Fischetti)
15
Strained Si NMOSFET Monte Carlo Simulations
1000
!MOSFET (Tox= 2 nm) K. K. Rim et. al., IEEE Trans. on Elec. Dev., 47 (7), pp. 1406, 2000
! MIT well-tempered device structure:http://www-mtl.mit.edu/Well/device50/topology50.html
!1-D Schrödinger equation for quantum correction
!As suggested by Fischetti et. al., J. Appl. Phys., 92 (12), 2002), surface roughness reduction may
play a role in mobility increase in strained-Si devices. 16
Current enhancement in Strained Si NMOSFET
7
S-Si, γ=0.2, reduced SR BSi 0.6 V SSi 0.6 V
3
Vg - VT = 2.0 V
500 BSi = Unstrained Si
Id ( µA/µm )
0 0
0.0 0.4 0.8 1.2 1.6 2.0 0.07 0.08 0.09 0.10 0.11 0.12 0.13
Vd (V) Channel Position (um)
17
Strained Si p-MOSFETs
ε-Si on Si0.7Ge0.3
ε-Si on Si0.65Ge0.35
1.5
Phys. 92, *Rim et al. IEDM
3745 (2002)
(1995).
1.4 Nayak et al. IEEE
Trans. on Elec.
1.3 Dev. 43, 1709
(1996)
1.2
2.5x10
12 12
5.0x10 7.5x10
12
1.0x10
13
**Rim et al.
Ninv per cm
2 Symposium on
VLSI
• µeff enhancement decreases with gate Technology
(2002)
overdrive* for holes
– No p-channel enhancement at Eeff = 1 MV/cm** for x = 0.28
– Physical mechanism poorly understood
Performance benefits of ε-Si primarily from n-MOSFET 18
Mobility enhancement in tensile and compressively strained Si
19
Mobility with Strain (Courtesy: Yu)
20
SiGe strain- and band-
engineered heterostructures
2DEG
Ec Ec
Increasing y
Ev Ev
Increasing x
Si1-yGey
Ev
ψholes
a⊥
aSi
∆6 ∆E c
∆4
Relaxed Strained
Si Si 1-x Ge x
HH
HH & LH
∆E v
Type-I (Compressive)
25
SiGe MOSFET Structure
Poly
Oxide Ec
SiGe
Energy
Si Substrate Ev
∆Ev
Depth
Carbon Concentration
• Carbon has a smaller lattice constant Carbide
– Strain compensation of SiGe (~8:1) Amorphous
– Tensile strained Si-C on Si
Islanded
Twinned
• Low solubility in Si Alloy
– Need low temperature growth to incorporate
C due to low solubility (5x1017 cm-3) Temperature
– Growth window for alloy growth
A. R. Powell, K. Eberl, B. A. Ek, and S. S. Iyer,
• Carbon ∆Ev=21-26meV/%C in SiGeC "Si1-x-yGexCy growth and properties of the
ternary system," Journal of Crystal Growth Vol.
(Lanzerotti, EDL,1996) 127, pp. 425, 1993.
– Ge ∆Ev=25 meV/3% Ge
Si Si1-yCy
• Carbon ∆Ec=75-90 meV/%C for SiC ∆(6) ∆4
CB
– (Faschinger, APL, 1995)
∆2
Bare Si
0% C, 40% G e
-3
-2.5 10 1% C, 40% G e V -V =-4V
G T
1.5% C, 40% Ge
-3
Red = after processing
-2 10
Blue = as grown
)
A( -3
Si0.795Ge0.2C0.005
-1.5 10
ID
-3
-1 10
-4
-5 10
V -V =-2V
G T
0
0 10 Si0.8Ge0.2
0 -1 -2 -3 -4 -5
V (V)
D
[001]
[010]
]
00
[1
32
Mobility in Relaxed SiGe
-4 0
Si
Vertical Si, relaxed and R e l. S iG e
S t r . S iG e
-3 0
strained Si1-xGeX PHFETs W /L = 1 2 0 µ m /7 0 n m V - V = -1 .5 V
showing enhancement of
I (mA)
GS T
T ox=4nm
-2 0
D
presence of strain. 0
0 V
• Bulk Ge has higher electron (2.5x) and hole (4x) mobility than Si, and can potentially
lead to faster MOSFETs and more balanced N vs. PMOSFETs.
• Germanium bulk substrates brittle, lower thermal conductivity (0.6W/cm-K vs. 1.5 for Si)
• Smaller Ge bandgap than Si broadens absorption spectrum; optoelectronic integration
on CMOS?
• Native oxide on Ge surface is not stable; GeO2 water soluble, GeO volatile at low T.
Deposited high-k gate dielectrics promising
• Performance much worse than expected, especially for NMOSFETs, probably because
of poor interface between Ge and high-k gate dielectric, as well as poor dopant
activation and interface between metal- source/drain
• Higher junction leakage in Ge, especially at high T 34
• Higher dielectric constant in Ge leads to worse electrostatics (DIBL, SS)
UHVCVD Ge-on-Si NMOS w/o SiGe buffer with PVD HfO2 and TaN gate
1 3
Ig(A)/cm2 High frequency (1MHz) and
calculated low frequency
2.5
0.1 L=10um, W=100um
Capacitance(uF/cm )
EOT=1.1nm
2
2
0.01
2
Ig(A)/cm
1.5
0.001 EOT=1.1nm
1
L=10um, W=100um
0.0001 0.5
0
0 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2
V (V)
V (V) G
G
10.0
8.0
Vg=0.1V
L=2um, W=5um Vg=0.6V
-5
10 6.0 Vg=1.1V
I (uA/um)
Vg=1.6V
Vg=2.1V
-7
10 4.0
S
SS=170mV/dec
I (A/um)
Vds=0.1V
-11 Vds=0.6V 0.0
10 Vds=1.1V 0 0.5 1 1.5 2 2.5
Vds=1.6V V (V)
Vds=2.1V DS
-13
10
-1 -0.5 0 0.5 1 1.5 2 2.5 3
35
V (V)
GS
Donnelly, .., Banerjee, SRC 2004
Effect of strain in Ge layer
Si0.5Ge0.5 % Compressive strain in Ge
1800 Si0.4Ge0.6 2 1.6 1.2 0.8 0.4 0
12
1600 Si0.3Ge0.7
Effective mobility (cm / Vs)
Experimental
1200 Si0.1Ge0.9
Ge 8
1000 Cz-Si
800 6
600
4 Experimental
400
Theoretical
200 2
0
2 4 6 8 10 12 14×10
12 0
2 0.5 0.6 0.7 0.8 0.9 1.0
Ninv per cm Ge fraction in virtual substrate
*Lee et al.
Appl. Phys. • Higher strain in the Ge layer favors high µeff* **M. V.
Fischetti
Lett. 79,
3344 (2001). – x ≤ 0.7 and S.
E. Laux,
Lee et al. in • reasonable agreement with theoretical calculations** J. Appl.
Mater. Res. Phys.
Soc. Symp. – x ≥ 0.8 80,
Proc., vol. (1996).
686, • rampant defect nucleation in Si cap, µeff depressed 36
A1.9.1(2002)
.
3-D Transistor Structures
top gate
100 nm
G
S D IBM ‘97
S G D Berkeley ‘99
G Lucent ‘99
37
Mark Bohr, ECS Meeting PV 2001-2, Spring, 2001
Strained-Si PMOSFET on SiGe-on-Insulator
p+ Relaxed p+
Si1-xGex Strained-Si (20 nm)
38
T. Mizuno et al., IEDM, 934-936 (1999)
SSOI with thin SiGe buffers w/o misfits
using BPSG compliant substrates
39
Rim, et. al. & Sturm et. al. (IEDM, 2003)
High mobility heterojunction transistor (HMHJT)
2.5
21
10
2 HJMOSFET HJMOSFET
-3
Si
1.5 Si 20
10 V =V =-2V
DS GS
E (eV)
V =V =-2V
1 DS GS
v
41
Subthreshold and Output Characteristics for HMHJT
-8
10
-3 Si control device
-7
HMHJT
-5
-6 V -V =0, -0.5, -1, -1.5, -2V
10 G T
-5
ID (mA)
Si control
ID (A)
10
-7 HMHJT -4
-3
-9
V = -0.1, -0.6, -1.1, -1.6 V
10 DS
-2
-1
-11
10
-3 -2.5 -2 -1.5 -1 -0.5 0 0
-2 -1.5 -1 -0.5 0
V (V)
GS V (V )
DS
42
Process Issues
44
Takagi, et. al, IEDM 2003
45
Device Metrics
• Speed
• τ = Cload VDD / Id
• Power
• P = f Cload VDD2
• Saturation current
• IDSAT = (W/2L) (krkoA) (TEOT,INV)-1 µ (VG-VT)2
• Consider VG ⇒ VDD
• Transconductance
• gm = (W/L) (krkoA) (TEOT,INV)-1 µ VDSAT
• Off-state power
• Subthreshold swing and source/drain junction leakage
46