MC74VHC02

Quad 2Input NOR Gate

The MC74VHC02 is an advanced high speed CMOS 2input NOR
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.

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MARKING
DIAGRAMS

Features

14

High Speed: tPD = 3.6 ns (Typ) at VCC = 5.0 V

Low Power Dissipation: ICC = 2 mA (Max) at TA = 25C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 40 FETs or 10 Equivalent Gates
PbFree Packages are Available*

A1
B1
A2
B2
A3
B3
A4
B4

3
5

10

9
11
12

13

Y2

Y3

14

A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W = Work Week
G or  = PbFree Package
(Note: Microdot may be in either location)

Y1

14

VCC

A1

13

Y4

B1

12

B4

Y2

11

A4

A2

10

Y3

B2

B3

GND

A3

FUNCTION TABLE
Inputs

*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.

November, 2005 Rev. 4

VHC
02
ALYW 


TSSOP14
DT SUFFIX
CASE 948G

Y4

Figure 1. LOGIC DIAGRAM

Semiconductor Components Industries, LLC, 2005

VHC02G
AWLYWW

PIN ASSIGNMENT
Y1

Y=A+B

SOIC14
D SUFFIX
CASE 751A

Output

L
L
H
H

L
H
L
H

H
L
L
L

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.

Publication Order Number:

MC74VHC02/D

MC74VHC02

MAXIMUM RATINGS
Symbol

Parameter

Value

Unit

VCC

DC Supply Voltage

0.5 to + 7.0

Vin

DC Input Voltage

0.5 to + 7.0

Vout

DC Output Voltage

0.5 to VCC + 0.5

IIK

Input Diode Current

20

mA

IOK

Output Diode Current

20

mA

Iout

DC Output Current, per Pin

25

mA

ICC

DC Supply Current, VCC and GND Pins

50

mA

PD

Power Dissipation in Still Air,

500
450

mW

Tstg

Storage Temperature

65 to + 150

C

SOIC Packages
TSSOP Package

This device contains protection

circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.

Maximum ratings are those values beyond which device damage can occur. Maximum ratings
applied to the device are individual stress limit values (not normal operating conditions) and are
not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Derating SOIC Packages: 7 mW/C from 65 to 125C
TSSOP Package: 6.1 mW/C from 65 to 125C

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min

Max

Unit

2.0

5.5

VCC

DC Supply Voltage

Vin

DC Input Voltage

5.5

Vout

DC Output Voltage

VCC

40

+ 85

C

0
0

100
20

ns/V

TA

Operating Temperature

tr, tf

Input Rise and Fall Time

VCC = 3.3V 0.3V

VCC =5.0V 0.5V

DC ELECTRICAL CHARACTERISTICS
Symbol

Parameter

Test Conditions

VCC
V

VIH

Minimum HighLevel Input

Voltage

2.0
3.0 to
5.5

VIL

Maximum LowLevel Input

Voltage

2.0
3.0 to
5.5

VOH

Minimum HighLevel Output

Voltage

Vin = VIH or VIL

IOH = 50mA

Vin = VIH or VIL

IOH = 4mA
IOH = 8mA

VOL

Maximum LowLevel Output

Voltage

Vin = VIH or VIL

IOL = 50mA

Vin = VIH or VIL

IOL = 4mA
IOL = 8mA

TA = 25C

Min

Typ

TA = 40 to 85C

Max

1.50
VCC x 0.7

Min

0.50
VCC x 0.3

2.0
3.0
4.5

1.9
2.9
4.4

3.0
4.5

2.58
3.94

2.0
3.0
4.5

Max

1.50
VCC x 0.7

2.0
3.0
4.5

Unit
V

0.50
VCC x 0.3

1.9
2.9
4.4

2.48
3.80

0.0
0.0
0.0

0.1
0.1
0.1

0.1
0.1
0.1

3.0
4.5

0.36
0.36

0.44
0.44

Iin

Maximum Input Leakage

Current

Vin = 5.5 V or GND

0 to 5.5

0.1

1.0

mA

ICC

Maximum Quiescent Supply

Current

Vin = VCC or GND

5.5

2.0

20.0

mA

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2

MC74VHC02

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

TA = 25C

Symbol
tPLH,
tPHL

Cin

Parameter

Test Conditions

Maximum Propagation Delay,

Input A or B to Output Y

Min

TA = 40 to 85C

Typ

Max

Min

Max

Unit
ns

VCC = 3.3 0.3V

CL = 15pF
CL = 50pF

5.6
8.1

7.9
11.4

1.0
1.0

9.5
13.0

VCC = 5.0 0.5V

CL = 15pF
CL = 50pF

3.6
5.1

5.5
7.5

1.0
1.0

6.5
8.5

10

Maximum Input Capacitance

10

pF

Typical @ 25C, VCC = 5.0V

15
CPD
Power Dissipation Capacitance (Note 1)
pF
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC / 4 (per gate). CPD is used to determine the
noload dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)

TA = 25C
Typ

Max

Unit

VOLP

Quiet Output Maximum Dynamic VOL

0.3

0.8

VOLV

Quiet Output Minimum Dynamic VOL

0.3

0.8

VIHD

Minimum High Level Dynamic Input Voltage

3.5

VILD

Maximum Low Level Dynamic Input Voltage

1.5

Symbol

Characteristic

TEST POINT
A or B

VCC

50%

OUTPUT
DEVICE
UNDER
TEST

GND
tPLH

tPHL

C L*

50% VCC

*Includes all probe and jig capacitance

Figure 2. Switching Waveforms

Figure 3. Test Circuit

INPUT

Figure 4. Input Equivalent Circuit

ORDERING INFORMATION
Package

Shipping

MC74VHC02DR2

SOIC14

2500 / Tape & Reel

MC74VHC02DR2G

SOIC14
(PbFree)

2500 / Tape & Reel

MC74VHC02DTR2

TSSOP14*

2500 / Tape & Reel

MC74VHC02DTR2G

TSSOP14*

2500 / Tape & Reel

Device

For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.

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3

MC74VHC02
PACKAGE DIMENSIONS
SOIC14
CASE 751A03
ISSUE G

A
14

P 7 PL
0.25 (0.010)

R X 45 

T
0.25 (0.010)

T B

DIM
A
B
C
D
F
G
J
K
M
P
R

D 14 PL

SEATING
PLANE

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.127
(0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.

MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50

INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
0
7
0.228 0.244
0.010 0.019

TSSOP14
DT SUFFIX
CASE 948G01
ISSUE A
14X K REF

0.10 (0.004)
0.15 (0.006) T U

T U

NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.

N
2X

14

L/2

0.25 (0.010)

M
B
U

L
PIN 1
IDENT.

F
7

0.15 (0.006) T U

DETAIL E
K

A
V

K1

J J1

SECTION NN
W

C
0.10 (0.004)
T SEATING
PLANE

DETAIL E

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4

DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M

MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50

1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0
8

INCHES
MIN MAX
0.193 0.200
0.169 0.177
0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0
8

MC74VHC02

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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including Typicals must be validated for each customer application by customers technical experts. SCILLC does not convey any license under its patent rights
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MC74VHC02/D