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Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010

Two Control Schemes to Enhance the Dynamic


Performance of the STATCOM and SSSC
Author 1: INDRANIL.SAAKI , Author 2: U.SALMA
Abstract - The paper presents an in-depth investigation of the dynamic performance of the Static Synchronous Compensator (STATCOM) and the Static Synchronous Series Compensator (SSSC) theoretically and by exact digital simulation. A 48-pulse GTO dc-ac converter model is designed to represent the operation of the STATCOM and SSSC within a power transmission system. Two major factors of the STATCOM instability are analyzed and a new Automatic Gain Controller (AGC) is proposed to ensure the stable operation of the STATCOM under various load conditions. It is shown that the Phase-Locked Loop (PLL) inherent delay has a great effect on the dynamic operation of the SSSC and a new auxiliary regulator is proposed to enhance the dynamic performance of the SSSC. The proposed control schemes are validated by digital simulation. Index Terms - Automatic gain controller, auxiliary regulator, dynamic performance, static synchronous series compensator (SSSC), static synchronous compensator (STATCOM), 48-pulse converter.
Presented at the international conference on power, control and embedded system (ICPCES) in Chennai, India on December 08-10, 2010.

Fig. 1. Static synchronous compensator.

I. STATIC SYNCHRONOUS COMPENSATOR


THE Static Synchronous Compensator (STATCOM) is a power electronic-based Synchronous Voltage Generator (SVG) that generates a three-phase voltage from a dc capacitor in synchronism with the transmission line voltage and is connected to it by a coupling transformer as shown in Fig. 1. By controlling the magnitude of the STATCOM voltage, the reactive power exchange between the STATCOM and the transmission line and hence the amount of shunt compensation can be controlled. The operation and control fundamentals of the STATCOM have been extensively discussed in [1][3]. The control system is based on a decoupled strategy or d-q transformation that makes it possible to control the reactive current flow between the STATCOM and the transmission system. II. A 48-PULSE CONVERTER AND THE BASIC CONTROL OF THE STATCOM There are various types of dc-ac converter topologies that can be employed in the STATCOM, such as two level, three level and PWM converters [1], [4]. Since two level, multipulse converters can be implemented easily and fulfill the STATCOM requirements, they are widely used in STATCOM applications.
INDRANIL.SAAKI is with the department of Electrical and Electronic Engineering, Gitam University, Visakhapatnam, India. (email ID : indranil.saaki@gmail.com) U.SALMA is with the department of Electrical and Electronic Engineering, Gitam University, Visakhapatnam, India. (email ID : salma@gitam.edu)

Fig. 2. Configuration of a 48-pulse converter. (2-24 pulse circuit) Besides they are the most economical type of dc-ac converters. For digital simulation purposes, a two level, 48pulse converter was modeled. Fig. 2 shows the configuration of a 48-pulse dc-ac converter, using eight 6-pulse GTO converters with four separate transformers. The details can be found in [1] and [5]. The phase displacement of two consecutive 6-pulse converters is 15 . Fig. 3 shows the digital simulation of a 48-pulse converter using Power System Blockset (PSB) of Simulink software. The Total

Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010


Harmonic Distortion (THD) of the generated voltage in Fig. 3 was measured by PSB as . Defining THD = 0.075 as full inductive operation of the STATCOM. I C max and I L max are the corresponding STATCOM current ratings. The Phase-Locked Loop (PLL) provides the basic synchronizing signal which is phase angle of the line voltage, . Line voltage, Vt , is compared with the reference voltage and a voltage regulator provides the required reactive current of the STATCOM by considering the regulation slope. The STATCOM reactive current, I q Ref is compared with this and a PI controller provides the required phase displacement .

V22 +V32 +...+Vn2 Vh THD = = V1 V1

Fig. 3. Digital simulation of the 48-pulse converter.

where Vi is rms of the i th harmonic, Vh is rms of total harmonic content and V1 is rms of the fundamental frequency component. Therefore total rms of the voltage is Vrms = V12 +Vh2 = V12 +(0.075V1 ) 2 Thus, V1 =0.997 Vrms that shows the voltage harmonic content is very small. This 48-pulse, GTO converter will be used for deigital simulation of the STATCOM. Unlike the PWM and three level converters, two level converters do not have internal capability of voltage control and only the phase angle of the output ac voltage can be controlled by gating signals. Therefore the only way to control the magnitude of the ac voltage is by the input dc voltage. The process of dc capacitor voltage control is achieved by a small phase displacement, between the STATCOM voltage, Vs , and the transmission line voltage, Vt If Vs lags Vt , real power flows from the transmission system to the dc capacitor (charge) and if Vs leads Vt , real power flows from the dc capacitor to the transmission line (discharge). Besides, a small is always required to compensate switching and coupling transformer losses by real power flow from the transmission line to the STATCOM. Fig. 4 shows the basic control structure of the STATCOM, based on a decoupled, d-q controlled strategy and the two level, 48-pulse converter. The regulation slope is defined as [1] VVL max VV k = C max = (3) I C max I L max where VC max is the maximum line voltage drop at full capacitive and VL max is the maximum line overvoltage at

Fig. 4. Basic control structure of the STATCOM

Fig. 5. Power system representation as seen by the STATCOM.

Fig. 6. Functional block diagram representation of the STATCOM.

III. DYNAMIC REPRESENTATION OF THE STATCOM Fig. 5 shows a simple per unit power system representation as seen by the STATCOM (including coupling transformer). Is the equivalent Thevenin reactance of the power system as seen by the STATCOM, Vcq is the

Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010


equivalent Thevenin voltage and is the STATCOM bus voltage. For the STATCOM capacitive operation we have Veq <0=Vt <0+( jI q )( jX eq ) Vt =Veq + I q X eq Fig. 6 shows the functional block diagram representation of the STATCOM when operating in capacitive mode [1]. The STATCOM can be modeled as a reactive current source with transportation lag, Td . The voltage regulator and the feedback voltage measurement are also modeled with transportation lags of T1 and T2 , respectively. The digital simulation results for voltage regulator output, I q Ref STATCOM voltage phase displacement , dc capacitor voltage Vdc and B2 bus voltage are shown in Fig. 8. The STATCOM is connected to bus B2 at t=0.1 Sec, while both loads are in the power system. It regulates the bus voltage to 0.97 pu. At t = 0.4 Sec, load 1 is rejected and only load 2 with high impedance remains. As shown in Fig. 8 the voltage regulator and therefore the dc capacitor and bus voltages exhibit strong oscillations. Although the STATCOM has a fast and stable response for the strong system, it exhibits oscillations for the weak power system. B. Effect of the PLL The PLL provides the basic synchronizing signal which is the phase angle of the bus voltage, . It is obtained from the zero crossing of the bus voltage. In the case of a

Fig. 7. Single-line diagram of the simulated power system. A. Effect of the Power System Strength on the STATCOM Stability As shown in Fig. 6, the system reactance, X eq , is a part of the feedback loop and it is crucial to note that X eq varies as loads are added to or rejected from the power system or when a transmission line or generator outage occurs. Therefore the overall closed loop gain and the stability margin of the STATCOM are greatly affected by X eq or system strength [1], [6]. If the impedance of the power system increases (weak system) the amount of voltage change due to the STATCOM reactive current increases and the overall system tends to instability. If the power system impedance decreases (strong system), the system is more stable, although the response is slower than that of the weak system. Therefore the power system strength greatly affects the response time and stability of the STATCOM. If the voltage regulator is set to provide a fast response for a strong system, it may lead to instability for a weak power system, while if the voltage regulator is set to provide a stable response for a weak power system, the response for a strong power system will be very slowand sluggish, as the overall system closed loop gain decreases. Digital Simulation: To demonstrate the effect of the power system strength on the STATCOM stability, an exact digital simulation, using the 48-pulse converter of Fig. 2, was performed by PSB/Simulink. Fig. 7 shows the single line diagram of the simulated power system with the STATCOM. The voltage regulator parameters are K p =0.004 and K i =3 and the regulation slope, k , is 48.3 V/A. The control structure of Fig. 4 was employed. Power system and STATCOM parameters are given in Appendix. ( MVAbase =100)

Fig. 8. Effect of the power system strength on the STATCOM stability, digital simulation.

Fig.9. Effect of the PLL delay on the STATCOM operation, digital simulation.

sudden change in the power system, such as load rejection, it takes about half a cycle of voltage (8.3 ms for Hz) for the PLL to be synchronized with the new voltage phase angle,

Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010


plus the signal processing delay. During this time the STATCOM operates at the previous phase angle, while the bus voltage phase has changed. Depending on the amount of phase angle change and whether it is increased or decreased, an uncontrolled real power, and therefore reactive power exchange would occur between the STATCOM and the transmission line during this inherent PLL delay. Digital Simulation: To demonstrate the effect of the PLL delay, the system of Fig. 7 with three loads different than that of the illustrated ones was simulated. Load 1 is an inductive load with P=1 pu and Q = 0.6 pu, load 2 is another inductive load with P = 1 pu and Q = 0.7 pu and load 3 is a capacitive load with P = 0.3 pu and Q = 0.35 pu. The simulation results for voltage regulator output, , dc capacitor voltage, Vde STATCOM reactive power, Qs and B2 bus voltage, VB 2 are shown in Fig. 9. The STATCOM is connected to the power show the actual dynamic process of the STATCOM step variations and to explain the effect of the PLL inherent delay. IV. AUTOMATIC GAIN CONTROLLER An Automatic Gain Controller (AGC)was designed to reduce the voltage regulator gain and therefore reduce the oscillations of the STATCOM in the case of a weak power system. The key is to detect the voltage regulator oscillations and reduce its gain until the STATCOM is stable again. A similar idea has been applied to stabilize the StaticVoltage Regulators (SVC) [6], but not yet to the new converter-based compensators. Thus the voltage regulator gain is set up to give a fast response for a strong system and in the case of a weak power system the AGC reduces its gain. The designed AGC is a variable gain that is comprised of three components: Oscillation Detector, PLL Oscillation Eliminator and Gain Reducer. Fig. 10 shows the STATCOM block diagram with the AGC. The Oscillation Detector detects any oscillations of the voltage regulator by

Fig. 10. STATCOM block diagram with the AGC.

system at t = 0.1 Sec with only load 1 in the system. At t = 0.5 Sec load 2 is switched in. The STATCOM is supposed to inject more reactive power, however due to PLL inherent delay, the STATCOM voltage leads the bus voltage for about half a cycle and the real power flows from the dc capacitor to the transmission line and Vde drops sharply. Therefore the STATCOM injected reactive power and hence B2 bus voltage drops sharply at first. At t = 1 Sec, load 3 is switched in and at t = 1.5 Sec loads 1 and 2 are rejected and only load 3 remains connected. When loads 1 and 2 are rejected, the STATCOM is supposed to operate in inductive mode (from capacitive to inductive mode), however due to PLL delay, the STATCOM voltage lags the bus voltage at first and the real power flows from the transmission line to the dc capacitor and it is charged. Thus the STATCOM injects more reactive power (capacitive) and the bus voltage jumps to higher level at t = 1.5 Sec. As the digital simulation shows, due to PLL delay, the STATCOM exhibits one or more strong oscillations when the loads are switched, specially when the STATCOM is operating at high current. Since the previous digital simulations have been performed based on Laplace domain functional model of the STATCOM, and not the actual GTO converter model, the effect of the PLL delay has not been demonstrated by digital simulation. Thanks to the exact modeling, it was possible to

Fig. 11. STATCOM with AGC, digital simulation.

computing the maximum and minimum of I q Ref in intervals of t .The difference between max I q and min I q Ref, I q Ref determines rate of the oscillations. A variable gain 0<k 1 is applied to the voltage regulator, based on I q Ref,. Since the voltage regulator input is the bus voltage error, delay time of the voltage measurement should be considered in selecting t . Besides, other delays such as voltage regulator and STATCOM delays should be considered. For the designed AGC, t was set to 40 ms to account for the above inherent delays. The PLL Oscillation Eliminator block eliminates the oscillation due to the PLL delay so that the AGC does not react to this oscillation. It ignores the first I q Ref, that is more than 1 A. Thus it is ensured that the AGC does not respond to the first PLL oscillation, as it is very large but of very short duration.

Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010


A variable gain 0<k 1 is generated by the Gain Reducer block and is applied to the voltage regulator. This variable gain is a function of and is smaller for larger and vice versa. A nonlinear function to meet the above requirements was selected as k= 10 VI q Re f +10 (6) V. STATIC SYNCHRONOUS SERIES COMPENSATOR The Static Synchronous Series Compensator (SSSC) is one of the most recent FACTS devices for power transmission line series compensation. It is a power electronic-based Synchronous Voltage Generator (SVG) that generates a three phase voltage, from a dc capacitor bank, in quadrature with the line current. Fig. 13 shows the basic diagram of the SSSC. The operation and control fundamentals of the SSSC can be found in [1], [2], [5]. The basic building block of the SSSC is a dc-ac converter which is connected in series with the transmission line by a coupling transformer. If the SSSC voltage, Vs , lags the line current, I L , by 90o , a capacitive series compensation is obtained and if leads I L by 90o , an inductive series compensation is obtained. By controlling the magnitude of Vs the amount of series compensation can be adjusted. the end of the simulation. As expected, the AGC does not affect the STATCOM when there is no oscillation in . Fig. 12 shows the variable gain, , applied to the voltage regulator. It is very small after load 1 rejection ( Sec) and gradually gets closer to unity as the oscillations become smaller.

A. Digital Simulation With the AGC In order to verify the performance of the AGC in stabilization of the STATCOM, the system of Fig. 7 with the same illustrated loads and same step changes was again simulated, while the STATCOM was equipped with the AGC. The STATCOM is connected to the power system at t=0.1 Sec while both loads are in the system and at t=0.4 Sec, load 1 is rejected. The simulation results for I q Ref , , Vdc and VB 2 are shown in Fig. 11, along with the results of the same system without the AGC, to validate the advantage of the AGC. Fig. 11(a) shows that the voltage regulator is stabilized after a few oscillations and as the result, the STATCOM dc capacitor and B2 bus voltages are stabilized, while the system without the AGC is still oscillating at

Fig. 14. Basic control structure of the SSSC.

A. Basic Control of the SSSC


Fig. 12. The AGC variable gain, digital simulation.

Fig. 13. Static synchronous series compensator.

As of the STATCOM, two-level, multipulse converters with practical and economical characteristics and low THD are widely used in SSSC applications. Therefore the same 48-pulse converter will be used to investigate the SSSC dynamic performance. The only way to control the magnitude of the converter ac voltage is by the input dc voltage. The dc capacitor voltage control is achieved by a small phase displacement, , beyond the required 90o , between Vs and I L . If Vs lags or leads I L by 90o plus , real power flows from the SSSC to the transmission line and the dc capacitor is discharged. Similarly, if lags or leads I L by 90o minus , real power flows from the transmission line to the SSSC and the dc capacitor is charged. Besides, a small amount of real power from the transmission line is required to compensate the converter switching and coupling transformer losses.

Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010


The main function of the SSSC is to control the real power flow. This can be achieved either by direct control of the line current or power, or alternatively by indirect control of the compensating reactance, X s , or series voltage, Vs [1]. Because of practical considerations, sometimes the reactance control may be preferred. The degree of series compensation, S , is usually expressed as the ratio of the series injected reactance, X s , to the transmission line reactance, X l . Therefore, S =( X s X l ) and the reference reactance is SX l which is negative for capacitive and positive for inductive compensation. Fig. 14 shows the basic control structure of the SSSC, with the series injected reactance, X s , as the reference value. The Phase-Locked Loop (PLL) system provides the basic synchronization signal, , which is the phase angle of the line current. X Ref is compared with X s and the error is passed to a PI controller that generates the required phase angle displacement, . The final output of the control system is the phase angle of the SSSC voltage. VI. DYNAMIC PERFORMANCE OF THE SSSC In order to investigate the operation of the PLL system and its effect on the dynamic performance of the SSSC, an exact digital simulation of the SSSC within a power transmission system, using the 48-pulse converter is presented. The digital simulation is accomplished by using the Power System Blockset (PSB) and Simulink software. transmission line. When load 2 is switched in, Vdc and therefore Qs are increased in order to provide the required . A. Investigation of the Phase-Locked Loop Performance The PLL system provides the basic synchronizing signal which is the phase angle of the line current. It is obtained from the zero crossing of the line current. In the case of a sudden change in the power system, such as switching of load 2 in the previous section, it takes about half a cycle of the line current (8.3 ms for f =60 Hz ) for the PLL to be synchronized with the new phase angle, plus the signal processing delay. This inherent PLL delay, causes some uncontrolled real power (and therefore reactive power) exchange between the SSSC and the transmission line. Therefore depending on the amount of the phase angle change and whether it is increased or decreased, the dc capacitor would be charged or discharged at load switching instants. As shown in Fig. 16, at t=0.3 Sec, has to increase, however it first drops and then increases with large overshoot. Similarly, at t=0.6 Sec, Vdc has to decrease, however it first increases and then drops very fast with large undershoot. The result of large and fast variations of Vdc at load switching instants is large and fast variations of the SSSC reactive power, Qs , and therefore in the series injected reactance, X s as shown in Fig. 16. Therefore the total series reactance of the transmission line would exhibit large variations which means oscillatory behavior of the line current, voltage, and power.

Fig. 15. Single-line diagram of the power transmission system.

Fig. 15 shows the single line digram of the power transmission system with the SSSC compensation. The power system and SSSC parameters are given in Appendix. The SSSC operates in capacitive mode with X Ref = -0.1 pu. The PI controller parameters are: K p =20 and K i =4 . The simulation results for the SSSC voltage phase, , dc capacitor voltage, Vdc , SSSC reactive power, Qs and series injected reactance, X s , are shown in Fig. 16. The SSSC is switched at t=0.1 Sec, while only load 1 is in the system. The measured before Sec is the reactance of the series coupling transformer which is a small positive value and after the SSSC is switched, it is the reference value which is -01 pu. At t=0.3 Sec load 2 is switched to bus B3 0.6 Sec. Since the SSSC operates in and is rejected at t capacitive mode, the phase angle of Vs is almost o . The 90 0.1 SSSC injects a capacitive reactance of pu in series with

Fig. 16. Dynamic performance of the SSSC, digital simulation.

VII. AUXILIARY CONTROL DESIGN An auxiliary regulator, using the dc capacitor voltage,was developed to enhance the dynamic performance of the SSSC. One critical aspect is to select the appropriate control signal. Since the process of losing the synchronization and rapid variations of the dc capacitor voltage occurs very fast, the SSSC series injected voltage, Vs , or reactive power, Qs , can not be selected as the calculation time is long. However, the dc capacitor voltage is

Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010


readily available and can be measured very fast. Besides, it is an exact indication of losing synchronization and rapid variations due to PLL delay. The key element is the rate of the variations of Vdc or ( Vdc /t). For a fixed interval of t, the variations of Vdc can be measured and a rapid change of Vdc occurs | Vdc |when is greater than a threshold, k . The values of t and k depend on the dc capacitor size and the SSSC parameters such as rating power. Besides, t and k are not independent, a smaller t requires a smaller k . A key factor is to detect the rapid variations very fast, as it happens in only a few mSec. Therefore t should be very small and about 1 ms. For this short duration, a Vdc of over 0.05 pu can be considered fast and is due to PLL delay. The exact values of t and k are a function of the SSSC parameters and may be obtained by some trial and error for the best results. After detecting the rapid variations of Vdc , the strategy is to correct the phase angle of the SSSC voltage, , with respect to the sign of the variations. If Vdc >0, the dc capacitor is charging very fast. This happens when Vs lags the line current, I L , by a small amount of less than 90 o for capacitive operation, or Vs leads I L by an amount of less than 90o for inductive operation. In these cases the real power flows from the transmission line to the dc capacitor. Thus if a small phase angle, , is added to the process of rapid increasing of Vdc can be made slower. Since sudden, large phase angle deviation, , would result in large real power exchange between the SSSC and the transmission line and this may cause unstable operation of the SSSC, should be a small value. By digital simulation and some trial operates only when | Vdc | >k and other than that a zero angle will be added to . Therefore it does not affect the normal operation of the SSSC and only in the case of the PLL delay, improves the dynamic performance of the SSSC. A. Digital Simulation In order to validate the new auxiliary regulator, an exact digital simulationwas performed, using the system in Fig. 15, while the SSSC is equipped with the new auxiliary regulator. Vdc is measured in every 0.8 ms ( t=0.8ms) and the threshold k , is 0.1 pu, i.e., the output of the Rate Detector is nonzero when | Vdc |>0.1 pu. The constant phase angle, , is 2.3o . The simulation results for Vdc , Qs and X s are shown in Fig. 18 along with the simulation results without the auxiliary regulator. The thick line shows the results with and the thin line shows the results without the auxiliary regulator. While the new regulator does not affect the SSSC in normal operation, the results are different at switching instants, t=0.3 Sec and t=0.6 Sec. It can be verified that Vdc exhibits smaller and slower variations when load 2 is added or rejected. Therefore the SSSC reactive power, Qs , and series injected reactance, X s , have much smaller and slower variations that yield to more stable power system. Figs. 19 and 20 show the simulation results at switching instants, t=0.3 Sec and t=0.6 Sec. The thick line is with and the thin line is without the auxiliary regulator. They clearly show the effect of the new regulator on the SSSC dynamics in more details.

Fig. 17. Block diagram of the auxiliary regulator for the SSSC.

and error it was found that the SSSC would be unstable for > 2.5o and for < 1o it has little effect on the SSSC k performance. Similarly if Vdc < <0 , the dc capacitor is discharging very fast and it shows that Vs lags I L by an amount of more than 90 o for capacitive operation, or leads by more than 90o for inductive operation. Thus the real power flows from the dc capacitor to the transmission line. In this case, if a small negative phase angle, - , is added to , the process of rapid dc capacitor discharging can become slower. Fig. 17 shows the block diagram of the auxiliary regulator for the SSSC dynamic enhancement. Vdc is measured in intervals of t and if | Vdc | >k the output of the Rate Detector becomes nonzero. Depending on the sign of Vdc a positive or negative constant phase angle, , is selected. The final sign of , is determined by the operating mode of the SSSC. The auxiliary regulator

Fig. 18. Dynamic performance of the SSSC with and without the auxiliary regulator, digital simulation

Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010


APPENDIX The system parameters of Fig. 7 are: ( MVAbase =100) Grid: Rated Voltage: 230 kV Short Circuit Capacity: 3000 MVA Reactance, : 0.3 pu Resistance, : 0.1 pu. Transmission Line: Reactance, : 0.2 pu (230 KV, 300 MVA) Power Transformer:(Y/) Rated Voltage: kV 230/33kV Rated Power: 300 MVA Leakage Reactance: 0.01 p.u. STATCOM: Type of valves: GTO Number of pulses: 48 Nominal ac voltage: 25 kV Nominal dc voltage: 2 kV Rated power: 100 MVAR GTOs Forward Resistance: 1 m Capacitor Bank (dc): Total Capacitance: 10 mF Rated dc Voltage: 2 kV Coupling Transformer: (Y/Y) Rated Voltage:25/230 kV Rated Power: 100 MVA Resistance: 0.001 pu Leakage Reactance: 0.08 pu. The system parameters of Fig. 15 are: ( MVAbase =100)

Fig. 19. SSSC performance with and without the auxiliary regulator (load switched in)

Fig. 20. SSSC performance with and without the auxiliary regulator (load switched out)

VIII. CONCLUSION Dynamic performance of the STATCOM and SSSC under various loads was investigated and two control schemes were proposed to enhance their operation. TheAGC is a powerful tool to ensure stable operation of the STATCOMas the power system conditions may change at any time. While the AGC ensures the stability of the STATCOM, it does not affect its normal operation. However, the AGC does not guarantee the optimum gain to obtain the fastest response of the STATCOM for a weak power system. The optimum gain is a function of the power system strength which varies as the loads are switched in or out of the power system or due to generator and transmission line outages. The auxiliary regulator, using the dc capacitor voltage, is an effective tool to improve the dynamic performance of the SSSC. Since it is based on the dc capacitor voltage, it can be easily implemented at the SSSC location and proves to be quite effective in reducing the transient variations of the power system, such as line current and bus voltage. However, the uncontrolled variations in dc capacitor voltage, as the main reason for the SSSC oscillatory operation, can not be fully eliminated. The main reason is the transmission line current transients at load switching instants which causes a quasi dynamic line current. This dynamics of the line current causes an uncontrolled real power exchange between the SSSC and the transmission system, even if they are exactly in phase. A

Transmission Line: Reactance, X l : 0.25 pu (230 kV, 300 MVA) Resistance, Rl : 0.05 pu. Power Transformer: (Y/) Rated Voltage: 230/33kV Rated Power: 300 MVA Leakage Reactance: 0.01 pu. SSSC: Type of Valves: GTO Number of Pulses: 48 Nominal ac Voltage: 6.6 kV Nominal dc Voltage: 1 kV Rated Power: 35 MVAR GTOs Forward Resistance: Capacitor Bank (dc): Total Capacitance: 10 mF Rated dc Voltage: 1 kV. Coupling Transformer: Rated Voltage: 6.6/36 kV Rated Power: 35 MVA Resistance: 0.001 p.u. Leakage Reactance: 0.02 p.u.
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Proceedings of the International Conference on Power,Control and Embedded Systems,Dec 8-10,2010


[1] [2] [3] [4] [5] [6] N. G. Hingorani and L. Gyugyi, Understanding FACTS, Concepts, and Technology of Flexible AC Transmission Systems. Piscataway, NJ: IEEE Press, 2000. L. Gyugyi, Dynamic compensation of ac transmission lines by solidstate synchronous voltage sources, IEEE Trans. Power Del., vol. 9, no. 2, pp. 904911, Apr. 1994. C. Schauder and H. Mehta, Vector analysis and control of advanced static var compensator, in Proc. Inst. Elect. Eng. Int. Conf. AC DC Transmission, 1991, pp. 299306. Paper no. 345. D.Soto and C. Green, A comparision of high-power converter topologies for the implementation of facts controllers, IEEE Trans. Indust. Electron., vol. 49, no. 5, pp. 10721080, Oct. 2002. K. K. Sen, SSSCstatic synchronous series compensator: Theory modeling and application, IEEE Trans. Power Del., vol. 13, no. 1, pp. 481486, Jan. 1998. R. M. Mathur and R. K. Varma, Thyristor-Based FACTS Controllers for Electrical Transmission Systems. Piscataway, NJ: IEEE Press, 2002.