VersaNode 210 Hardware Integration Application Note

Version 1.1 Date: October 12, 2010

08-00010-01

Proprietary & Confidential NIVIS LLC

Purpose and Audience

The purpose of this document is to provide all the necessary data to achieve hardware integration of the VN210 router within a data acquisition, sensor or communication interface board. This document is intended for hardware engineers who wish to incorporate the VN210 within a new hardware design. By definition the VN210 is a wireless modem that is pre-loaded with the Nivis ISA100.11a stack.

Pin-out and Interfaces

The following section presents the pin assignment of the VN210 and a brief description of the functionality associated with each pin. An external processing entity can communicate with the VN210 using either an UART interface (utilizing UART2) or an SPI interface. The UART1 port is dedicated to serial firmware download.

Figure 1. Pin Assignment of the VN210

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No. 1

Name UART2-CTS

Description UART2 Clear to Send

Type DIG

Dir I

Comments Standard UART communication with flow control. Connect this to UART-RTS of application processor. Standard UART communication with flow control. Connect this to UART-CTS of application processor. Standard UART communication with flow control. Connect this to UART-TXD of application processor. Standard UART communication with flow control. Connect this UART-RXD of application processor. Not Used Not Used Standard UART communication. Used for upgrading the firmware of the VN210. TTL<-> RS232 level shifters should be employed when connecting to RS232 port. Standard UART communication. Used for upgrading the firmware of the VN210. TTL<-> RS232 level shifters should be employed when connecting to RS232 port. Not Used Not Used READY signal used to wake up the application processor. Not Used Standard SPI Communication Standard SPI Communication Standard SPI Communication Standard SPI Communication Connect to Ground pin. Not Used Not Used Used for Wakeup & Status (Provisioning) button. Holding this pin low for 10 seconds causes the radio to return to the factory defaults state and scan for a provisioning device. Not Used

UART2-RTS

UART2 Request to Send

DIG

UART2-RXD

UART2 Receive Data

DIG

UART2-TXD

UART2 Transmit Data

DIG

5 6 7

UART1-RTS UART1-CTS UART1-RXD

UART1 Request to Send UART1 Clear to Send UART1 Receive Data

DIG DIG DIG

I O I

UART1-TXD

UART1 Transmit Data

DIG

9 10 11 12 13 14 15 16 17 18 19 20

I2C-SDA I2C-SCL TMR1 TMR0 SPI-SCK SPI-MOSI SPI-MISO SPI-SS GND KBI0 RTC-FOUT KBI6

I2C bus DATA I2C bus CLOCK Timer 1 I/O Timer 0 I/O SPI Clock SPI Data Out SPI Data In SPI Slave Select Ground RTC clock out enable / Keyboard interface pin 0 32768Hz RTC clock out Keyboard interface pin 6

DIG DIG DIG DIG DIG DIG DIG DIG N/A DIG DIG DIG

I/O I/O O I/O O O I O N/A O O I

21 22 23 24 25 26

KBI5 GND GND GND GND RTC-INT-B

Keyboard interface pin 5 Ground Ground Ground Ground RTC wake-up interrupt / Keyboard interface pin 7

DIG N/A N/A N/A N/A DIG

I/O N/A N/A N/A N/A O

Not Used

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No. 27

Name KBI1

Description Keyboard interface pin 1

Type DIG

Dir I

Comments Used as boot switch in order to boot different firmware images based on the position of the switch (future functionality). At present this pin should be held HIGH. Not Used Not Used WKU signal. Used by the application processor to wake up the VN210 processor. Not Used Not Used Not Used Reserved for future functionality. At present this pin should be held HIGH. Set ADC2-VREFH to Low and ADC2-VREFL to High and power the VN210 for a few seconds to erase the flash. After erasing the flash, set the ADC2-VREFH to High and ADC2-VREFL to Low. See the comments for ADC2-VREFH

28 29 30 31 32 33 34 35 36

KBI2 KBI3 KBI4 GND ADC3 ADC2 ADC1 ADC0 ADC2VREFH

Keyboard interface pin 2 Keyboard interface pin 3 Keyboard interface pin 4 Ground ADC pin 3 ADC pin 2 ADC pin 1 ADC pin 0 ADC2 reference, high pin

DIG DIG DIG N/A Analog Analog Analog Analog Analog

I/O I/O I N/A I I I I I

37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

ADC2VREFL GND VCC GND RESET JTAG-RTCK JTAG-TDO JTAG-TDI JTAG-TCK JTAG-TMS GND GND GND RF GND

ADC2 reference, low pin Ground Supply voltage Ground RESET pin JTAG Return Clock / ADC pin 7 JTAG Test Data Output JTAG Test Data Input JTAG Test Data Input JTAG Test Mode Select Ground Ground Ground RF pin Ground

Analog N/A N/A N/A DIG DIG DIG DIG DIG DIG N/A N/A N/A Analog N/A

I N/A N/A N/A I O O I I I N/A N/A N/A I/O N/A

Connect this pin to regulated power supply VCC. (+3V < Vcc <3.3V) Reset pin of the VN210. LOW to reset and HIGH to run. Standard JTAG interface Standard JTAG interface Standard JTAG interface Standard JTAG interface Standard JTAG interface

Not Used

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Serial and SPI Interfacing with VN210

The following figures indicate the correct UART and SPI pin connectivity between the VN210 and an external application processor.

(ExtRTS) EXTRTS 1 (ExtCTS) EXTCTS 2 (RX) UART2-RXD 3 (TX) UART2-TXD 4 VN210 (RDY) TMR1 11 (WKU) KBI4 30 GND

UART-RTS UART-CTS TX RX DAQ/Application Processor RDY_RADIO WKU_RADIO GND

Figure 2: Interfacing with the VN210 using UART based communication

(CLK) SPI-SCK 13 (MOSI) SPI-MOSI 14 (MISO) SPI-MISO 15 (SS) SPI-SS 16 VN210 (RDY) TMR1 11 (WKU) KBI4 30 GND

SCLK MOSI MISO SS DAQ/Application Processor RDY_RADIO WKU_RADIO GND

Figure 3: Interfacing with the VN210 using SPI based communication

Connect the RDY pin only if the full wakeup communication mode is desired (please consult the document entitled 08-00011-01_Nivis_ISA100.11a_FULL_API_Integration_Manual.pdf or 08-00014-01_Nivis_ISA100.11a_SIMPLE_ API Integration_Manual.pdf).

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Power Supply Considerations

Maximum Ratings
Parameter Supply Voltage Voltage on any digital I/O Min -0.3 -0.3 Typ 3.0 Vcc Max 3.3 Vcc + .02 Units V V Comment

Normal Operating Conditions

Parameter Supply voltage Voltage on analog pins Voltage supply noise Peak current Storage and operating temperature Operating relative humidity Transmit current Receive current
1) 2)

Min 2.7 0

Typ

Max 3.3 Vcc 200 60

Units V V mVpp mA C %RH mA mA A

Comments

50Hz 15MHz TX mode, maximum output power

-40 10

+85 90 60 21 15 27

Non condensing

Hibernate current

For additional information please consult the VersaNode 210 data sheet (document entitled 93-00002-01_Nivis_VersaNode_210_Datasheet)

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Layout Information and Mechanical Drawings

Figure 4: Recommended layout footprint. Primary dimensions are in inches. Dimensions in [mm] are in millimeters.

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Figure 5: Outline dimension drawing. Primary dimensions are in inches. Dimensions in [mm] are in millimeters.

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Figure 6: Detailed outline dimension drawing. Primary dimensions are in inches. Dimensions in [mm] are in millimeters

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