918 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO.

SING, VOL. 50, NO. 12, DECEMBER 2003

1.5-V MOS Translinear Loops With Improved

Dynamic Range and Their Applications to
Current-Mode Signal Processing
Carlos A. De La Cruz-Blas, Antonio López-Martín, and Alfonso Carlosena

Abstract—Novel MOS translinear loop topologies for very region of transistors, thus, making it an interesting alternative
low-voltage applications are presented. The inclusion of dc level for nonlinear and linear current–mode signal processing.
shifting, together with a novel biasing scheme based on two Unfortunately, most of the proposed TL loop implementations
MOS transistors in the triode region, allows the operation of the
loops at supply voltages as low as +2 sat maintaining
are not able to exploit the potential of the TL principle for very
low supply voltage [2], [3].
at the same time a large dynamic range. Several current-mode
translinear circuits, both static and dynamic, i.e., geometric mean, To overcome this restriction, we propose in this paper novel
squarer/divider, multiplier and square-root-domain filters, are TL loop topologies able to operate at supply voltages as low as
implemented following this approach, demonstrating on silicon
, and featuring at the same time a large dynamic
the proposed techniques.
range. They are based on a novel loop biasing technique, and
Index Terms—Companding, current-mode circuits, MOS the inclusion of dc level shifters. In the literature, level-shifting
translinear loops, very low-voltage.
techniques have been formerly employed to decrease the supply
voltage of current mirrors [4]–[6]; their versatility has been
I. INTRODUCTION demonstrated experimentally in many practical designs, al-
lowing the artificial reduction of the effective threshold voltage
A NALOG DESIGN is facing a continuous and profound
challenge to satisfy portable electronic equipment needs.
This fact and the down scaling in modern submicron CMOS
of the CMOS process [1]. This strategy was subsequently
extended and applied to more elaborated circuits. For instance,
in [7] and [8], an operational amplifier and a linear transcon-
fabrication processes are forcing to pay attention to low-voltage
ductor employing this technique are proposed, respectively.
analog circuits. Tighter low-voltage requirements confront
In this paper, level-shifting techniques are integrated as a part
designers with the search for new techniques, to revisit current
of TL loops design, in both stacked and up–down topologies,
methodologies and/or to find versatile and new ones at all
leading to a large dynamic range at low supply voltages in both
design levels; at device level, using transistors driven differently
structures. Moreover, a novel biasing scheme employing tran-
(using the bulk terminal) or operating in alternative regions
sistors in the triode region for up–down TL loops is provided,
(weak and moderate inversion); at system level, employing new
achieving these benefits to a larger extent. A complete family
structures and methodologies [1]. For instance, current–mode
of novel low-voltage static and dynamic current-mode circuits
processing exploits the signal-handling capability of currents,
based on the techniques proposed has been built in a 0.8- m
whereas voltages are nonlinearly related to circuit currents
CMOS process, including geometric mean, and squarer/di-
according to their inherent compression law , and
vider circuits, a multiplier/divider and first- and second-order
for MOS and bipolar junction transistors (BJTs), respectively.
square-root-domain filters. Measurement results are provided
These compressed voltages are simultaneously processed along
confirming the versatility of the proposed approach.
with their respective currents, but they play a secondary role in
The paper is organized as follows. In Section II, the TL prin-
the designs. In this way, the signal dynamic range becomes less
ciple is reviewed; Section III discusses the inclusion of floating
influenced by a reduction in supply voltage. Translinear (TL)
voltage sources in MOS TL loops in conjunction with a novel
loops constructed with MOS transistors operating in strong
biasing scheme for the up–down topology. Section IV describes
inversion and saturation fall into this category. The TL principle
the practical implementation of the level shifters. Second-order
is based on large-signal behavior, exploiting a wide operating
effects induced by the level shifters are investigated in Section V.
Simulation and measurement results demonstrating these ideas
Manuscript received March 25, 2003; revised July 11, 2003. This work
are offered in Section VI.
was funded in part by the Spanish Dirección General de Investigación under
Grant TIC2000–0615-C02–02 C. A., and in part by a Scholarship from
CONACyT/México under Contract 118658. This paper was recommended by
Associate Editor F. Duque-Carrillo. II. MOS TRANSLINEAR PRINCIPLE
The authors are with the Department of Electrical and Electronic Engi-
neering, Public University of Navarra, Campus Arrosadía, Pamplona E-31006 The term “translinear” was first introduced by Gilbert [9] in
Spain (e-mail: carlos.aristoteles@unavarra.es; antonio.lopez@unavarra.es;
carlosen@unavarra.es). 1975, emphasizing the fact that trans conductance ( ) is linear
Digital Object Identifier 10.1109/TCSII.2003.820230 with current, for the case of BJT transistor and MOS transistor
1057-7130/03$17.00 © 2003 IEEE
DE LA CRUZ-BLAS et al.: 1.5-V MOS TL LOOPS WITH IMPROVED DYNAMIC RANGE
in weak inversion. However, when transconductance is linear
with voltage instead of current like (1)
(1)
(where is a scaling factor), it leads to another class
of translinear circuits that can be implemented by the
quasi-quadratic law of the MOS transistor, i.e., solving (1) for
in terms of and subsequently integrating
(2)
being an arbitrary constant. This fact is considered as an ex-
tension of the translinear principle, known as MOS (or voltage)
translinear principle [2]. The quadratic expression (2) could be
achieved using MOS transistors in strong inversion and satura-
tion region, whose first order mathematical model is given by
(3)
where , , , , and are the gate–source voltage, MOS
transconductance parameter, threshold voltage, channel width,
and channel length, respectively. Comparing (2) and (3), we get
, and . one each other, since there is usually a tradeoff between them.
According to expression (3), the MOS translinear principle
was stated as follows: in a loop with an even number of gate-
source connections and with the same number of transistor ar-
ranged clockwise (CW) and counterclockwise (CCW), if it is
assumed that all the transistors operate in strong inversion and
saturation region then
(4)
Another interesting characteristic, arising from (4) is that the
resulting relationship between drain currents ideally does not
depend on temperature or process variations.
A limitation of this and other techniques based on the
MOS square law is that mobility reduction and velocity
saturation effects in modern deep submicron technologies
notably degrade the square law performance of small devices.
Such short-channel effects cause that the transconductance
parameter and the threshold voltage of (3) be no longer
constant, showing dependences on and [10]. To
mitigate such effects, larger than the minimum length of the
fabrication process is required in the transistors that build the
TL loops. This choice also reduces mismatching and channel
length modulation effects, but a decrement in bandwidth is also
observed. A paper that addresses other second-order effects in
MOS TL circuits is for instance [2].
Essentially, there are two practical translinear topologies for
the case of four transistors: stacked and up–down [2]. Fig. 1
depicts both possibilities where, for the moment, the voltage
sources will be assumed equal to zero.
The up–down topology is inherently better suited for low
supply voltages than the stacked one, due to the avoidance of
stacked gate-source connections [11], [12] that allows opera-
tion at , instead of of the stacked
counterpart, where is the minimum drain-source voltage
919
Fig. 1. TL loops with voltage sources.
to operate in saturation. In Section III, it will be shown how the
insertion of floating sources leads to a drastic reduction in the re-
quired voltage for the stacked case and increases dynamic range
for the up–down case thanks to a novel biasing scheme.
III. ADDING FLOATING SOURCES IN THE TL LOOP
In this section, the effects of including floating voltage
sources1 in MOS translinear loops are investigated. The main
goals are: 1) to find the appropriate floating voltage source
values to reduce the supply voltage and 2) to extend the dy-
namic range of the signals. These characteristics are related to
The inclusion of the voltage sources (see Fig. 1) modifies the
loop (4) as follows:
(5)
where all the transistors have been considered to have the same
ratio. Note that for each transistor a voltage source is
added at its gate, in order to preserve the symmetry, even though
the total effect can be modeled by only one source.
To achieve the same current relationship as in the conven-
tional TL circuits, it is necessary that (4) and (5) become iden-
tical, that is
(6)
Observe that no particular restrictions apply on , 2, 3,
4. Thus, could be either linear or nonlinear, time dependent
or not. The only condition is to satisfy (6). In addition, it will be
required that no current flows through the floating sources, in
order to facilitate the proper current injection into the loop tran-
sistors. With this in mind it is possible to determine the correct
values of to accomplish our objectives, i.e., preserving the
correct operation of the TL transistor loop at low supply volt-
ages.
As will be demonstrated later, the most evident benefit of em-
ploying the voltage sources in the stacked loop is the possibility
to achieve a correct functionality with supply voltages as low as
. For the up–down loop, a novel biasing tech-
nique will be presented allowing to decrease supply voltage to
the same value. Since practical implementation of the floating
voltage sources requires this supply voltage, they do not lead to
a further reduction. However, they increase the dynamic range
of the TL circuit for this supply voltage level.
1The terms floating source, voltage source, and level shifter will be used in-
terchangeably.
920 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12, DECEMBER 2003

Fig. 2. Stacked configuration, square root cell.

Fig. 4. Novel up–down geometric-mean circuit.

, since voltage at node is in this case. If , it

is possible to design these sources to reduce the supply voltage.
Fig. 3. Simplifying sources. The solution to achieve the sought objective is given by

In order to demonstrate the operation of TL loops including

the floating sources, a geometric-mean circuit will be analyzed. (9)
It will also serve as a basic cell for building other static and
dynamic TL circuits such as squarer/divider, multiplier, as well Observe that the condition keeps in the appro-
as first- and second-order square-root-domain filters. priate operating region, nevertheless, (6) imposes a restriction.
Therefore, has to be forced to to achieve a correct oper-
A. Geometric-Mean Circuit ation of the TL loop. Considering a ,
To simplify the analysis, the effects of will be studied on a voltages out of the range specified by (9) would make that at
specific case, the geometric-mean circuit; however, the general- least one transistor would operate in the triode or cutoff region
ization to other topologies employing the same loop is obvious, (when the upper or lower bound are surpassed, respectively).
as will be seen later. Choosing identical and equal , then the
The geometric-mean circuit is implemented in the stacked voltage at node will be and
configuration, when the from (5) (assuming that (6) is sat- the minimum supply becomes
isfied) are forced to fulfill the conditions below
(10)
(7)
At this point, it is necessary to explain that the possibility to
On other hand, the up–down loop has the following current reach the lowest bound depends strongly on the floating source
requirements: implementation. For instance, assuming that and
, then and . Thus,
(8) only a reduced voltage headroom (lees than ) is available to
design . As will be seen later, a resistor and current mirrors
In both cases, , being for the stacked are the basic elements to implement , demanding a
configuration, whereas for the up–down topology. for operating correctly. This fact will restrict the
supply voltage of the complete circuit.
B. Stacked Configuration
Fig. 2 shows the stacked configuration with the dc level C. Novel Up–Down Configuration
shifters and biasing circuitry included. – constitute the Fig. 4 shows a novel square root cell implemented with the
TL loop and – provide the required biasing currents to up–down translinear loop, where again the simplification of
satisfy (7). sources in Fig. 3 is used. As can be observed, the biasing circuit
Comparing the stacked configuration of Fig. 2 with the gen- is more complex than in the stacked topology [2].
eral scheme in Fig. 1(a), a simplification of the sources ac- Transistors – form the MOS TL loop and the re-
cording to the equivalence shown in Fig. 3 can be made, where maining transistors provide the correct injection of currents
’s have been assumed identical. into the loop in compliance with (8). As mentioned above, the
Assuming for the moment that , the minimum supply biasing circuitry of the up–down topology allows to decrease
voltage needed to properly bias the circuit is determined by the supply voltage to , instead of using the
the branch where flows; thus, this branch requires level shifter to this end at these voltage levels [12]. In this
DE LA CRUZ-BLAS et al.: 1.5-V MOS TL LOOPS WITH IMPROVED DYNAMIC RANGE
TABLE I
TRANSISTOR ASPECT RATIOS
sense, a novel alternative is proposed in Fig. 4, where and
are operating in triode region, adding their drain-source
voltages , for setting the proper bias voltage at the
drain of ( ). Transistors and
are arranged in a negative feedback configuration that sets the
required dc level at the loop transistor sources. When voltage
at any of the common gate nodes of the loop transistors tends
to decrease, the corresponding gate voltage of either or
tends to decrease, so that the equivalent resistance implemented
by this transistor in triode region tends to increase. This leads
to an increase in the voltage at the common source node of
and that compensates for the initial decrease.
This novel biasing scheme allows the avoidance of the
classical diode-connected MOSFET at the sources of and
[2], reducing the requirements from to . to obtain , but it is dependent on threshold voltages
Thus, the minimum supply level needed to achieve the square
root function is
(11)
demanding as condition for biasing the
TL transistor loop. This new proposal has advantages over that
offered in [12] in terms of silicon area and simplicity, while
keeping similar dynamic range and bandwidth. Table I shows
the aspect ratios of the MOS transistors in Fig. 4.
Once that the novel low-voltage biasing is employed in the
up–down TL loop, the floating voltage sources cannot further
reduce the voltage supply required since their physical imple-
mentation also requires a minimum voltage supply of
. However, level shifters can be exploited in this case
to extend the dynamic range. This is due to the fact that by the
inclusion of the level shifters, drain voltages of and
in Fig. 4 are Volts lower than the corresponding gate-voltage
of the TL circuit, so that larger drain-currents can be driven be-
fore they enter in their triode region. Nonetheless, the maximum
current that can be applied to the loop depends on this fact and
the level shifter implementation, i.e., the maximum current will
be reached when either enter in their triode region or
level shifters no longer operate correctly. In our TL design, the
second condition occurs first. The values for , leading to an
increment of the dynamic range, are expressed by
(12)
If (12) is not accomplished, two possibilities arise. For the upper
values of (12), at least one of the loop transistors will be forced
to enter in the triode region wrecking the MOS TL principle. On
the other hand, lower values of (12) will require larger supply
voltages for the MOS TL loop to operate correctly.
IV. PRACTICAL IMPLEMENTATION OF VOLTAGE SOURCES
The required characteristics for floating sources are: 1) value
bounded according to (9) and (12); 2) supply voltage compat-
921
Fig. 5. Voltage source implementation.
ible with the circuit; and 3) no current flowing out or into their
terminals.
According to previous works, floating sources can be imple-
mented in several ways: 1) MOS transistor in strong or weak
inversion [5]; 2) floating-gate MOS transistors [4]; 3) switched
floating capacitor [7], [8]; and 4) resistor with current sources
[8], [13]. Equation (12) imposes a voltage restriction that is dif-
ficult to achieve with solution 1) because the circuitry needed
usually requires higher supply voltages than .
Nevertheless, in [14] a weak inversion transistor is employed
and
technology, so that the operation of TL loop transistors in the
intended region is not guaranteed. Solution 2) is a good alterna-
tive, even though the gate initial charge on the practical design
needs to be removed. Solution 3) requires an extra clock signal,
which increments the complexity and the noise. Last, solution
4) depicted in Fig. 5, is the simplest and more straightforward
one to implement it, since only current mirrors and resistor
are required. The process tolerances for can be compensated
by tuning . The source value is given by
(13)
where the resistance terminals are high-impedance nodes
whose voltage is set by the nodes to which the floating source
is attached.
The voltage limitation of the proposed source is
for the upper bound, and for the
lower one, restricting this fact the lower supply voltage of both
translinear loops stacked and up–down to operate correctly.
V. SECOND-ORDER EFFECTS
The addition of the dc level shifters to the TL loops influ-
ences their bandwidth, power consumption and area. A careful
analysis is needed to minimize the impact of second-order ef-
fects and their influence in the TL loop operation. This Section
describes briefly some important issues and considerations to
reduce these influences.
A. Bandwidth
Level shifters incorporate extra poles and zeros to the TL
loop, and modify the total resistance and capacitance at the
nodes to which they are connected. To estimate their influence,
a small signal analysis was made. In such an analysis, transistor
(see Fig. 4) and floating source were considered. The
drain-gate connection of increases the parasitic capacitances
and the conductance of transistor . These effects can be ne-
glected if a proper aspect ratio of the transistors is selected.
922 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12, DECEMBER 2003

Thereby the poles and zeros generated by the inclusion of the

floating source have to be faraway from those created by the
transistors of the TL loop. In our design, the simulated small
signal bandwidth of the floating source alone was from 14.7
to 15.5 MHz depending on the tuning current , whereas the
bandwidth of the TL loop alone was approximately 2.5 MHz.
The bandwidth of both circuits (as in Fig. 4) remains practi-
cally 2.5 MHz. The latter data were obtained for a level shifter
with and transistor aspect ratios ,
employing BSIM3 models from a 0.8- m AMS process for the
simulation.
Fig. 6. Stacked: mismatch.
B. Power Consumption and Area
With regard to the power consumption, it is obviously incre- employ the fact that local mismatch of two close elements with
mented. Fig. 5 shows that is distributed to several branches. dimensions , is [15], being , the width
This implies a larger current consumption. For the particular and length of a MOS transistor or a resistor, as the case may be.
case of two floating sources, the static power is given by Thereby, the total variance of could be expressed as

(14)
where is the total current to implement the floating sources.
To provide an example for , where the first and second term are the contributions of the
and . This represents 23% more than a
geometric mean without floating sources for input currents of
10 , thereby, the increment of power consumption is notice-
able.
Area is also an important issue in circuit design. For the par-
ticular case of floating sources, low and values are required
for increasing bandwidth and not influencing substantially the
MOS TL loop behavior. The area of the floating sources was
8.1 , i.e, a 13% more than for a geometric-mean cir-
cuit without floating sources employing an AMS 0.8- m tech-
nology.
C. Mismatch
Another second-order effect is the mismatch of floating
sources. After the simplification of the sources (Fig. 3) the
up–down topology is free from second-order effects by the
introduction of the voltage sources. This is not the case for the
stacked topology where in spite of the simplification according
to Fig. 3, two voltage sources remain within the loop. In this
case, due to mismatch in the floating batteries, (5) is modified
as follows:
(15)
where is the error voltage caused by mismatching, consid-
ered constant. Rearranging (15) according to the current values
in (7), and solving for
(16)
Equation (16) shows that mismatched sources lead to addi-
tional nonlinear terms and sensitivity to temperature and fabri-
cation process through the parameter . The error is mainly
due to the mismatched resistor in the floating batteries and
mismatch in the bias current . To estimate , it is feasible to
(17)
resistor and mismatch, respectively. is a constant,
whereas depends on the effective voltage ( ) [16].
The parameters and fully depend on the fabrication
process. A realistic value of for a 0.8- process consid-
ering transistor aspect ratios of and resistors of
is 1.5 mV, a 0.2% of a nominal .
To provide realistic figures, some simulations were carried
out. Fig. 6 shows simulation results for a geometric mean
with a fixed input current A, a sweep for
from 5 to 20 A and different values of . Note that due to
the voltage mismatch the curves deviate according to (16). The
quadratic term in (16) can be neglected in this case due to the low
value of . Considering this analysis, the viability to develop
a geometric-mean cell on silicon using a stacked translinear con-
figuration with floating sources is demonstrated. Obviously, a
tradeoff in terms of area, power consumption and minimization
of second-order effects exists.
VI. SIMULATION AND MEASUREMENT RESULTS
In general, MOS TL loops constitute versatile building
blocks with a wide range of applications. Some examples
are vector sum, root-difference squares, RMS-dc converters
[17], [18], differential linear transconductor [19], nonlinear
transconductors to implement square-root-domain filters
(companding techniques) [20] etc. In this section, the results
obtained for the new TL loop geometric-mean circuit are dis-
cussed. Then, a squarer/divider cell is designed, demonstrating
that the methodology applied to the geometric-mean circuit
can be readily extended. Once both circuits are implemented,
they can be combined to build more complex circuits, such as
multipliers and square-root-domain filters, which are described
at the end of this Section.
Simulation (BSIM3 models) and measurement results have
been obtained using a 0.8- m DPDM n-well CMOS technology,
with a single supply voltage as low as 1.5 V. Only circuits based
on the novel up–down TL loops were fabricated, due to their
DE LA CRUZ-BLAS et al.: 1.5-V MOS TL LOOPS WITH IMPROVED DYNAMIC RANGE
Fig. 7. Stacked simulation results.
Fig. 8. Up–down measurement results.
superior performance. However, simulation results are also pro-
vided for the stacked loop.
A. Geometric Mean
1) Stacked Topology: The stacked topology was simulated
first at supply voltages of 1.5 V, which would be impossible to
achieve without the insertion of floating sources. Simulations
were performed with V and a nominal resistance of
. of the circuit achieved by
Fig. 7 shows different plots over a range of , where it is
interesting to note the good behavior for values larger than
2.5 . For this supply voltage level, the stacked structure
drives some transistors in the ohmic region for very low
currents, leading to the errors observed in Fig. 7 near zero.
They are strongly reduced for higher supply voltages and lower
values of for the transistors that build the TL loop.
2) Up–Down Topology: As mentioned above, owing to the
novel biasing proposal, the up–down TL loop and level shifter
require in this case a minimum supply voltage of 1.5 V to op-
erate correctly. Therefore, level shifters were employed toward
a considerable extension of dynamic range, as can be confirmed
by the following measurement results.
Fig. 8 shows measurement results for with
, a sweep for from 0 to 25 . The dashed and dotted
line represent for ( ) and
, respectively. Note the increment around 26% for the input
current and the corresponding 9% for the output current ,
evidenving the beneficial influence of the floating sources.
923
Fig. 9. Squarer/divider: dc Characteristics.
Fig. 10. Microphotograph of a geometric mean and Squarer/Divider.
B. Squarer/Divider Cell
The geometric-mean cell discussed above in an isolated con-
figuration does not offer many design possibilities. To overcome
this drawback it is necessary to implement its dual function, a
squarer/divider, thus expanding their versatility and providing
flexibility to create more elaborated circuits and systems.
A squarer/divider is obtained by slightly modi-
fying the geometric mean of Fig. 4, by interchanging input and
output and adapting their input and output impedances [21].
Fig. 9 depicts the dc measurement results of the squarer/di-
vider, for , and different values
of , where is a control current (see Fig. 5) to establish the
value of the floating source . The dashed line ( )
demonstrates the improvement in accuracy and dynamic range
( ) although the price
to be paid by this superior performance is the increase in area
and power consumption.
The up–down geometric mean and squarer/divider were fab-
ricated in the mentioned 0.8 DPDM n-well CMOS process.
A microphotograph of the cells is shown in Fig. 10, being their
total area 0.15 . TL loop transistors are arranged in a
common–centroid topology. Table I shows the transistor aspect
ratios of both circuits.
C. Multiplier/Divider
A one quadrant multiplier/divider (see Fig. 11) is easily im-
plemented cascading a geometric mean and a squarer/divider
cell [21]. This can be mathematically demonstrated by (18).
(18)
Another multiplier/divider for instance in [22] and [23] can be
obtained employing another algebraic combinations through
924 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12, DECEMBER 2003
Fig. 11. One quadrant multiplier/divider: dc characteristics.
geometric mean and squarer/divider cells as primitives. The
multiplier/divider implementing (18) was fully designed and
tested in the laboratory providing good agreement with the
responses obtained in the simulation process.
Experimental results reflecting the static behavior of the one
quadrant multiplier are shown in Fig. 11, where is depicted
for A, A, A and from 0 (lower
line) to 6 A (upper line) in 1- A steps. Breadboard parasitics
avoid measuring correctly the 3-dB bandwidth. The simulated
one was approximately 2.5 MHz. This relatively poor value is
mainly due to the large length of the MOS loop transistors em-
ployed. Total harmonic distortion (THD) measurements were
also made employing an input sinusoid of 1 kHz with dc com-
ponent of 6 A, leading to a THD value lower than 2% for a gain
factor of approximately 1.7 and amplitude of the input signal as
large as 5 A. Obviously, when lower gains [see (18)] are
set, these distortion figures are notably improved.
D. Square-Root-Domain Filters
Now first- and second-order filters employing instantaneous
companding techniques will be presented making use of the
novel up–down TL loops proposed here as basic building
blocks. The companding paradigm entirely exploits the
nonlinear characteristics of the devices, firstly compressing
the input voltages, then properly processing, being finally
expanded at the output. Often, the intermediate step is achieved
through nonlinear processing and thus the coined name of:
”externally linear internally nonlinear systems” [24], being
companding techniques a subset of those. The nonlinear
blocks are implemented exploiting the dynamic translinear
principle and its implicit current mode operation, maximizing
the dynamic range available. Depending on the law employed
for compression, the system can be defined as log domain [25],
[26] or square-root domain [20] via bipolar (MOS in weak
inversion) or MOS transistors in strong inversion, respectively.
1) First-Order Square-Root-Domain Filter: Assume the
implementation of a current mode integrator expressed by the
following;
(19)
being , and the dot the dc gain, cutoff frequency
and time differentiation operator, respectively.
Fig. 12. Implementation of Cv
_ through up–down squarer/divider and
geometric-mean cells.
To design the square-root-domain filter, a mapping on (19)
is required. To this end, consider that the output current is
nonlinearly related to a certain voltage by
(20)
i.e the quadratic behavior of a MOS transistor operating in
strong inversion and saturation region (square-root domain).
It was demonstrated in [12] that substituting (20) in (19),
applying the chain rule ( ), scaling by a factor
(a linear capacitance) to translate the equations in the current
mode and solving for [27], (21) is obtained.
(21)
where the cutoff frequency and dc gain are related to and
by
(22)
Equation (21) represents the dynamic nonlinear large signal
behavior of the first-order square-root-domain filter [28]. In
spite of strong nonlinearities that are involved, the –
relationship remains linear, as can be confirmed by the exper-
imental results.
Equation (21) can be implemented by the novel up–down
TL loops proposed here. Thus, a MOS companding filter can
be designed employing two geometric-mean circuits and one
squarer/divider [28]. Firstly, a nonlinear circuit block that imple-
ments the RHS first term of (21) is made cascading a squarer/di-
vider and a geometric mean, where the denominator is injected
by the current of a MOS transistor (20), whose gate is connected
to . The second term is easily achieved by a geometric mean.
Fig. 12 shows the design strategy, where the blocks represent the
basic TL loops offered in the previous sections. In the fabricated
prototype the three cells were integrated, occupying a total area
of 0.22 . The aspect ratio of MOS transistor to obtain the
mapping (20) was . Circuit response was tested
on the filter with a single supply voltage and an
external capacitor . The simulated bandwidth (small
signal) of the cells to build the filter was 2.5 MHz, very similar
to that obtained in the multiplier/divider circuit.
Fig. 13 describes the frequency response of the first-order
square-root-domain filter for from 2 A to 8 A in
2 A steps. It can be appreciated the independent and nonlinear
DE LA CRUZ-BLAS et al.: 1.5-V MOS TL LOOPS WITH IMPROVED DYNAMIC RANGE 925

Fig. 13. Measurements of frequency response of the first-order Fig. 14. Second-order square-root-domain filter: Q-tuning measurements.
square-root-domain filter.
TABLE II
COMPARISON WITH FORMER BIQUAD FILTERS
tuning according to (22). The tuning range of the filter was mea-
sured, being from 2 to 10 kHz. Distortion measurements were
also carried out for a 1-kHz sine input current with dc level of 6
A and the amplitude from 0 to 6 A in 1 A steps. THD less
than 2% can be achieved for amplitudes up to 5 A.
2) Second-Oder Square-Root-Domain Filter: A step
forward leads to the implementation of a second-order
square-root-domain filter by extending the methodology Making use of the mapped state space, (24) and (25) can be
established in the previous section. However, to synthesize expressed in terms of and as follows:
more arbitrary square-root-domain filter or even any class of
companding system, more general methods are discussed in [3] (26)
and [29].
Consider the implementation of a current mode second-order (27)
low-pass filter expressed by the following:
In spite of the strongly nonlinear behavior of (26) and (27), the
input–output relationship remains linear, making a system ex-
(23)
ternally linear but internally nonlinear through a square-root law
for compressing the internal voltages. The representation in (26)
, and the dot being the dc gain, and time differentiation op- and (27) allows to express the parameters of the biquad in terms
erator, respectively. Now defining an auxiliary current of the current square-root ( ) by
(where is an arbitrary constant), (23) can be
decomposed in (24) and (25) (28)

Now that the state equations are in current mode, we can pro-
(24) ceed as for the first-order filter of the previous section to im-
plement (26) and (27). Thereby, three novel squarer/divider and
(25)
four geometric-mean cells as those in Figs. 8 and 9 are required
to build the complete second-order square-root-domain filter.
(24) is obtained substituting (25) in (23) and solving for . A prototype of the filter was fabricated occupying an area
This state variable representation was selected for obtaining a of 0.5 approximately and experimental results were ob-
physically realizable circuit [27]. tained. For instance, Fig. 14 shows the tuning for
In order to implement an instantaneous companding filter A and from 2 to 5 A in steps of 1 A. Obviously,
through the quadratic law of the MOS transistor, a mapped state some deviations (about 10%) respect to similuation results were
space is required. This mapping is achieved making appreciated due to the fabrication process tolerances. The THD
and , whose deriva- figures and the tuning of cutoff frequency were very similar to
tives can be expressed by and the first-order filter case.
, respectively. Voltages and represent the To provide more insight with the technique proposed here,
gate-source voltage of MOS transistor where voltage swings are a comparison was made with formerly reported biquad imple-
compressed by the square-root of and , respectively. mentations. Table II summarizes this comparison, where some
926 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 12, DECEMBER 2003
important parameters of the filters were considered. Filters [28]
and [3] employ the square-root-domain approach, whereas filter
[8] is a – design. are the aspect ratios of TL loop tran-
sistors. THD measurements were made at 1 kHz – 16
in this work, 10 kHz – 30 in [3], and 100 kHz, 0.8
in [8], respectively.
Note that thanks to the inclusion of dc level shifters and the
novel biasing scheme of the proposed up–down TL loops, a con-
siderable saving of supply voltage from in [28]
and in [3] to V can be appreciated,
preserving similar performance in our design with regard to the
former biquadratic square-root-domain filters. For the case of
the bandwidth, the filter in [28] offers a very large one. This
larger bandwidth may be due to the fact that the length of TL
loop transistors is smaller and the biasing current is also high
(200 A), whereas, in our case, the biasing current was 8 A.
As described in [28], the small value of the transistors leads
to a very small output impedance at the capacitor nodes. There-
fore, as mentioned in [28], strong deviations appear in (26) and
(27) causing distortion, and significantly degrading linearity and
filter performance.
With regard to the filter in [3], the novel-loop-biasing tech-
nique and the inclusion of level shifters lead to considerable im-
provements in terms of supply voltage, power consumption, and
silicon area, beyond the enhancement due to the more modern
fabrication process.
The comparison of [8] and our design is quite difficult due to
the different approaches. In fact, [8] offers an internally linear
voltage-mode circuit and in our design an internally nonlinear
current-mode processing. The bandwidth of the – is higher,
however, area and power consumption are similar.
VII. CONCLUSIONS
The level-shifting technique by means of floating sources in
MOS translinear loops for both stacked and up–down topolo-
gies was investigated. The main goals were a reduction of supply
voltage or improvement in the dynamic range. It has been shown
that for the stacked case, dramatic savings in supply voltage
can be achieved. For the up–down case, thanks to a novel bi-
asing scheme, the main benefit is reflected on an extended dy-
namic range. Both topologies are able to work at supply volt-
ages as low as . Second-order effects by the
mismatched sources, the impact over the bandwidth and the in-
crease in power consumption were analyzed, highlighting the
robustness of the up–down loop. Experimental results of static
cells based on the proposed up–down TL loop, such as geo-
metric mean, squarer/divider, multiplier/divider, and dynamic
systems like first and second-order square-root-domain filters
were offered providing more insight and validating the proposed
strategy. The topologies proposed constitute an interesting alter-
native for very low-voltage analog processing.
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Carlos A. De La Cruz Blas was born in Juchitan,
Oaxaca, México, in 1975. He received the M.Sc. de-
gree in electronic engineering from the Instituto Na-
cional de Astrofísica Óptica y Electrónica (INAOE),
Puebla, México, in 1999. He is currently working to-
ward the Ph.D. degree in low–voltage analog inte-
grated circuits at the Public University of Navarra,
Pamplona, Spain.
Alfonso Carlosena was born in Navarra, Spain, in
1962. He received the M.Sc. degree (Hons.) and
the Ph.D. degree in physics from the University
of Zaragoza, Zaragoza, Spain, in 1985 and 1989,
respectively.
From 1986 to 1992, he was an Assistant Professor
in the Department of Electrical Engineering and
Computer Science at the University of Zaragoza.
In October 1992, he joined the Public University of
Navarra, Pamplona, Spain, as an Associate Professor
and where he has also served as Head of the
Technology Transfer Office. In March 2000, he was promoted to Full Professor
at the Public University of Navarra. He has also been a Visiting Scholar with
the Swiss Federal Institute of Technology, Zurich, Germany and New Mexico
State University, Las Cruces. His current research interests include analog
circuits and signal processing, digital signal processing and instrumentation.
On these topics, he has published over 60 papers in international journals and
has a similar number of presentations at various conferences.

Antonio J. López-Martín was born in Pamplona,

Spain, in 1972. He received the M.Sc. and Ph.D.
degrees in electrical engineering from the Public
University of Navarra, Pamplona, Spain, in 1995
and 1999, respectively.
Currently, he is an Assistant Professor with the
Public University of Navarra. He was formerly
a Visiting Professor with the New Mexico State
University, Las Cruces, and an Invited Researcher
with the Swiss Federal Institute of Technology,
Zurich, Switzerland. His research interests include
low-voltage analog and mixed-mode integrated circuits, integrated sensor
interfaces, analog and digital signal processing and communication systems.
He has coauthored over 60 papers on these topics in international journals and
conferences.