System Components
Lothar Thiele
7-1
Contents of Course
1. Embedded Systems Introduction 2. Software Introduction 3. Real-Time Models 4. 4 Periodic/Aperiodic Tasks 5. Resource Sharing 6. Real-Time OS 12. Model Based Design 7. System Components 8. Communication 9. Low Power Design 10. Models
3.4
Hardware
Computer Engineering and Networks Laboratory
Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW
7-4
Implementation Alternatives
General-purpose processors
3.4.1
Application-specific instruction set processors (ASIPs) Microcontroller DSPs (digital signal processors)
Flexibility
3.4.3
Properties P ti
Good average performance for large application mix Hi h power consumption High ti
Swiss Federal Institute of Technology 7-6 Computer Engineering and Networks Laboratory
Pentium P4
Dual Core
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7-8
System Specialization
The main difference between general purpose highest volume microprocessors and embedded systems i l i d b dd d is specialization. Specialization should Speciali ation sho ld respect flexibility fle ibilit
application domain specific systems shall cover a class of applications some flexibility is required to account for late changes, debugging
coprocessors
buses
data paths
interfaces
logic cells
switch elements
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(de)compressor
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AX
AY AF
MX
MY MF
* +,MR
Different functionality of registers A AX AY AF MX MY MF MR Diff tf ti lit f i t An, AX, AY, AF,MX, MY, MF,
Swiss Federal Institute of Technology 7 - 13 Computer Engineering and Networks Laboratory
AX
AY AF
MX
MY MF
* +,+
MR
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t1
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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW
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Microcontroller
control-dominant applications
supports process scheduling and synchronization preemption (interrupt) (interrupt), context switch short latency times
low power consumption peripheral units often integrated suited for real-time applications
8051 core
SIECO51 (Siemens)
Swiss Federal
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complete system timers I2C-bus and par./ser. interfaces for communi communication A/D converter watchdog (SW activity timeout): safety on-chip memory interrupt controller p
A/DC 10 - bit PWM UART watchdog (T3) I2C parallel ports 1 through 5 p p g
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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW
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f2
B: buffer
3.4.3.1
Swiss Federal
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MAC - Instruktion
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3.4.3.3
VLIW: parallel operations (instructions) encoded in one long word (instruction packet), each instruction controlling one functional unit. E.g.:
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Cycle C l 1 2 3
Swiss Federal Institute of Technology
Instruction I t ti A B E C F D G
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CCIR601/656 YUV 4:2:2 38 MHz (19 Mpix/sec) Stereo digital audio I2S DC-100 kHz 2/4/6/8 ch. digital audio I2S DC-100 kHz I2C bus to b t camera, etc.
Video In
Huffman decoder Slice-at-a-time MPEG-1 & 2 CCIR60/656 YUV 4:2:2 80 MHz (40 Mpix/sec)
Audio In
Audio Out
I2C Interface
32K
V.34 V 34 or ISDN Front End Down & up scaling YUV RGB 50 Mpix/sec PCI (32 bits, 33 MHz)
TM - 1000
PCI Interface
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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW
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3.4.4
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FPGA - Classification
Granularity of logic units:
Gate, tables, memory, functional blocks (ALU, control, data path, processor)
Communication network:
Crossbar hierarchical mesh tree Crossbar, mesh,
Reconfiguration:
fixed at production time, once at design time, dynamic during run-time
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[ and source: Xilinx Inc.: Virtex-II Pro Platform FPGAs: Functional Description, Sept. 2002, //www.xilinx.com]
Swiss Federal Institute of Technology 7 - 33 Computer Engineering and Networks Laboratory
[ [ and source: Xilinx Inc.: Virtex-II Pro Platform FPGAs: Functional Description, Sept. 2002, //www.xilinx.com]
Swiss Federal Institute of Technology 7 - 34 Computer Engineering and Networks Laboratory
Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW
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Topics
System Specialization Application Specific Instruction Sets
Micro Controller Digital Signal Processors and VLIW
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