9 Design Flow

Figure 1.10 shows the sequence of steps to design an ASIC; we call this a design flow . The steps are listed below (numbered to correspond to the labels in Figure 1.10) with a brief description of the function of each step.

FIGURE 1.10 ASIC design flow.

1. Design entry. Enter the design into an ASIC design system,

2.

3. 4. 5. 6. 7.

either using a hardware description language ( HDL ) orschematic entry . Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a netlist a description of the logic cells and their connections. System partitioning. Divide a large system into ASIC-sized pieces. Prelayout simulation. Check to see if the design functions correctly. Floorplanning. Arrange the blocks of the netlist on the chip. Placement. Decide the locations of cells in a block. Routing. Make the connections between cells and blocks.

8. Extraction. Determine the resistance and capacitance of the

interconnect. 9. Postlayout simulation. Check to see the design still works with the added loads of the interconnect. Steps 14 are part of logical design , and steps 59 are part of physical design . There is some overlap. For example, system partitioning might be considered as either logical or physical design. To put it another way, when we are performing system partitioning we have to consider both logical and physical factors. Chapters 914 of this book is largely about logical design and Chapters 1517 largely about physical design.

9 Universal Logic : Mux to Logic gates conversion

Posted by Nityanand Dubey on January 7, 2010

We have seen the universal gates in out previous posts. The NAND and NOR are called the universal gates because they can create any of the logic gates. There is an another concept called Universal Logic, Universal logic can also be used to create any of the logic gates. MUX and Decoders are called Universal Logic In this post, we will see haw a 2:1 MUX can be used to create different logic gates. 1. Designing an Inverter using 2:1 MUX. To design an inverter using 2:1 mux, we have to use the input as the select line of the MUX and the zeroth select line would be tied with Logic 1 and First select line would be tired with Logic 0, Now when the select line (Input) goes to 1 the out put will be 0 ( inverted). Image : MUX to inverter -

2:1 mux as an inverter

2. Designing an AND Gate using 2:1 MUX. To design an AND using 2:1 mux, we need to tie the zeroth input to Logic 0 and the First input to the one of the input of the AND Gate. The other input of AND gate would be connected with the select line of the MUX. Now, the out put of the MUX would be 1 only if the both of the inputs are 1 otherwise it would be 0 for all conditions. Image : MUX to AND Gate -

2:1 MUX as an AND gate

3. Designing an OR Gate using 2:1 MUX.

To design an OR using 2:1 mux, we need to tie the First input to Logic 1 and the Zeroth input to the one of the input of the OR Gate. The other input of OR gate would be connected with the select line of the MUX. Now, the output of the MUX would be 1 when any oth the two inputs would be 1 otherwise it would be 0 for all conditions. Image : MUX to OR Gate -

2:1 MUX as an OR Gate

4. Designing an NOR Gate using 2:1 MUX. To design the NOR using 2:1 mux, we need to tie the Zeroth input of mux to one of the input of NOR and another input of MUX is tied to 0 . The another input of NOR gate would be applied to the select line of the MUX. Now, the output of the MUX would be AB = (A+B). which is as same as the output of NOR Gate. Image : MUX to NOR Gate -

2:1 mux as a NOR Gate

5. Designing an NAND Gate using 2:1 MUX. To design the NAND using 2:1 mux, we need to combine the AND Gate and inverter implementation 6. Designing an XOR Gate using 2:1 MUX. To design the XOR using 2:1 mux, we need to tie the Zeroth input of mux to one of the input of XOR and another input of MUX to the inverted of first input. The another input of XOR gate would be applied to the select line of the MUX. Now, the output of the MUX would be AB + AB which is as same as the output of XOR Gate. Image : MUX to XOR Gate -

2:1 Mux as a XOR gate

7. Designing an XNOR Gate using 2:1 MUX. To design the XNOR using 2:1 mux, we need to tie the First input of mux to one of the input of XOR and another input of MUX to the inverted of first input. The another input of XOR gate would be applied to the select line of the MUX. Now, the output of the MUX would be AB + AB which is as same as the output of XNOR Gate. Image : MUX to XNOR Gate -

2:1 mux as a XNOR Gate

ASIC's are usually classified into one of three categories: full-custom, semi-custom, and structured. Full-custom ASIC's are those that are entirely tailor-fitted to a particular application from the very start. Since its ultimate design and functionality is pre-specified by the user, it is manufactured with all the photolithographic layers of the device already fully defined, just like most off-the-shelf general purpose IC's. The use of predefined masks for manufacturing leaves no option for circuit modification during fabrication, except perhaps for some minor finetuning or calibration. This means that a full-custom ASIC can not be modified to suit different applications, and is generally produced as a single, specific product for a particular application only. Semi-custom ASIC's, on the other hand, can be partly customized to serve different functions within its general area of application. Unlike full-custom ASIC's, semi-custom ASIC's are designed to allow a certain degree of modification during the manufacturing process. A semicustom ASIC is manufactured with the masks for the diffused layers already fully defined, so the transistors and other active components of the circuit are already fixed for that semi-custom ASIC design. The customization of the final ASIC product to the intended application is done by varying the masks of the interconnection layers, e.g., the metallization layers. Structured or Platform ASIC's, which belong to a relatively new ASIC classification, are those which have been designed and produced from a tightly defined set of: 1) design methodologies; 2) intellectual properties (IP's); and 3) well-characterized silicon, aimed at shortening the design cycle and minimizing the development costs of the ASIC. A

platform ASIC is built from a group of 'platform slices', with a 'platform slice' being defined as a pre-manufactured device, system, or logic for that platform. Each slice used by the ASIC may be customized by varying its metal layers. The 're-use' of pre-manufactured and pre-characterized platform slices simply means that platform ASIC's are not built from scratch, thereby minimizing design cycle time and costs.