European Journal of Scientific Research ISSN 1450-216X Vol.60 No.4 (2011), pp. 482-487 EuroJournals Publishing, Inc.

. 2011 http://www.eurojournals.com/ejsr.htm

Low Power Adaptive Viterbi Decoder with Facsu

N. D. Bobby Asst. Professor, S.A. Engineering College, Chennai S. K. Srivatsa Professor, Electronics Engineering, Anna University K. Lal Kishore Director, R & D Cell, JNTUH University S. Raj Kumar PG Scholar, S.A. Engineering College, Chennai Abstract Viterbi decoding is an optimal algorithm for decoding convolutional code in maximal likelihood sense. Its main drawback is that the decoding complexity grows exponentially with the code length. So, it can be utilized only for relatively short codes. In order to minimize power consumption and minimize BER, experimental calculations indicate that the use of Adaptive Viterbi decoder leads to a reduction in decoder power consumption for 49% over a Viterbi decoder which consumes power of 55% with no loss of decode accuracy. In this paper, we present a novel low-power FACSU, which consumes lower power than a conventional Adaptive ACSU.

Keywords: VLSI, Viterbi Decoding, FPGA, Adaptive Viterbi Decoding.

I. Inroduction
A Viterbi decoder [1, 2] is an important target for power reduction in many low-power communication devices. It can account for more than one-third of power consumption during baseband processing in current generation cellular telephones [3]. As integrated circuits continue to become smaller and faster, the appeal of higher complexity Viterbi decoders for higher memory order convolutional codes increases. Higher memory order codes can achieve superior coding performance without requiring precious additional channel bandwidth. However, to counteract the exponential dependence of Viterbi decoder complexity on higher memory order in low-power designs, good power reduction methods that exploit variations in the communications system are needed. In order to overcome this problem, the adaptive Viterbi Decoder (AVD) [4] [11] has been developed. This Decoder reduces the average number of computations required per bit of decoded information while achieving comparable bit error rates (BER) versus Viterbi algorithm implementations. As is the case in many designs today, significant untapped power reduction potential lies in dynamically varying a AVD implementation according to real-time changes in system characteristics. Low-power AVD is a well-studied subject. Power reduction in AVDs has been achieved by either reducing the number of states (reduced-state sequence decoder) [3], the size of survivor memory [4], or the number of trellis paths (limited-search trellis) [5] at the expense of increased BER and/or reduced throughput. Other approaches include

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scarce state transition [6] where the most-likely path passes through the zero states most of the time allowing shorter survivor memories and efficient limited-search trellis decoding [7]. In this paper, we present energy-efficient architectures for the fast add-compare-select unit (FACSU), For 128 State rate convolutional code for constraint length k=8, Nmax=8, Threshold=17 and Truncation length =40

II. Adaptive Viterbi Decoder Architecture

A high-level view of the implemented adaptive Viterbi decoder architecture is shown in Figure 1.Most hardware implementations of the Viterbi algorithm [9] are split into three parts: the branch metric generators (BMG), add-compare-select (ACS) units, path metric storage and control, and the survivor memory unit .A BMG unit determines distances between received and expected symbols. The ACS unit determines path costs and identies lowest-cost paths. The survivor memory stores lowest cost bitsequence paths based on decisions made by the ACS units and the path metric array holds per-state path metrics. The ow of certain data path and the storage of results is determined by the control path.
Figure 1: Adaptive Viterbi decoder architecture

In the implemented decoder, the expected symbol value (BMselect) is used to select the appropriate branch metric from the BMG, as shown at the left in Figure 2. This branch metric value is combined with the path metric of its parent present state to form a new path metric, di. At each Trellis stage, the minimum-value surviving path metric among all path metrics for the preceding Trellis stage, dm, is computed. New path metrics are compared to the sum dm + T to identify path metrics with excessive cost. Comparators are then used to determine the life of each path based on the threshold, T.
Figure 2: ACS unit of adaptive Viterbi decoder

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If the threshold condition is not satised by path metric dm + T, the corresponding path is discarded. Once the paths that meet the threshold condition are determined, the lowest-cost Nmax paths are selected. Sorting circuitry is eliminated by allowing feedback adjustments to the parameter T for each received symbol. If the number of paths that survive the threshold is less than Nmax, no iteration is required. As show in Figure 4, for stages when the number of paths surviving the threshold condition is greater than Nmax, T is iteratively reduced by 2 for the current Trellis stage until the number of paths surviving the threshold condition is equal to or less than Nmax. The T value is reset to its original value prior to the Processing of the next Trellis stage. Appropriate values for T and Nmax were determined in previous work [8], so that T reduction is needed infrequently (for less than 5% of symbols). The output of the ACS units includes path valid signals which indicate which of the 2 * Nmax paths have survived pruning. Details regarding other decoder components can be found in [8].

III. Fast Add Compare Select Unit

The adder block and carry block combined with RCS block is Fast Add compare select unit. RCS Block reduces the critical path delay. It is partitioned into two blocks as LSB and MSB comparators. The branch metric is quantized to 4bit and path metric is quantized to eight bit respectively. The MSB block is the four bit comparator. It compares the MSB values of the two paths Ai (7:4) and Aj(7:4). Comparison is done bit by bit starting from eighth bit. If the eighth bit of both Ai and Aj are equal, then it starts comparing the seventh bit. Likewise bitwise comparison continues, If the bit value differs, the path which posses the lowest bit value will be selected. If the bitwise comparison is equal in MSB, then we consider comparing the 5 input bit of LSB. Inputs to LSB is generated by adding 4b of path metric to the 4b of branch metric which results in generating the carry bit.
Figure 3: Fast Add Compare Select Unit.

So the 5b input to LSB is generated and the bit wise comparison is done in the similar way as in MSB. While comparing all the bits are equal, the lowest bit value path is selected. The RCS decision is made based on 4bit MSB of path metrics Ai and Aj respectively. The correct decision depends upon 4bit LSBS of updated path metrics Ai(o:3) and Aj(0:3) as the propagated carries will make the 4bit MSB Ai(7:4) and Aj(7:4) equal. The wrong decisions will affect the decoder performance.

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IV. AVD with Fast Add Compare Select Unit

Figure 4: Adaptive viterbi decoder with FACSU.

The ACS unit is the most important part and is different from common viterbi decoder, and its structure is shown in detail in Fig4. Adaptive Viterbi decoder consists of three parts as shown in fig 4. When two input bits that represent the outputs of the encoder have been transmitted are received from the channel, the branch metric generator (BMG) calculate the Hamming distance between the received bits and the 2K possible expected values. This path will be sent to next module to calculate , and then select the surviving paths . After accepting the new branch metrics from BMG, the main task of the Add-Compare-Select (ACS)module is to update the path metric. In conventional add compare select unit while comparing the two path cost values, 4bit branch metric is added to eight bit path metric to generate the eight bit output with carry, and discard the paths that dont satisfy the two criterias for path retention.ie 1. Path is retained if path is less than dm+T 2. The total number of survivor path is limited. The operation needed is to find the minimum cost among all surviving paths in the previous trellis stage by updating the threshold value dm. From the information of surviving paths, we can use decoding method such as register-exchange or trace-back, to generate the output sequences. In Fast Add Compare Select unit when two paths are compared, first MSB of both path metrics are compared bitwise. If values of bit wise comparison differs low cost path is selected. If all the values of MSB are equal LSB of branch metric is added to path metric to generate the output with carry. The selection mux is used to select the low cost path. FACSU is better than conventional ACSU computation of low path cost is minimized there by consuming the power.

V. Implementation Analysis
Power consumption values for AVA decoers were implemented in XC3S50 were determined with the following equation: Power = ((0.02xf) + 0.09) x A x V. Where f is the design frequency, A is the percentage of used device flip flop, and the I/O multiplied by their switching activity of 30% was used with a supply voltage of 5v. The implementation is done for both Adaptive viterbi decoder conventional Add Compare Select Unit and

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Fast Add Compare Select Unit. In Table 1 we are comparing the both Conventional ACSU and FACSU. .Comparision report shows the number of CLB slices, LUT,power consumption, number of filpflop and latency utilized for both ACSU and FACSU. Here we have analysed the process in xilinx project navigator XC3S50PQ208 with the speed -5 for high performance industry standard and simulated in Modelsim 6.2 .

VI. Result Analysis

The simulation result for Fast Add Compare Select Unit is shown below in fig 5. The Power analysis was performed for both conventional and fast ACS Unit, as mentioned in the tale1. The comparison shows that implementing FASCU has reduced the computational resources, memory, noise tolerance and power consumption in Adaptive Viterbi Decoder.
Figure 5: Simulation Result of Fast Add Compare Select Unit.

Table 1:
S.NO 1. 2. 3. 4.

Comparison of Conventional and Fast ACS.

Analysis Slice FF I/P LUT Slices Power Adaptive Viterbi with Conventional ACS 8 40 21 56.05mw Adaptive Viterbi with Fast ACS 1 29 16 35.87mw

Conclusion
The power consumption is minimized by implementing Fast Add Compare Select Unit in Adaptive Viterbi Decoder. Our future work is to implement this architecture in digital data communication receivers to reduce the power consumption and to enhance the performance of the system,.

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References
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