Department of Electrical and Computer Engineering University of New Hampshire

ECE 583 Design with Programmable Logic Spring 2008

Midterm Exam I
Instructor: Dr. Kuan Zhou Date: February 26, 2008 Place:Kingsbury Hall S320 Time: 2:00 PM 3:00 PM Note: Work should be performed systematically and neatly. This exam is closed book, closed notes, closed neighbour(s). Allowable items include exam, pencils, straight edge, and calculator. Question #8 is for graduate students only. Best wishes. Question 1 2 3 4 5 6 Sum Please print in capitals: Points 10 10 20 30 30 20 100/20 Score

Last name:____________________________ First name:

1. (10) State an advantage and a disadvantage of using schematics (diagrams) to design a circuit compared to a hardware description language.

Schematics: easier to describe interconnections among different components. HDL: more appropriate to describe complicated logic relations among different components.

2. (10) a. (2 point) Synthesis_ is the process of transforming a behavioral description into a structural gate-level circuit. b. (2 point) Integer is an example of an unconstrained array. Sequential_______.

c. (2 points) All statements inside of a process are

d. (2 point) A top-level entity designed to test a VHDL model is called a _test bench_____.

list

e. (2 point) A process is triggered whenever a signal in its has an event on it.

sensitivity

3. (15pt) The following input transitions occur in the simulation of the VHDL architecture below. Show, on a simulation list that includes the outputs, all the transitions that will occur during the simulation.
ARCHITECTURE first OF exam1_4 IS BEGIN PROCESS (a, b) BEGIN IF a = '0' THEN x <= b after 5 ns; ELSE x <= 'Z' after 2 ns; END IF; END PROCESS; y <= a AND b; END ARCHITECTURE first; time 0 ns 10 ns 20 ns a 0 1 1 b 0 0 1

(Hint: y<= a AND b is equivalent to: Process (a, b) y<= a AND b; End PROCESS;

0ns

5ns

10ns 0

12ns

20ns 1

22ns

4. (20) Write VHDL code for the body of a 16-1 multiplexor built using five 4-1 multiplexors. Write a testbench for this 4-to-1 multiplexor. Assume you have available a "mux4to1" component with its interface and architecture: ENTITY mux4to1 IS PORT (w0, w1, w2, w3: IN STD_LOGIC; s: IN STD_LOGIC_VECTOR(1 DOWNTO 0); f: OUT STD_LOGIC); End Entity mux4to1;

ENTITY mux16to1 IS PORT (w: IN STD_LOGIC_VECTOR(0 to 15); s: IN STD_LOGIC_VECTOR(3 DOWNTO 0); f: OUT STD_LOGIC); End ENTITY mux16to1;

Solution:

ARCHITECTURE struct of mux16to1 IS COMPONENT mux4to1 IS PORT (w0, w1, w2, w3: IN STD_LOGIC; s: IN STD_LOGIC_VECTOR(1 DOWNTO 0); f: OUT STD_LOGIC); End COMPNENT mux4to1; signal m: STD_LOGIC_VECTOR(3 downto 0); begin mux1: mux4to1(struct) port map (w(0), w(1), w(2), w(3), s(3), s(2), m(0)); mux2:mux4to1(struct) port map(w(4),w(5),w(6),w(7),s(3),s(2),m(1)); mux3:mux4to1(struct) port map(w(8),w(9),w(10),w(11),s(3),s(2),m(2)); mux4:mux4to1(struct) port map(w(12),w(13),w(14),w(15),s(3),s(2),m(3)); mux5:mux4to1(struct) port map(m(0),m(1),m(2),m(3),s(1),s(0),f); END ARCHITECTURE struct;

Testbench:

ENTITY testbench IS END ENTITY testbench; ARCHITECTURE behave of testbench IS Signal w: STD_LOGIC_VECTOR(0 to 3); Signal s: STD_LOGIC_VECTOR (1 downto 0); Signal f: STD_LOGIC; Begin Mux1: entity work.mux4to1(behav) port map(w(0),w(1),w(2),w(3),s(1),s(0),f); Process IS W <= 0101; s<= 00 after 10ns, 01 after 10ns, 10 after 10ns, 11 after 10ns; wait; end process; END ARCHITECTURE behave;

5. (15pt) Draw a block diagram that corresponds to the following VHDL model. Be sure to label all inputs, outputs, internal signals, and component ports. LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY circuit IS PORT(init, run, slow_pace, fast_pace, speed_sel: IN std_logic; pump1, pump0, motorA, motorB: OUT std_logic); END Entity circuit; ARCHITECTURE exam1 OF circuit IS component counter_2bit is PORT (reset, en, clk : in std_logic; Q : out std_logic_vector(1 downto 0)); end component counter_2bit; component decode_2_to_4 is PORT (sel : in std_logic_vector(1 downto 0); D0, D1, D2, D3 : out std_logic); end component decode_2_to_4; signal clock : std_logic; signal S : std_logic_vector(1 downto 0); BEGIN cnt: counter_2bit port map (init, run, clock, S); dec: decode_2_to_4 port map (S, pump0, pump1, motorA, motorB); clock <= slow_pace when speed_sel = '0' else fast_pace; END ARCHITECTURE exam1;

Solution:
init reset run en clk Q
pump0 pump1 motorA motorB

D0

sel

D1 D2 D3

speed_sel 0
slow_pac e

1
fast_ pa ce

6. (15 points) Draw a state diagram corresponding to the VHDL program shown below. entity foo is port (b, clk: in STD_LOGIC; u, v: out STD_LOGIC); end foo; architecture bar of foo is signal state: state_type; begin
process(clk) begin

if clkevent and clk = '1' then if state = baseball and b = '1' then state <= birdie; elsif state = puck and b = '0' then state <= baseball; elsif state = puck and b = '1' then state <= birdie; elsif state = birdie and b = '0' then state <= baseball; elsif state = birdie and b = '1' then state <= puck; end if; end if; end process; u <= '1' when state = baseball or state = puck else '0'; v <= '1' when state = birdie else '0'; end architecture bar;