ASYNCHRONOUS SEQUENTIAL CIRCUITS-DESIGN

DR T WALINGO LECTURE 7

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DESIGN PROCEDURE
STEPS Obtain a primitive flow table from the given specification. Reduce the flow table by merging rows in the primitive flow table. (STATE REDUCTION) Assign binary states variables to each row of the reduced flow table to obtain the transition table. (STATE ASSIGNMENT) Assign output values to the dashes associated with the unstable states to obtain the output maps. Simplify the Boolean functions of the excitation and output variables and draw the logic diagram. SUMMARY OF STEPS A. From the specification obtain the primitive table. B. From the primitive table obtain the transition and output table. C. Implement your circuit.
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EXAMPLE 1 : GATED LATC DESIGN

QUESTION Design a gated latch circuit with two inputs, G (gate) and D (data), and one output Q. The gated latch is a memory element that accepts the value of D when G = 1 and retains this value after G goes to 0. Once G = 0, a change in D does not change the value of the output Q.

UNDERSTANDING QUESTION
Principle of operation - Input D, Gate G D goes through when G is High In memory when G is low

Step 1: Primitive Flow Table A primitive flow table is a flow table with only one stable total state in each row. The total state consists of the internal state combined with the input. To derive the primitive flow table, first a table with all possible total states in the system is needed. Identify and circle the stable states and add the information (other states) to retain memory. Note that the one input changes at a time DG= 01 to 10 & 11 to 00 not allowed There are other ways but will be discussed with other examples

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EXAMPLE 1 - STEP 1: PRIMITIVE FLOW TABLE INFORMATION

All combinations are required All input combinations are 01, 11, 00, 10. For this the output Q can be 0 or 1. Note that a double input change is not allowedFundamental mode. Primitive table has one row for a stable state. Step A: Create a table with all possible combinations. Step B: Mark the possible stable states diagonals DG can be 00 and Q=0 DG can be 00 and Q=1 Step C: Mark the impossible states- in blue. DG cannot be 11 and the output is zero DG cannot be 01 and the output is 1 Remove the impossible states. Step D: Label, circle and insert outputs to the stable states.
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DG 00 a,0 b,0 c,0 d,1 e,1 f,1 01 11 10

Q 0 0 0 1 1 1

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EXAMPLE 1 - STEP 1 PRIMITIVE FLOW TABLE INFORMATION

Step E: Determine the un allowed states of a row and mark with don't cares -,- or x,x. States where two inputs changes from stable state. Marked in yellow. Step F: Determine the unstable states and fill them in the table. Reasonable unstable states should be chosen following the principles of operation of the design. Preferably in the same column. The output may be considered in the choice in case of multiple states in the column. When x changes from 00 to 01 a reasonable change is from a to b. Mark the outputs of the unstable states as don't cares. Marked in white. Note: Red represents circled stable state.
5 DG 00 a,0 a,x a,x 01 b,x b,0 x,x 11 x,x e,0 e,x 10 c,x x,x c,0 0 0 0 Q

d,1
x,x d,x

b,x
b,x x,x

x,x
e,1 e,x DG

f,x
f,x f,1

1
1 1

a b c d e f

00 a,0 a,x a,x d,1 x,x d,x 00

01 b,x b,0 x,x b,x b,x x,x 01 b,x b,0 x,x b,x b,x x,x

11 x,x e,x e,x x,x e,1 e,x 11 x,x e,x e,x x,x e,1 e,x

10 c,x x,x c,0 f,x f,x f,1 10 c,x x,x c,0 f,x f,x f,1

a b c d e f

a,0 a,x a,x d,1 x,x d,x

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EXAMPLE 1 - STEP 2: REDUCTION OF THE PRIMITIVE FLOW TABLE

Rules for merging two or more rows into one: Use the methods of row reduction or implication table on equivalent states (done before). Presence of non conflicting states and outputs in each of the columns. (two parts showing candidates for merging - no conflicting entries in each of the four columns) Whenever, one state symbol and dont care entries are encountered in the same column, the state is listed in the merged row. If the state is circled in one of the rows, it is also circled in the merged row. The output state is included with each stable state in the merged row. Note: Red represents circled stable state.
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DG

a
b c d e f

00 a,0 a,x a,x d,1 x,x d,x

01 b,x b,0 x,x b,x b,x x,x

11 x,x e,x e,x x,x e,1 e,x

10 c,x x,x c,0 f,x f,x f,1

00 abc def a,0 d,1

01 b,0 b,x

11 e,x e,1

10 c,0 f,1

00 a b a,0 b,1

01 a,0 a,x

11 b,x b,1

10 a,0 b,1

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EXAMPLE 1 - STEP 3: TRANSITION TABLE AND LOGIC DIAGRAM

State Assignment Assign a binary value to each state. This converts the flow table to a transition table. In assigning binary states, care must be taken to ensure that the circuit will be free of critical races. Set a=0, b=1 Excitation and output tables Simplify these tables and express as Boolean function Value of Y and output Q is as given. Use don't cares for further simplification give them a value that simplifies your circuit further. Use combinational logic diagram with feedback

Dont cares used to make output Q = Y

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EXAMPLE 1 STEP 3 - IMPLEMENTING WITH SR LATCH

The procedure is as before from the transition table. Given a transition table derive a pair of maps for Si and Ri. In filling the table determine from the excitation table the S and R values that will give the state transition for the combinations indicated in the transition table. Derive the simplified Boolean functions for each Si and Ri. From the map Draw the logic diagram for NAND latches, use the complemented values of those Si and Ri. Note the figure has used a NAND latch for a change.

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SUMMARY OF DESIGN PROCEDURE

Problem definition: state the design specifications. Interpretation: Obtain a primitive flow table from the given design specifications (most difficult). State reduction: reduce flow table by merging rows in primitive flow table (implication table, merger diagram as done before). Reduce equivalent states and compatible states. Done in earlier chapter. State assignment: assign binary state variables to each row of the reduced flow table to obtain the transition table Eliminates any possible critical races. Output assignment: assign suitable output values to the don't cares associated with the unstable states to obtain the output maps. Simplification: Simplify the Boolean functions of the excitation and output variables and draw the logic diagram. Can be implemented using normal gates. can be implemented using SR latches.
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IMPLICATION TABLES FULLY SPECIFIED STATES - REVISED

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IMPLICATION TABLES INCOMPLETELY SPECIFIED STATES - REVISED

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IMPLICATION TABLES INCOMPLETELY SPECIFIED STATES - REVISED

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IMPLICATION TABLES INCOMPLETELY SPECIFIED STATES - REVISED

in one group

no implied states

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RACE FREE STATE ASSIGNMENT

Race-free: avoiding critical races Only one variable changes at any given time. may allow noncritical race. Adjacent assignment Condition: binary values of states between which transitions occur only differ in one variable. tedious process: test and verify each possible transition between two stable states. m variables required for a flow table with n rows: 2m n No critical race for assigning a single variable to a flow table with two rows. Transition diagram: pictorial representation of all required transitions between rows Try to find only one binary variable changes during each state transition. If critical races exist, add extra rows to obtain race-free assignment.

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RACE FREE ASSIGNMENT 3 ROW EXAMPLE

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RACE FREE ASSIGNMENT -3 ROW EXAMPLE

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RACE FREE ASSIGNMENT 4 ROW EXAMPLE

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RACE FREE ASSIGNMENT 4 ROW EXAMPLE

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HAZARDS
In the design of asynchronous sequential circuit, the circuit must be operated in fundamental mode with only one input changing at any time, and must be free of critical races. Hazards: unwanted switching transients at the output because different paths exhibit different propagation delays. May cause the circuit to malfunction. in combinational circuits: may cause temporary falseoutput value. in asynchronous sequential circuits: may result in a transition to a wrong stable state. Need to check for possible hazards and determine whether causing improper operations.
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HAZARDS

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HAZARD TYPES

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HAZARDS

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HAZARDS
Draw final circuit

Hazard exists whenever 2 adjacent 1s in a K-map are not covered by a single product. To remove all static hazards, find a cover that includes each pair of adjacent 1s.
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HAZARDS - ELIMINATION

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ESSENTIAL HAZARDS
An essential hazard is the result of the effects of a single input variable change reaching one feedback path before another feedback path. Essential hazards cannot be corrected by adding redundant gates as in static hazards. They can always be eliminated in a realization by the insertion of sufficient delays in the feedback paths. Facility in doing this comes only with experience.

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...

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CLASS EXERCISE
1. Design a latch circuit with one input T and one output Q. The latch is a memory element that toggles the value of Q when T = 1 and retains this value after T goes to 0. 2. Design a negative edge triggered T FF.

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CLASS EXERCISE 1: DERIVE AND CONSTRUCT A `T' FLIP-FLOP

Step 1: Obtaining the state table

Principle of operation. Toggles when the input is 1 else keeps its state
T 0 _ _ _ _ 1 0 0 1 1 c,1 d,1 Q 0 a,0 b,0 T 1 0 0 1 1 Q 0 a,0 a,0 c,1 c,1 T 1 d,1 b,0 b,0 d,1 0 0 1 1 a b c d Q 0 a,0 a,x c,1 c,x T 1 d,x b,0 b,x d,1

Obtaining the primitive flow table. Determine all the possible states. For every input combination how many outputs would you have. Table 1 Name the primitive stable states. Table 2. Fill in the next temporary states observing the rules. Table 3 E.g. From (a,0) when input changes by 1, The circuit will toggle to an output of zero and hence the best next state is (d,0). Note that the operation is in the fundamental mode.

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Step2: State Reduction No further state reduction Step 3: State assignment T
a
00 T

01

0
00,0 00,x 11,1 11,x

1
10,x 01,0 01x 10,1

0 a b c a,0 a,x c,1

1 d,x b,0

00 00 11

b,x

10

11

c,x

d,1

10

No cross transitions hence straightforward race free assignment Step C: Implementation y1 y2 00 01 0 0 0 1 1 1 1 0 0 1 y1 y2 00 01 0 0 0 1 1 1 0 1 1 0 y1 y2 00 01 11 10 0 1

0
x 1 x

x
0 x 1

11
10

11
10

Y1 T y1 T y2
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Y2 T y1 Ty2
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Z y1

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Checking carefully we identify a hazards in the first and second term and adjust it. Our final equations are
Y1 T y1 T y2 y1 y2
Y2 T y1 Ty2 y1 y2

Z y1

Note: Student to implement the circuit using the NAND gates

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CLASS EXERCISE 2 -SOLUTION

Students to finish the design.

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