References
The following references are in the textbook, Introduction to Digital Logic Design, by John Hayes, Addison-Wesley, 1993. The relevant pages will be photocopied and distributed to each lab team by the TA during the week of April 1. 1. For discussions and examples of a ROM-based realization of a binary multiplier, see pages 7374 and pages 259-260. This method will be used in part MG6A of the project. 2. The design of a 2 2 binary multiplier is presented on pages 340-342 as an example of multiple-output combinational logic design using basic gates for the hardware. 3. A counter-based design for a general n n binary multiplier is shown as Example 8.8 on pages 660-664. It is a sequential machine composed of three counters and five-state one-hot
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controller, using SSI and MSI components. An alternative approach to the design of this counter-based multiplier, using algorithmic state machine (ASM) charts, is presented on pages 684-691. We will use a variation of this approach for parts MG6B and HD6 of this project. 4. The design of an 8 8 bit shift-and-add multiplier from an ASM chart is presented as Example 8.10 on pages 691-698. We may use this design as an example in class, with the hardware simplification discussed in Problem 8.69 on page 712.
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2. 3. 4. 5.
6. 7.
8.
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9. Use palette [DBG GATES] DELTAS to determine the delay time of the ROM. 10. Close QuickSim without saving. Study the simulated output waveforms and write a discussion of the results in your report, including the value of typical delay time found in Part 9.
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Product Count 10-Bit Up Counter 3 10 P 2-Bit Binary MSD 8-Bit BCD LSDs Multiplicand 4 N1 4-Bit Down Counter 1 Count Enable Load Clock Zero Clear Clear
Control _INC3 _CLR3 CLR3 ST _DCR1 FG _LD1 CLK _ZER1 RDY Count Enable _DCR2 _LD2 CLK _ZER2 Ready _RST Reset Start
Clock
4 CT1
4 CT2
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START ? Y
Clear the Product in Up-Counter 3 Load Multiplicand N1 into Down-Counter 1 Load Multiplier N2 into Down-Counter 2 State S1
Counter 2 = 0 ? N
Counter1 = 0 ?
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Read the cited text references to fully understand the logical behavior of this multiplier. The table below shows the IC components (in your hardware lab kit) that are available to implement this circuit. You should be familiar with these devices from experience in the previous experiments. Nine of these IC chips are dedicated to specific uses as indicated in the Description column. Although the four chips specified for use in HD6 will not appear in the MG6B simulation, they cannot be used for other purposes in MG6B. Since the IDL-800 breadboard will accommodate a maximum of 12 IC chips, your design is constrained to using not more than three additional chips from the items having no pre-assigned application in the table. IC 74LS00 74LS00 74LS02 74LS04 74LS08 74LS10 74LS20 74LS32 74LS74A 74LS76A 74LS76A 74LS86 74LS138 74LS153 74LS157 Description Quad 2-input NAND Quad 2-input NAND Quad 2-input NOR Hex Inverter Quad 2-input AND Triple 3-input NAND Dual 4-input NAND Quad 2-input OR Dual D Flip-Flop Dual JK Flip-Flop Dual JK Flip-Flop Quad 2-input XOR 1 of 8 Decoder Dual 4-input MUX Quad 2-input MUX 7-Segment Display controller in HD6 Multiplicand, down-counter 1 Multiplier, down-counter 2 1 for control states, 2 for Start signal processing, 1 spare Lower 8 bits (two BCD digits) of up-counter 3 Clock generator for 7-segment display controller in HD6 Most significant 2 bits of composite up-counter 3 7-Segment Display controller in HD6 Application 2 to 1 MUX for Decimal Points in HD6 (one spare gate)
74LS169B 4-bit Up/Dn Counter 74LS169B 4-bit Up/Dn Counter 74LS175 74LS194 74LS390 MC14584 Quad D Flip-Flop 4-bit Shift Register Dual Decade Counter Hex CMOS Schmitt
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The first two lines specify the number of input and output variables, respectively, and the next two lines give the labels for the variables in the order in which their values are written in the tabular data. The data lines are an exact reproduction of the entries from the table of Part 2. Invoke man espresso and man -s 5 espresso for details. Save your file and then invoke the minimizer as follows: espresso MG6B.espin The espresso program will return the simplified output in the same format as the input, but it will usually contain fewer product terms and more hyphens, corresponding to fewer gates and fewer gate inputs. Further simplification may sometimes be obtained if the polarity of one or more outputs is changed. If your invoke espresso with the switch -Dopo, the program will try various combinations of output polarities and give an "optimal" configuration in the same format as the input, with an additional comment line containing a bit string corresponding to the output variables in the following format: #.polarity 0111010 A zero in this string indicates that the polarity of the corresponding output must be changed, and a one indicates that the polarity of the corresponding output remains unchanged. Thus you would realize the network as if the polarity comment were not present, and then attach logical inverters to all outputs which have corresponding zeros in the polarity comment. Try the polarity option with the invocation espresso -Dopo MG6B.espin Obtain printed copies of your espresso input and output files for inclusion in your report. From inspection of the espresso outputs create a corresponding circuit realization using a minimum number of gates of any type listed without a pre-assigned application in the table on Page 7. Keep in mind that you can use only three IC packages for the control unit. 4. Practical considerations for hardware implementation on the IDL-800 Logic Lab units require that the additional circuitry shown in Figure 3 on Page 10 be included in the controller, and should also be included in the Mentor Graphics schematic. The input ST is an asynchronous Start input from push-button Switch B on the IDL-800. The switch is debounced internally with an RS flip-flop, and the output remains high as long as the button is depressed. In order for a depression of the switch to initiate a single multiply operation, the two flip-flops with AND Gate 1 produce a single synchronized pulse with a duration of one clock period at the output START, regardless of how long the switch is depressed. This behavior is illustrated by the waveforms beneath the schematic in Figure 3. The system clock for the multiplier will be derived from the IDL-800 Function Generator OUT shown as the signal FG in Figure 3. An LS gate, shown here as AND Gate 2 must be used to obtain a suitable TTL clock signal, CLK, which is connected directly to the clock inputs of the state flip-flop and the down-counters 1 and 2. The controller _DCR1 and _DCR2 outputs are connected to the G6 count enable inputs on the respective down-counters. Up-counter 3 counts on a negative clock transition, and has no count-enable input. Therefore NOR Gate 3 must be used to provide a gated clock with negative phase at _INC3. The gate signal X is the _INC3 signal derived in Part 3 with the tacit assumption that the counter had separate clock and count-enable inputs. The waveforms in Figure 3 show that the output signal _INC3 from the NOR gate (negative logic symbol) will trigger up-counter 3 on a negative clock edge which is synchronous with the positive edge of the system clock which triggers down-counter 1. 5. Use your design of Part 3 with the augmentations of Part 4 to create a schematic for the controller using components listed in the table on Page 7, with the three IC package limit.. 9
ST
D1 C
Q1 Q1
D2 C
Q2 Q2
_INC3 CLK
FG FG CLK ST
Q1
Q2
START
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5. Run the simulation in the default unit delay mode for 5000 nanoseconds and obtain a printer plot of the waveforms for a domain of 0 to 5000 ns. 6. Use palette DEBUG GATES > DELTAS to determine the multiplication time in nanoseconds for both 2x3 and 3x2 by measuring the time from the falling edge of RDY to the next rising edge of RDY. Include these values in your report, and explain why they are different. 7. Reset the state of the simulator. Delete the forces using pull-down Report > Waveforms... Forces OK Select all of the forces in the forces window, and use pop-up Delete twice. Load the force file to multiply 15x15 from $MGC_HOME/user/logic/MG6B_forces_50000 Run the simulation for 50000 ns. Study the simulated output waveforms and discuss the results. You may wish to expand areas of the waveform display to see the details of the state transitions. You may also wish to test for other values of the multiplier and multiplicand to see if the correct product is obtained. 8. Use popup Setup > Window... to set up Domain label interval = 600, Curve height = 30 and Curve spacing = 20. Obtain a printer plot for a domain of 45000 to 49000 ns.
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Open down on the control block and note that Board Architect has attached package identifiers and pin numbers for the entire design. To save these notations, again invoke pull-down Miscellaneous > Merge Annotations > All. Obtain a printed copy of your annotated schematic with pull-down File > Print Sheet. 7. Repeat Part 6 for the up-counter block. 8. Finally, MGC > Exit with Yes for saving the schematic and PCB design data base. 9. Determine a layout of chips on the breadboard with a view toward minimizing the wiring complexity. Refer to the chip pin layouts in the class web notes or previous experiments. 10. Wire your circuit on the breadboard in accordance with the four schematics, and use the 8-inch reinforced leads for connections between the board and the IDL-800 connectors. Adjust the Function generator frequency to observe your multiplier behavior at different speeds. You will have continuous access to the Hardware Laboratory in Room 208 Cushing to test your design before the final presentations that will be held in your assigned laboratory between April 19 and April 23.
Formal Report
Write a two or three-page narrative discussing your results, the difficulties which you encountered, and what you learned from this experiment. Include all of the tables, schematics, waveform charts and espresso files, as requested in the experiment procedure, and make appropriate references to them in your narrative. Your report should be prepared with a word processing program, and it should include a cover sheet. The supporting documentation must include: 1. MG6A a) 7. Page 2: Schematic for the ROM realization. 2. MG6A b) 1. Page 3: C program source code for ROM contents generation. 3. MG6A b) 7. Page 3: Delay timing simulation of the ROM realization. 4. MG6A b) 9. Page 4: Measured delay time of the ROM. 5. MG6B a) 3. Page 9: Final copies of espresso input and output files. 6. MG6B c) 5. Page 12: Unit timing simulation of MG6B_top from 0 to 5000 ns. 7. MG6B c) 6. Page 12: Measured multiplication times for 2x3 and 3x2. 8. MG6B c) 8. Page 12: Unit timing simulation of MG6B_top from 45000 to 49000 ns. 9. HD6 5. Page 12: Annotated Schematic for MG6B_top. 10. HD6 6. Page 13: Annotated Schematic for MG6B_control. 11. HD6 7. Page 13: Annotated Schematic for MG6B_upctr. 12. A copy of this Laboratory MG6/HD6 document, printed duplex (two-sided). All of the annotated schematics for the counting multiplier should show pin numbers and package reference codes corresponding to the actual hardware configuration. Due Date: This report is due in your assigned laboratory period between April 19 and April 23.
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