UNIVERSITI TEKNOLOGI MALAYSIA Faculty of Electrical Engineering

Stop Watch

Report from a project conducted on 20th July 2010 as part of SEC 4722 at the Microprocessor Laboratory

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Group Members Name Goh Chong Sen IC Number 871009-08-5121

Rozlina Binti Ibrahim xxxxxx-xx-xxxx Tang Jia Wei 870814-02-5821

July 2010 ABSTRACT

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We are required to develop a stop watch program using 68000 Assembly Language, which will be executed by pressing the reset button on the EASy68K simulator hardware. The stop watch should have START, CLEAR, STOP, HALT and RESET functions. To implement all the functions, we must press the interrupts buttons on the EASy68k Integrated Development Interface and all the buttons pressed will emit a distinguish sound. The stop watch must be accurate to the real time clock. We also are required to design the circuit implementation of the hardware.

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Table of Contents
1. 2. 3. 4. 5. 6. INTRODUCTION .............................................................................................................. 4 PROCEDURES .................................................................................................................. 4 RESULT AND DICUSSION ............................................................................................. 5 CONCLUSIONS ................................................................................................................ 8 REFERENCES ................................................................................................................... 8 APPENDICES .................................................................................................................... 9

July 2010 1. INTRODUCTION

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A stop watch is use to measure the amount of time elapsed from a particular time until the time when it is stop. We are used an external devices use 68ks 3 Interrupt Priority Level inputs (IPL0*, IPL1*, IPL2*) to request the encoded priority level of the hardware interrupt. The 3-bit code IPL0* IPL2* specifies one of 8 interrupt request from 0 to 7. The interrupt mask bits I2, I1, I0, in the status register determine the level of interrupt that will be function. The five functions for the Stop Watch are START, CLEAR, STOP, HALT and RESET. The START button is to start count and display. The CLEAR button is to clear the display to 00.00.0 and reset count. The STOP button is to stop count and stop display. The HALT button is to stop display but still count. When RESET, the stop watch will reset everything (count, display, SR & etc) For this Stop Watch, the number of digit that we are used is as shown in Figure 01.

Figure 01: Number of digit used for the stop watch.

2. PROCEDURES A flowchart has been constructed before the program is coded. The purpose of the flowchart is to easier the coding of the program. Then, program for Stop Watch is coded by using 68000 Assembly Language. After coding, the program is tested using EASy68k Integrated Development Interface. By using the interrupt buttons on the EASy68k, the START, CLEAR, STOP, HALT and RESET functions are tested. After the stop watch program is functional, the circuit implementation of the hardware is designed by using PSPICE and Microsoft Visio. Basic gates are used for the interrupt design for start, clear, stop, and halt. A true table is drawn first and continues with the K-maps to obtain a simplest form of gate. After that, the digital circuit of the interrupt is drawn. Lastly, a 555 timer is used for design the halt-reset pin to obtain the RESET function. For the stop watch, we are assumed that the frequency of the processor used is 8MHz. The true table, K-maps, and flowchart of this experiment are provided at the appendices of this report.

July 2010 3. RESULT AND DICUSSION

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Clock

8MHz OUT 8 1 2 U1 OSC14 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 15 27 26 25 1 5407 1 2 1 5407 2 2 24 12 13 10 19 20 23

8

Reset
V1 V1 +5Vdc 1M +5Vdc 4.7K 4.7K RESISTOR

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 CLK IPL0 IPL1 IPL2 BERR BGACK BR DTACK HALT RST VPA

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 FC0 FC1 FC2 AS BG EN LDS R/W UDS VMA

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 54 55 30 29 28 6 11 22 8 9 7 21

+5Vdc 1mikrof arad

1mikrof arad

1mikrof arad

GND

2 4 5 6 7

TRIGGER RESET OUTPUT CONTROL THRESHOLD DISCHARGE

VCC

V1

1M

555D 3

68000/LCC

Figure 02: The circuit for reset and clock input to the microprocessor.

START

CLEAR

STOP

HALT

V1 +5Vdc U7A 4049

4.7K

4.7K

4.7K

U4A 4049

U5A 4049

U6A 4049

U1 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 15 27 26 25 24 12 13 10 19 20 23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 53 54 55 30 29 28 6 11 22 8 9 7 21

1 2 6 4 5 1 2 6 4 5 1 2 6 4 5 1 2 6 4 5 1 2 6 4 5 4049 3 2 4049 U15A 1 3 2 3 2 U14A 4049 1 3 2 3 2 U8A

Interrupt IPL0, IPL1, IPL2

CLK IPL0 IPL1 IPL2 BERR BGACK BR DTACK HALT RST VPA

FC0 FC1 FC2 AS BG EN LDS R/W UDS VMA

68000/LCC

Figure 03: Digital circuit to compute the four interrupt levels.

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For the circuit implementation of Figure 02, 555 timer and additional of resister capacitor is used to implement the hardware reset. This is due to the hardware reset for 68000 required to be active for a minimum of 100ms at both *Halt and *RESET pin. Hence, a 555 timer plus some suitable value of resister capacitor with proper connection to produce a 100ms LOW to active the reset when reset button is pressed. Figure 03 show the start, clear, stop, halt functions implemented using interrupt of 68000. A basic gate with SOP method is used as one of the design for the interrupt. Other methods like basic gates, 8 to 3 encoder, multiplexer, and etc might also be used depends on the designer. A basic gate with SOP used due to its simplest concept where it produces active high output and additional of inverter for interrupts that is active low.
ORG $1000 RESET MOVE.L #$30000,D5 ;DELAY CONSTANT=(SPEED/10-1044)/18 MOVE.W #$2000,SR CLR.L D6 CLR.L D7 LEA SEG7,A2 CLR.L D0 CLR MOVE.B #%01000000,(A2,D0) ADD.B #2,D0 CMP.B #16,D0 BNE CLR LEA SRESET,A1 MOVE.B #70,D0 TRAP #15 LOOP BTST #0,D7 ;COUNT FLAG BEQ LOOP RUN BTST #1,D7 ;DISPLAY FLAG BEQ NODISP JSR DISPLAY NODISP JSR DELAY ADD.L #1,D6 CMP.L #$EA60,D6 ;COMPARE WITH 100MIN (MAX) BNE SKIP CLR.L D6 SKIP BRA RUN DISPLAY LEA LEA CLR.L CLR.L CLR.L MOVE.L DIVU MOVE.L SWAP ANDI.L MOVE.B ANDI.L DIVU MOVE.L SEG7,A2 TABLE,A0 D0 D1 D2 D6,D2 #10,D2 D2,D0 D0 #$000000FF,D0 (A0,D0),14(A2) #$0000FFFF,D2 #60,D2 D2,D0 SWAP ANDI.L DIVU MOVE.B MOVE.B SWAP ANDI.L MOVE.B BSET MOVE.B ANDI.L DIVU MOVE.B MOVE.B SWAP ANDI.L MOVE.B BSET MOVE.B RTS DELAY D0 #$0000FFFF,D0 #10,D0 D0,D1 (A0,D1),10(A2) D0 #$000000FF,D0 (A0,D0),D0 #7,D0 D0,12(A2) #$0000FFFF,D2 #10,D2 D2,D0 (A0,D0),6(A2) D2 #$000000FF,D2 (A0,D2),D2 #7,D2 D2,8(A2)

CLR.L D4 MOVE.L D5,D4 BTST #1,D7 BNE DEL ADD.L #50,D4 ;CYCLES DIFFERENCE BETWEEN DISPLAY AND NO DISPLAY/CYCLES PER ONE DELAY DEL SUB.L #1,D4 BNE DEL RTS HALT BCLR #1,D7 ;CLEAR DISPLAY FLAG RTS STOP BCLR #0,D7 ;CLEAR COUNT FLAG MOVEM.L D0-D2,-(SP) ;SAVE REGISTER DATA JSR DISPLAY MOVEM.L (SP)+,D0-D2 ;LOAD REGISTER DATA STP BTST #0,D7 ;POLL FOR COUNT FLAG CHANGE(START) BEQ STP RTS

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START CLEAR MOVE.B RTS CLR.L CLR.L JSR RTS ORG DC.L ORG DC.L ORG DC.L ORG DC.L ORG DC.L ORG DC.L IP1 ORG LEA MOVE.B TRAP JSR RTE LEA MOVE.B TRAP JSR RTE LEA MOVE.B TRAP JSR RTE LEA MOVE.B TRAP JSR RTE EQU DC.B DC.B DC.B DC.B DC.B DC.B DC.B END #3,D7 D6 D7 STOP $000 $01000000 $004 $1000 $064 IP1 $068 IP2 $06C IP3 $070 IP4 $2000 SHALT,A1 #70,D0 #15 HALT SSTOP,A1 #70,D0 #15 STOP SCLEAR,A1 #70,D0 #15 CLEAR SSTART,A1 #70,D0 #15 START $E00000 %00111111,%00000110,%01011011,%01001111,%01100110 %01101101,%01111101,%00000111,%01111111,%01101111 'Reset.wav',0 'Halt.wav',0 'Stop.wav',0 'Start.wav',0 'Clear.wav',0 $1000 ;SET COUNT&DISPLAY FLAGS ;CLEAR COUNT ;CLEAR FLAGS

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IP2

IP3

IP4

SEG7 TABLE SRESET SHALT SSTOP SSTART SCLEAR

The source code of the program is shown above, we implement control the flow of the program with two flags defined in bit 0 and bit 1 in D7 where bit 0 is count flag, bit 1 is display flag. Thus the four interrupt button is changing the flags to its desired state. Example is START button is changing both flag to 1 which means both counting and displaying will be performed. The delay time for this program is dependent on the speed of the processor and can be defined by the formula, DELAY CONSTANT= (SPEED/10-1044)/18. Delay Constant refers to the time of delay, or number of subtracting loop in delay function. Speed is processor speed in Hertz or cycles per

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second. Divide by 10 is to get the speed unit into cycles per 0.1 second. 1044 is the number of bus cycles in without any delay while 18 is number of bus cycles per one loop of delay. By substituting in the processor speed, we can get the delay constant for 0.1 second, which means every count will be performed for each 0.1 second. Thus, this Stop Watch program can be calibrated to run in any processor speed. In addition, this program has display sensitivity of 0.1 second. However counting sensitivity is depends on the delay constant, which depends on the speed of processor. As an example, for delay constant of 10000, when we push the STOP button at halfway of delay, lets say when the delay constant is subtracting and stop at 5000. After the START button is pressed, the delay will continue from delay constant of 5000, and in this case the sensitivity of counting is approximate to 0.1/10000 seconds, which is 0.1 micro seconds.

4. CONCLUSIONS In conclusion, this experiment simulates a stopwatch using EASy68K with function START, STOP, CLEAR, HALT and RESET. All the functions is able to implement by using interrupt and reset of EASy68K but one component which is the stopwatch that accurate with real time clock is not able to implement correctly. This is due to the different processing speed of each computer. Hence, the stopwatch is not able to perform accurate to the real time clock at different kind of computer, the delay constant need to be adjusted for each type of processing speed.

5. REFERENCES [1] James L. Antonakos. (2004). The 68000 Microprocessor: Hardware and Software Principles Motorola 68000. Wikipedia, the free encyclopedia. 20 July, 2010.

and Application: Fifth Edition. Pearson: Prentice Hall. [2]

<http://en.wikipedia.org/wiki/Motorola_68000> [3] "Motorola 68000." The Free Dictionary By Farlex. 20 July, 2010.

<http://encyclopedia2.thefreedictionary.com/68000+Microprocessor> [4] Lee Davison. "EASy68K Example programmes." EASy68K. 23 July, 2010.

<http://members.multimania.co.uk/leeedavison/68k/easy68k/index.html> [5] Huntmine. "Stop Watch for Motorola 68hc12 Microprocessor." Eadaboard.com. 23 July

2010. <http://www.edaboard.com/ftopic46655.html> [6] "The 68000 Architecture." OpenSourceProject.org.cn. 27 July, 2010.

<http://book.opensourceproject.org.cn/embedded/oreillyedsignbed/opensource/0596003625/dbhardwa re-chp-7-sect-1.html>

July 2010 6. APPENDICES

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A B (START) (CLEAR) 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1

C (STOP) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D (HALT) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

ILP2 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0

ILP1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0

ILP0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0

Table 01: The truth table for three interrupt inputs (active high).

Figure 04: K-Maps for the true table of Table 01 (SOP).

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Main Program Delay

START

Clear data register use for delay. Initialize delay count.

Display

Clear data register. Reset SR.

Is Display Flag = 0 ? No Yes ADD.L #50,D4 ;CYCLES DIFFERENCE

BETWEEN DISPLAY AND NO DISPLAY

Calculate & send value to last seven segment. 1/10 second

Initialize display value of seven segment display

Calculate & send value to seven segment Ten. second

No

Is all segment display intialized? SUB.L #1,D4 NO

Calculate & send value to seven segment second

Yes Yes Is Count Flag = 0 ? Is Delay end?

Calculate & send value to seven segment Ten minute

Yes

Calculate & send value to seven segment minute

No RTS Is Display Flag = 0 ? No

RTS

Yes

Delay

Counting

Display

Figure 05: The flowchart for Main program, Delay, and Display.

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Interrupt Level 4

Interrupt Level 3

Interrupt Level 2

Interrupt Level 1

IP4

IP3

IP2

IP1

Play Start sound

Play Clear sound

Play Stop sound

Play Halt sound

Start

Clear

Stop

Halt

RTE

RTE

RTE

RTE

Start

Clear

Stop

Halt

Set flag D7=3

Clear all flag count D6

Clear Count flag

Clear Display flag

RTS

Stop

Save counted data

RTS

RTS

Display (current value)

Restore Counted data

Yes Is Count Flag = 0 ? No

RTS

Figure 06: The flowchart for interrupt from level 4 to level 1.

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