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APPENDIX B-2
Farmwald/Horowitz Patents No. 1. Claim Term, Phrase, Claims or Clause access time 937/4(1), 5(1) information 097/6(1) NVIDIAS Preliminary Proposed Construction information that specifies a predetermined non-zero amount of time that a device must wait from receiving a transaction request to responding to a transaction request a predetermined non-zero amount of time that must transpire before commencing an action. NVIDIAS Evidence 097 patent, 7:1-4, 9:58-64, 10:26-38; 15:64-16:11, 16:44-67, 20:17-31; 937 patent, 7:1-4, 9:59-65, 10:27-39; 15:6316:9, 16:45-65, 20:14-28. 696 patent, 6:34-39, 7:1-8, 9:57-63, 10:8-12, 36-39, 11:19-31, 15:60-16:10, 16:45-65, 20:14-28; See also citations to same or substantially similar content in 937 patent. 997 patent, 6:34-39, 7:11-18, 10:3-8, 20-26, 48-51, 11:19-31, 16:18-32, 16:66-17:23, 20:43-57. 020 patent, 6:62-66, 8:42-57, 9:46-64; See also citations to same or substantially similar content in 937, 281, 097, 696, 997 patents.

2.

delay time

937/31(30) 696/27(26), 29(26)

3.

read delay

997/1, 19, 32, 35, 38 997/1, 19, 32, 38 696/26, 29(26), 30(26) 281/36, 42(36), 43(36) 097/1, 5(1), 26 937/1, 3(1), 4(1), 5(1), 18, 23(18), 24(18), 37(30) 020/2(1), 32(28), 34(28), 37(28), 38

4.

in response to

a predetermined non-zero amount of time that must transpire before data is read from a memory device. plain meaning.

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No. 5.

6.

Claim Term, Phrase, Claims or Clause information that 937/32(30) represents an amount of time which lapses latch circuitry 937/19(18)

NVIDIAS Preliminary Proposed Construction information that indicates a predetermined non-zero amount of time that must lapse. circuitry for maintaining a particular state of a signal until being reset.

NVIDIAS Evidence 937 patent, , 6:34-39, 7:1-8, 9:57-63, 10:8-12, 36-39, 11:19-31, 15:60-16:10, 16:45-65, 20:14-28 937 patent,10:15-27, 49-60, 12:12-16, 23:43-52; 25:60-26:9; The Computer Glossary Fourth Edition 1989 same for Fifth Edition from 1991 (A latch is an electronic circuit, such as a flip-flop, that maintains one of two states. It is set and then reset.); IBM Dictionary of Computing 1994 (latch (1) a bistable circuit that is set and reset by appropriate input signals; (3) an electronic circuit that records the status of a signal until it is reset); Microsoft Computer Dictionary 1991 (latch a circuit or circuit element used to maintain a particular state, such as on or off, or logical true or false. A latch changes state only in response to a particular input. A flip-flop is one kind of circuit.); The Illustrated Dictionary of Microcomputers Third Edition 1990 (latch an arrangement or circuit used to hold data in a ready position until required, usually controlled by another condition or circuit. Also called lock. latching a technique in which data is held in a circuit until other circuits are ready to change this circuit)

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No. 7.

Claim Term, Phrase, Claims or Clause latch 937/19(18)

NVIDIAS Preliminary Proposed Construction maintaining a particular state of a signal until being reset, as distinguished from sampling

NVIDIAS Evidence 937 patent,10:15-27, 49-60, 12:12-16, 23:43-52; 25:60-26:9; The Computer Glossary Fourth Edition 1989 same for Fifth Edition from 1991 (A latch is an electronic circuit, such as a flip-flop, that maintains one of two states. It is set and then reset.); IBM Dictionary of Computing 1994 (latch (1) a bistable circuit that is set and reset by appropriate input signals; (3) an electronic circuit that records the status of a signal until it is reset); Microsoft Computer Dictionary 1991 (latch a circuit or circuit element used to maintain a particular state, such as on or off, or logical true or false. A latch changes state only in response to a particular input. A flip-flop is one kind of circuit.); The Illustrated Dictionary of Microcomputers Third Edition 1990 (latch an arrangement or circuit used to hold data in a ready position until required, usually controlled by another condition or circuit. Also called lock. latching a technique in which data is held in a circuit until other circuits are ready to change this circuit); See also citations for sample / samples / sampling. 020 patent, 6:12-26, 20:45-60; 937 patent, 6:14-25, 20:45-60; 997 patent,

8.

memory controller / controller device /

997/1, 3(1), 19, 26(19), 31(19),

a device that includes circuitry to direct the actions of one or more memory

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No.

Claim Term, Phrase, Claims or Clause memory controller 32, 38 device 696/26 937/18, 19(18), 22(18), 23(18), 24(18), 26(18), 29(18), 30, 31(30) 020/1, 2(1), 10(1), 11(1), 12(1), 13(1), 14(1), 38, 47(38), 49(38)

NVIDIAS Preliminary Proposed Construction devices

NVIDIAS Evidence 6:24-35, 21:7-19; 696 patent, 6:13-27, 20:45-60; 020 patent, claims 1, 17, 28, 38. 937 Reexam, 12/18/2009 OA, 8/6/2010 OA, 11/24/2010 ACP, 4/4/2011 ACP (and citations therein).

9.

integrated circuit controller device

020/38

A controller device constructed on a single monolithic substrate, commonly called a chip.

10.

memory device

937/2(1), 4(1), 5(1), 8(1), 18, 23(18), 24(18), 30, 32(30), 36(30) 37(30), 38(30), 097/1, 5(1), 6(1), 26 281/36, 38(36), 39(36), 40(36),

A device in which data can be stored and retrieved electronically.

Rambus v. Infineon, 318 F.3d 1081, 1091 (Fed. Cir. 2003); Rambus v. Hynix II, 05-00334, 7/10/2008 Claim Construction Order at 21; The New IEEE Standard Dictionary of Electrical and Electronic Terms 662 (5th ed. 1993); IBM Dictionary of Computing 347 (10th ed. 1994). See also citations for controller device; 937 Reexam, POs 12-18-09 Response. 020 patent, 1:20-27, 3:23-28, 31-32, 50-55, 4:10-14, 5:29-32, 58-63, 7:1830, 19:63-20:13. See also citations to same or substantially similar content in 937, 097, 281, 696, 997 patents; Rambus v. Hynix II, 05-00334, 7/10/2008 Claim Construction Order at 32-35. 937 patent, 3:63-4:2.

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No.

Claim Term, Phrase, or Clause

Claims 42(36), 43(36), 44(36), 45(36), 46(36) 696/26, 27(26), 28(26), 29(26), 30(26), 31(26), 997/1, 19,26(19), 32, 38 020/1, 2(1), 28, 29(28), 32(28), 34(28), 35(28), 37(28), 38, 49(38)

NVIDIAS Preliminary Proposed Construction

NVIDIAS Evidence 95/001,134, 2010-03-29 POs Comments at 3. 937 Reexam, 12/18/2009 OA, 8/6/2010 OA, 11/24/2010 ACP, 4/4/2011 ACP, NVIDIAs 11/23/2011 Cross-Appeal Brief (and citations therein). U.S. Patent No. 5,841,715, claims 1 and 3. U.S. Patent No. 5,657,481, claim 1.

11.

operation code

937/1, 3(1), 4(1), 5(1), 14(1), 15(1), 17(1), 18, 23(18), 24(18), 29(18), 30, 37(30) 020/2(1), 32(28), 34(28), 37(28), 38 696/26, 29(26), 30(26), 35(26) 997/1, 2(1), 3(1), 19, 26(19), 31(19), 32(19), 38

One or more control bits specifying a type of action to be performed by a memory device.

020 patent, 3:50-60, 4:1-5, 10:12, 5:29-50, 6:16-17, 53-60, 8:58-63, 9:2464. See also citations to same or substantially similar content in 937, 281, 696, 997 patents; The Authoritative Dictionary of IEEE Standard Terms 769 (2001 ed.)

12.

precharge information 937/17(1) 696/35(26),

Information denoting whether sense amplifiers and/or bit lines (or a portion of the sense amplifiers and/or bit lines) should be precharged. 5

696 patent, 10:52-60, 32-44; See also citations to same or substantially similar content in 937, 997 patents; Rambus v. Hynix I, 00-20905,

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No.

Claim Term, Phrase, or Clause

Claims 997/19, 32(30)

NVIDIAS Preliminary Proposed Construction

NVIDIAS Evidence 11/15/2004, Claim Construction Order at 22-23. Rambus v. Hynix II, 05-00334, Dkt. No. 312, Rambuss Opening Markman Brief at 18; Murphy Decl. 188-95. Rambus v. Hynix I, 00-20905, Dkt. No. 328, Rambuss Opening Claim Construction Brief at 19. 696 patent, 6:28-54, 10:8-14; 16:4552; Fig. 16. 696 patent, 6:34-39, 7:1-8, 9:57-63, 10:8-12, 36-39, 11:19-31, 15:60-16:10, 16:45-65, 20:14-28; See also citations to same or substantially similar content in 937, 097 patents. 020 patent, 21:50-55, 22:21-56, 23:2641; 937 patent, 25:60-26:9; See also citations to same or substantially similar content in 937, 097, 696, 997 patents; Przybylski Depo Testimony, 8/18/2011 at p. 86:1219, 8/19/2011 at pp. 314:12-315:16 Przybylski Hearing Testimony, 10/13/2011 at pp. 831:18832:18, 833:17-834:15. Rambus v. Hynix II, 05-00334, Dkt. No. 312, Rambuss Opening Markman Brief at 15; Dkt. No. 313, Murphy Decl., 156.

13.

programmable register representative of a number of clock cycles of the external clock signal to transpire sample / samples / sampling

696/26

14.

696/28(26) 937/5(1)

A register within a memory device that is permanently or semi-permanently loaded with a fixed value. indicates a number of clock cycles of the external clock signal that must transpire before commencing an action.

15.

997/1, 19, 32, 38 696/27(26), 28(26) 097/1, 26 937/1, 18, 23(18), 26(18) 020/14(1), 17, 25(17), 29(28), 30(28), 34(28), 49(38)

obtain/ obtains/ obtaining at one or more discrete points in time, as distinguished from latch/ latches/ latching.

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No.

Claim Term, Phrase, or Clause

Claims

NVIDIAS Preliminary Proposed Construction

NVIDIAS Evidence

16.

value is representative 696/27(26), of a delay time to 29(26) transpire variable delay line 020/11(1), 12(1)

17.

937 Reexam, 12/18/2009 OA, 8/6/2010 OA, 11/24/2010 ACP, 4/4/2011 ACP (and citations therein). information that indicates a 696 patent, 6:44-49, 7:1-8, 9:57-63, predetermined non-zero amount of time 10:8-12, 36-39, 11:32-45, 15:60-16:10, that must transpire before commencing 16:45-65, 20:14-28. an action. a delay line that uses feedback to 020 patent, 22:57-23:13, Fig. 12. provide a varying amount of the delay.

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Barth II Patents No. 1. Claim Term, Phrase, or Clause after a second/third delay time has transpired memory device Claims 119/21 952/21 953/25 2. 050/29 119/21 952/21, 22(21) 953/25 3. integrated circuit memory device 050/29 119/21 952/21, 22(21) A memory device constructed on a Rambus v. Infineon, 318 F.3d 1081, single monolithic substrate, commonly 1091 (Fed. Cir. 2003); Rambus v. called a chip. Hynix II, 05-00334, 7/10/2008 Claim Construction Order at 21; The New IEEE Standard Dictionary of Electrical and Electronic Terms 662 (5th ed. 1993); IBM Dictionary of Computing 347 (10th ed. 1994). See also citations for memory device. Signals provided to a memory device 119 patent, Fig. 10; 5:61-63, 1:37-39; for initiating a sense operation within 9:56-59; 1:40-44; 11:40-42; See also the memory device. citations to same or substantially similar content in 050, 952 and 953 patents. The memory device begins to perform a write operation only after a first predetermined non-zero amount of time transpires. 119 patent, 12:18-25; 2:18-19; See also citations to same or substantially similar content in 050, 952 and 953 patents. A device in which data can be stored and retrieved electronically. NVIDIAs Preliminary Proposed Construction After an additional second/third predetermined non-zero amount of time has transpired. NVIDIAS Evidence 119 patent, 10:7-10, 11:18-22, 3:313, Fig. 3; See also citations to same or substantially similar content in 952 and 953 patents. 119 patent, 1:19-44, 7:10-18, 19:3022:57; 953 patent, 19:60-26:11; 952 patent, 19:59-24:35; 050 patent, 19:53-22:67.

4.

sense command

050/29 119/21 952/21 953/25

5.

the memory device initiates a write operation after a first delay time transpires

953/25

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6.

the write command is 119/21 presented/posted 952/21 internally to/within the memory device after a first/second delay [time] has transpired from when the write command is received

The write command is provided to a memory core of a memory device only after a first/second predetermined nonzero amount of time has transpired from when the write command is received by the memory device.

7.

write command

050/29 119/21 952/21 953/25

119 patent, 1:37-39, 2:21-25, 10:2466, 11:1-6, Figs. 1, 16-21, 48; See also citations to same or substantially similar content in 050, 952 and 953 patents; File History of patent # 7,197,611, 8/21/2006 Amendment to Final Office Action. 2/17/06. Amendment, at 9 (pointing to support in 1J[102 of specification [equivalent to ' 119 patent, col. 10, 11.48-57]) Signals provided to a memory device 119 patent, 12:18-25; 2:18-19; See for initiating a write operation within a also citations to same or substantially memory device. similar content in 050, 952 and 953 patents. a predetermined non-zero amount of time that must transpire before commencing an action. 119 patent, 10:24-66, 11:1-6, Figs. 17-21. See also citations to same or substantially similar content in 050, 952 and 953 patents. 2/17/06 Amendment, at 9 (pointing to support in 1J[102 of specification [equivalent to ' 119 patent, col. 10, 11.48-57])

8.

delay time

119/21 952/21 953/25

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