PIN CONFIGURATION OF 8085 1.

The microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique. 2. The microprocessor is capable of performing various computing functions and making decisions to change the sequence of program execution. 3. In large computers, a CPU implemented on one or more circuit boards performs these computing functions. 4. The microprocessor is in many ways similar to the CPU, but includes the logic circuitry, including the control unit, on one chip. 5. The microprocessor can be divided into three segments for the sake clarity, arithmetic/logic unit (ALU), register array, and control unit.
8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows

1. Power supply and clock signals 2. Address bus 3. Data bus 4. Control and status signals 5. Interrupts and externally initiated signals 6. Serial I/O ports Power supply and Clock frequency signals: 1. Vcc + 5 volt power supply 2. Vss Ground 3. X1, X2 : Crystal or R/C network or LC network connections to set the frequency of internal clock generator. 4. The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally. 5. CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor. Address Bus: 1. A8 - A15 (output; 3-state) 2. It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address; Multiplexed Address / Data Bus: 1. AD0 - AD7 (input/output; 3-state) 2. These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus. During the Opcode fetch operation, in the first clock cycle, the lines deliver the lower order address A0 - A7. 3. In the subsequent IO / memory, read / write clock cycle the lines are used as data bus. 4. The CPU may read or write out data through these lines. Control and Status signals: 1. ALE (output) - Address Latch Enable. 2. This signal helps to capture the lower order address presented on the multiplexed address / data bus. 3. RD (output 3-state, active low) - Read memory or IO device. 4. This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device. 5. WR (output 3-state, active low) - Write memory or IO device. 6. This indicates that the data on the data bus is to be written into the selected memory location or I/O device.

7. IO/M (output) - Select memory or an IO device. This status signal indicates that the read / write operation relates to whether the memory or I/O device. 8. It goes high to indicate an I/O operation. It goes low for memory operations. Status Signals: It is used to know the type of current operation of the microprocessor.

1. Interrupts and Externally initiated operations: 2. They are the signals initiated by an external device to request the microprocessor to do a particular task or work. 3. There are five hardware interrupts called, TRAP RST 7.5 RST 6.5 RST 5.5 INTR INPUTS

INTA (ACTIVE LOW OUTPUT 4. On receipt of an interrupt, the microprocessor acknowledges the interrupt by the active low INTA (Interrupt Acknowledge) signal.
Reset In (input, active low) 1. This signal is used to reset the microprocessor. 2. The program counter inside the microprocessor is set to zero. 3. The buses are tri-stated. Reset Out (Output) 1. It indicates CPU is being reset. 2. Used to reset all the connected devices when the microprocessor is reset. Direct Memory Access (DMA): Tri state devices:

1. 3 output states are high & low states and additionally a high
impedance state.

2. When enable E is high the gate is enabled and the output Q can be 1

or 0 (if A is 0, Q is 1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters into a high impedance state.

3. For both high and low states, the output Q draws a current from the
input of the OR gate.

4. When E is low, Q enters a high impedance state; high impedance

means it is electrically isolated from the OR gate's input, though it is physically connected. Therefore, it does not draw any current from the OR gate's input. 5. When 2 or more devices are connected to a common bus, to prevent the devices from interfering with each other, the tristate gates are used to disconnect all devices except the one that is communicating at a given instant. 6. The CPU controls the data transfer operation between memory and I/O device. Direct Memory Access operation is used for large volume data transfer between memory and an I/O device directly. 7. The CPU is disabled by tri-stating its buses and the transfer is effected directly by external control circuits. 8. HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the microprocessor acknowledges the request by sending out HLDA signal and leaves out the control of the buses. After the HLDA signal the DMA controller starts the direct transfer of data. 1. READY (input) 2. Memory and I/O devices will have slower response compared to microprocessors. 3. Before completing the present job such a slow peripheral may not be able to handle further data or control signal from CPU. 4. The processor sets the READY signal after completing the present job to access the data. 5. The microprocessor enters into WAIT state while the READY pin is disabled. Single Bit Serial I/O ports: 1. SID (input) - Serial input data line 2. SOD (output) - Serial output data line These signals are used for serial communication.

PIN DETAILS :

1.4 ADDRESSING MODES Every instruction of a program has to operate on a data.

The method of specifying the data to be operated by the instruction is called Addressing. The 8085 has the following 5 different types of addressing. 1. Immediate Addressing 2. Direct Addressing 3. Register Addressing 4. Register Indirect Addressing 5. Implied Addressing 1. Immediate Addressing: In immediate addressing mode, the data is specified in the instruction itself. The data will be a part of the program instruction. EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP, 2700H. 2. Direct Addressing: In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this addressing mode, the program instructions and data can be stored in different memory. EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator; SHLD 3000H 3. Register Addressing: In register addressing mode, the instruction specifies the name of the register in which the data is available. EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C. 4. Register Indirect Addressing: In register indirect addressing mode, the instruction specifies the name of the register in which the address of the data is available. Here the data will be in memory and the address will be in the register pair. EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX B. 5. Implied Addressing: In implied addressing mode, the instruction itself specifies the data to be operated. EX. CMA - Complement the content of accumulator; RAL