1. Mention the classification of 8085 instruction set. An instruction is a binary pattern designed inside a microprocessor to perform a specific function.

The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. These instructions can be classified into the following five functional categories: 1. data transfer (copy) operations, 2. arithmetic operations,

3. logical operations, 4. branching operations, and 5. machine-control operations. 2. list out the limitation of 8085 can quality as an MPU (i) The lower order address bus of the 8085 microprocessoris multiplexed (time shared) with the data bus. The buses need to be demultiplexed. (ii)Appropriate control signals need to be generated to interface memory and I/O with the 8085. yes but external hardware as to be interfaced. 3. What are the general purpose register used in 8085? The 8085 is an 8-bit computer, therefore the length of the general registers B, C, D, E, H, and L is 8 bits. Some registers, however, can be paired, specifically BC, DE, and HL, to hold and use 16... 4. Mention the flag register used in 8085? Sign flag, Zero flag, Auxillary flag, Parity flag, Carry flag. 5. What are the functions of bus interface unit (BIU)? (a) Fetch instructions from memory. (b) Fetch data from memory and I/O ports. (c) Write data to memory and I/O ports. (d) To communicate with outside world. (e) Provide external bus operations and bus control signals. 6. What is software interrupt?

7. List out the partitions if memory segments 1. Code segment, 2. Data segment, 3. Extra segment, and 4. Stack segment.

7. How the operating mode of 8086 is determined?.

By using the pin MN/MX MINIMUM/MAXIMUM: indicates what mode the processor is to operate.

8. What is register Addressing Modes?

Most 8086 instructions can operate on the 8086's general purpose register set. By specifying the name of the register as an operand to the instruction, you may access the contents of that register. Consider the 8086 mov (move) instruction: mov destination, source

This instruction copies the data from the source operand to the destination operand. The eight and 16 bit registers are certainly valid operands for this instruction. The only restriction is that both operands must be the same size. 10 Mention the FLAG TRANSFER INSTRUCTIONS in 8086? LAHF SAHF PUSHF POPF 11 How the program execution transfer instruction is used in 8086?

12 Give the assembly language program statement format

13. State the internal address for 8255 A The internal address for the device are: Port-A 00; Port-B 01; Port-C -10; control register 11. 14. What is 8251A The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial data communication. As a peripheral device of a microcomputer system, the 8251 receives parallel data from the CPU and transmits serial data after conversion. This device also receives serial data from the outside and transmits parallel data to the CPU after conversion. 15. How the 8279 was initialized? 16. What is maximum clock frequency and read back feature of 8254? (i)The clock frequency for the 8254 timer is the NTSC frequency 14.31818 MHz (ii)8254 has powerful command called READ BACK command which allows the user to check the count value, programmed mode and current mode and current status of the counter.

17. Mention the three standard device organization of 64 KB density SRAM tranceiver latch and decoder 18. What is refreshing in DRAM?

19. How to buffering the outputs of port devices? The output buffer is computer memory allocated by the serial port object to store data that is to be written to the device. When writing data to your device, the data flow follows these two steps: 1. The data specified by the write function is sent to the output buffer. 2. The data in the output buffer is sent to the device. 20. What is Shaft encoder? A rotary encoder, also called a shaft encoder, is an electro-mechanical device that converts the angular position of a shaft or axle to an analog or digital code, making it an angle transducer. Rotary encoders are used in many applications that require precise shaft unlimited rotation including industrial controls, robotics, special purpose photographic lenses[1], computer input devices (such as optomechanical mice and trackballs), and rotating radar platforms. There are two main types: absolute and incremental

Internal Architecture of 8085 Microprocessor

Control Unit Generates signals within uP to carry out the instruction, which has been decoded. In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur. Arithmetic Logic Unit The ALU performs the actual numerical and logic operation such as add, subtract, AND, OR, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation in Accumulator. Registers The 8085/8080A-programming model includes six registers, one accumulator, and one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter. They are described briefly as follows. The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions. Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. Flags The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the Table and their bit positions in the flag register are shown in the Figure below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) is set to one. When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is not used as a register; five bit positions out of eight are used to store the outputs of the five flip-flops. The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction. These flags have critical importance in the decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested through the software instructions. For example, the instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY flag is set. The thorough understanding of flag is essential in writing assembly language programs. Program Counter (PC) This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location Stack Pointer (SP) The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16bit address in the stack pointer. The stack concept is explained in the chapter "Stack and Subroutines." Instruction Register/Decoder Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then takes instruction and decodes or interprets the instruction. Decoded instruction then passed to next stage. Memory Address Register Holds address, received from PC, of next program instruction. Feeds the address bus with addresses of location of the program under execution. Control Generator Generates signals within uP to carry out the instruction which has been decoded. In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur.

Register Selector This block controls the use of the register stack in the example. Just a logic circuit which switches between different registers in the set will receive instructions from Control Unit. General Purpose Registers uP requires extra registers for versatility. Can be used to store additional data during a program. More complex processors may have a variety of differently named registers. 8085 System Bus Typical system uses a number of busses, collection of wires, which transmit binary numbers, one bit per wire. A typical microprocessor communicates with memory and other devices (input and output) using three busses: Address Bus, Data Bus and Control Bus. Address Bus One wire for each bit, therefore 16 bits = 16 wires. Binary number carried alerts memory to open the designated box. Data (binary) can then be put in or taken out.The Address Bus consists of 16 wires, therefore 16 bits. Its "width" is 16 bits. A 16 bit binary number allows 216 different numbers, or 32000 different numbers, ie 0000000000000000 up to 1111111111111111. Because memory consists of boxes, each with a unique address, the size of the address bus determines the size of memory, which can be used. To communicate with memory the microprocessor sends an address on the address bus, eg 0000000000000011 (3 in decimal), to the memory. The memory the selects box number 3 for reading or writing data. Address bus is unidirectional, ie numbers only sent from microprocessor to memory, not other way. Data Bus Data Bus: carries data, in binary form, between P and other external units, such as memory. Typical size is 8 or 16 bits. Size determined by size of boxes in memory and P size helps determine performance of P. The Data Bus typically consists of 8 wires. Therefore, 28 combinations of binary digits. Data bus used to transmit "data", ie information, results of arithmetic, etc, between memory and the microprocessor. Bus is bi-directional. Size of the data bus determines what arithmetic can be done. If only 8 bits wide then largest number is 11111111 (255 in decimal). Therefore, larger number have to be broken down into chunks of 255. This slows microprocessor. Data Bus also carries instructions from memory to the microprocessor. Size of the bus therefore limits the number of possible instructions to 256, each specified by a separate number. Control Bus Control Bus are various lines which have specific functions for coordinating and controlling uP operations. Eg: Read/NotWrite line, single binary digit. Control whether memory is being written to (data stored in mem) or read from (data taken out of mem) 1 = Read, 0 = Write. May also include clock line(s) for timing/synchronising, interrupts, reset etc. Typically P has 10 control lines. Cannot function correctly without these vital control signals. The Control Bus carries control signals partly unidirectional, partly bi-directional. Control signals are things like "read or write". This tells memory that we are either reading from a location, specified on the address bus, or writing to a location specified. Various other signals to control and coordinate

the operation of the system. Modern day microprocessors, like 80386, 80486 have much larger busses. Typically 16 or 32 bit busses, which allow larger number of instructions, more memory location, and faster arithmetic. Microcontrollers organized along same lines, except: because microcontrollers have memory etc inside the chip, the busses may all be internal. In the microprocessor the three busses are external to the chip (except for the internal data bus). In case of external busses, the chip connects to the busses via buffers, which are simply an electronic connection between external bus and the internal data bus.

Maximum-mode interface circuit diagram (8086)

8086 Pin Diagram/Description AD15AD0 ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address and data bus. ALE Address Latch Enable. A HIGH on this line causes the lower order 16bit address bus to be latched that stores the addresses and then, the lower order 16bit of the address bus can be used as data bus. READY READY is the acknowledgement from the addressed memory or I/O device that it will complete the data transfer.

INTR INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH. INTA Interrupt Acknowledge from the MP NMI NON-MASKABLE INTERRUPT: an edge triggered input which causes an interrupt request to the MP. A subroutine is vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. RESET: causes the processor to immediately terminate its present activity. The signal must be active HIGH for at least four clock cycles. It restarts execution MN/MX MINIMUM/MAXIMUM: indicates what mode the processor is to operate in. The two modes are discussed in the following sections. M/IO : Differentiate between the Memory and I/O operation. A LOW on this pin indicated I/O operation and a HIGH indicated a Memory Operation HOLD : The 8086 has a pin called HOLD. This pin is used by external devices to gain control of the busses. HLDA : When the HOLD signal is activated by an external device, the 8086 stops executing instructions and stops using the busses. This would allow external devices to control the information on the 8086 MINIMUM AND MAXIMUM MODES of operation MN/MX Minimum mode The 8086 processor works in a single processor environment. All control signals for memory and I/O are generated by the microprocessor. Maximum mode is designed to be used when a coprocessor exists in the system. 8086 works in a multiprocessor environment. Control signals for memory and I/O are generated by an external BUS Controller.

Maximum Mode Interface The signals shown above are produced by 8288 depending on the state of S0, S1 and S2. DEN, DT/R and ALE signals are the same as minimum-mode systems LOCK: when =0, prevents other processors from using the bus QS0 and QS1 (queue status signals) : informs about the status of the queue

 RQ/GT 0 and RQ/GT 1 are used instead of HOLD and HLDA lines in a multiprocessor environment as request/grant lines. Memory Segmentation

Advantages of memory segmentation 1. Allow the memory capacity to be 1Mb even though the addresses associated with the individual instructions are only 16 bits wide. 2. Facilitate the use of separate memory areas for the program, its data and the stack. 3. Permit a program and/or its data to be put into different areas of memory each time the program is executed. 4. Multitasking becomes easy. Generation of 20 bit physical address The 20-bit Physical address is often represented as, Segment Base : Offset OR CS : IP CS 3 4 8 0 0 Implied Zero +IP 1 2 3 4 -----------------------

3 5 A3 4 H Two-part Addresses and Memory Segmentation Memory addressing is the centerpiece of the memory management function of an operating system. Early systems had flat memory models in which each byte was numbered sequentially from zero. The address of any byte in memory was in effect just the ordinal number telling "which" byte it was, e.g., the seven hundred twenty-third or the forty-three thousand two hundred ninth. Programmers referred to each byte by its sequence number in their programs. These numbers are called "absolute" or "physical" addresses. Computers later became more complicated (in order to get more powerful). One change was that within programs, programmers could refer to memory locations (particular bytes) by other numbering systems than the physical one, and the operating systems and/or CPUs would automatically translate from one to the other. Vintage 1980 microcomputers used physical addressing, and confined themselves to using 4digit hexadecimal numbers (which is the same thing as 16 bits) as addresses. The highest you can count with a 4-digit hexadecimal number is FFFF in hex, equivalent to 65535 in decimal. So no more than 65536 bytes or 64K of memory could be used. Even if you could have installed more, the computer could not have used it for lack of ability to refer to it. The IBM PC appeared in 1981 and was a fundamental redesign of the earlier microcomputer generation. The designers wanted to allow for 1MB of memory, or 16 times as much as the previous 64K limit. However for design reasons they did not wish to use numbers wider than 16 bits in their addressing system. So they overcame the limit by inventing a system of compound addresses. Each compound address contained 2 16-bit numbers, to be interpreted in a special way. These were the first "segmented addresses" in microcomputers. Coinciding with this was the appearance of a new CPU chip design with new registers to facilitate the new addressing method. (The CPU designers at Intel and the PC architects at IBM worked hand-in-glove designing each piece with the other in mind.) So what was this new addressing system, and the new way of interpreting the new-style addresses? Let me lead with an example in decimal. Forget hexadecimal, and computers, for a moment. In decimal we'll do the same thing that the 1981 PC architects did. Suppose till now we have been content to confine ourselves to counting using 2-digit numbers. Of course, that gave us the scope to count within the range from zero to ninety-nine. That has always been adequate. Ninety-nine is enough. It really has never occurred to us to count any higher. Now however, an ambitious engineer wants to do just that. He knows he can do it if he allows a third digit. That gets us beyond the 99 barrier alright, not only to 100 but all the way up to the unimaginably huge number 999. For design reasons though, the engineer chooses to avoid using 3-digit numbers. Instead he opts to invent a system of compound numbers, consisting of 2 ordinary 2-digit number and a special way of interpreting them. On the number line he will mark all numbers that are multiples of 10, starting with 0. Then he will use his first 2-digit number to identify a particular "deci-mark" on the number line. If his 2-

digit number is 00 he's talking about the mark at 0. If it's 01, the mark at 10. If it's 02, the mark at 20,..., if it's 09, the mark at 90. If it's 10, the one at 100. If it's 11, the one at 110. If it's 25, he means the mark at 250. Since his 2-digit numbers go up to 99 before they run out of gas, he now has a technique of referring, as the limit of his reach, to the point at 990 on the number line. What he has sacrificed is the ability to refer to any of the "in-between" numbers, like 11 or 19 or 255. He has diluted his 2-digit number so it goes farther. He gained scope at the expense of precision. That's the purpose of the second 2-digit number: to supply restored precision. Say he wants to refer to the number 763. He could select, as his first 2-digit number, 76. Because of the special, new "times ten" method of interpretation, we know this refers to the number 760. So he constructs a second 2-digit number to get him the rest of the way from 760 to 763. And that number is of course 3, which we'll write 03 to make it 2 digits. His notation system calls for him to write: 76:03 when he wishes to talk about 763. He now has a way to talk about it, but has successfully avoided using 3-digit numbers. Note he could land on 763 several other ways. For example, by starting at 750 instead of 760, then advancing 13 instead of 3. Just as the 43 yard line on the gridiron is equivalently a 3 yard gain from the 40, a 13 yard gain from the 30, or a 23 yard gain from the 10. All, same thing. So our engineer could write any of the following to refer to 763: 76:03 75:13 74:23 73:33 72:43 71:53 70:63 69:73 68:83 67:93 That's it. He can't let his first number go any lower than 67, because that would leave him short of 763 by more than 99, and the second number can only raise him 99 beyond his first one. You can make up the following rule for converting one of these compound addresses into a noncompound (i.e., regular 3-digit) one: to find the 3-digit linear address, take the left number of the compound address, shift it left one place (i.e., multiply it by 10), then add the right number.

The PC architects did pretty much the same thing. Instead of starting with 2-digit decimal numbers that provide a range of up-to-99, they started with 4-digit hexadecimal numbers providing a range of up-to-65536. But they compounded their numbers just the same way. And they ended up with an expanded reach. Their new reach, instead of extending up to 999 (just about a thousand), extended up to 1048575 ( just about a megabyte). But the system was the same. Consider an address 8F11:312A. The interpretation of this compound address and resulting absolute address is:

Note the above arithmetic is hexadecimal arithmetic, not decimal arithmetic. And note the result, 9223A, is much bigger than is FFFF, the previous counting ceiling. The two numbers have names. The left one is the segment address, and the right one is the offset address. Using this system to refer to memory locations is called memory segmentation. It's a way of making two 4digit (hexadecimal) numbers do the work of one 5-digit number. This was the new style of addressing by IBM's 1981 PC architects. Meanwhile, Intel's CPU designers made their own contribution. They came out with a chip (the 8086) that featured some new registers called segment registers. Programmers would work with the two-part addresses by

doing two things within their programs. When they wanted to use a certain address, they would first take the segment address half of it and write it into the segment register. Thereafter, they would forget about the segment and write only the offset addresses within their code. They could get away with leaving out an explicit segment in all their address references due to the way the CPU worked. It was designed to blend (add) with the programmer's offset addresses whatever number was sitting in the segment register. And to do it every time there was an address reference, automatically. The segment address wasn't really omitted from the code, just implicit. When you as a programmer put a number in a segment register you have in effect defined something called a "segment." This is a section of memory 64K bytes long. If the segment address is, for example, 2915, then the addresses in this segment start at 2915:0000 and go up to 2915:FFFF, which is the highest address in this particular segment. This range expressed in terms of absolute or physical addresses is from 29150 through 3914F. The relationship between a segment and the register which defines it is shown below.

The addresses appearing in program code are the offset addresses. The programmer writes FFFB. But when the program runs, it is 3914B that is affected.

Where can you put the segments in memory? Just about anywhere you want. They can occupy completely separate parts of memory, they can overlap, or two or more segments could even coincide. Because there are multiple segment registers, the CPU can keep track of, and a program can use, multiple segments at the same time. The old 8086 chip had 4 of these 16-bit segment registers: code segment, data segment, stack segment, extra segment. Once particular values are written into them, the positions of 4 64K-segments within the larger memory space are established. Three possible scenarios are shown below. But bear in mind a segment's location in memory can be changed in an instant. All it takes to shift the position of a segment is to simply put a new value into the corresponding segment register. Immediately, all explicit addresses appearing in the code (since they're offsets within the segment) map into a different set of physical addresses than they did before, by virtue of being differently complemented by the CPU.

The current Pentium chip has 6 segment registers rather than 4. And the addresses are a little different. You saw that both the segment and offset elements of the 2-part addresses discussed above are 16-bit numbers. In the Pentium, while the segment registers are 16-bit, the offsets are 32-bit numbers. Consequently the Pentium works with much larger segments. It also has a more elaborate and indirect system of translating the addresses that appear in programs into the absolute physical addresses needed at runtime. But the principles are all the same.

8255A

Features Pin Compatible with NMOS 8255A 24 Programmable I/O Pins Fully TTL Compatible High Speed, No Wait State Operation with 5MHz and 8MHz 80C86 and 80C88 Direct Bit Set/Reset Capability

Functional Description Data Bus Buffer This three-state bi-directional 8-bit buffer is used to interface the 82C55A to the system data bus. Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. Control words and status information are also transferred through the data bus buffer. Read/Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words. It accepts inputs from the CPU Address and Control busses and in turn, issues commands to both of the Control Groups. (CS) . Chip Select. A low on this input pin enables the communcation between the 82C55A and the CPU.

RD) Read. A low on this input pin enables 82C55A to send the data or status information to the CPU on the data bus. In essence, it allows the CPU to read from the 82C55A. (WR) Write. A low on this input pin enables the CPU to write data or control words into the 82C55A. (A0 and A1) Port Select 0 and Port Select 1. These input signals, in conjunction with the RD and WR inputs, control the selection of one of the three ports or the control word register. They are normally connected to the least significant bits of the address bus (A0 and A1). (RESET) Reset. A high on this input initializes the control register to 9Bh and all ports (A, B, C) are set to the input mode. Bus hold devices internal to the 82C55A will hold the I/O port inputs to a logic 1 state with a maximum hold current of 400mA. Group A and Group B Controls The functional configuration of each port is programmed by the systems software. In essence, the CPU outputs a control word to the 82C55A. The control word contains information such as mode, bit set, bit reset, etc., that initializes the functional configuration of the 82C55A. Each of the Control blocks (Group A and Group B) accepts commands from the Read/Write Control logic, receives control words from the internal data bus and issues the proper commands to its associated ports. Control Group A - Port A and Port C upper (C7 - C4) Control Group B - Port B and Port C lower (C3 - C0) The control word register can be both written and read as shown in the Basic Operation table. Figure 4 shows the control word format for both Read and Write operations. When the control word is read, bit D7 will always be a logic 1, as this implies control word mode information. 82C55A BASIC OPERATION A1 A0 RD WR CS INPUT OPERATION (READ) Port A Data Bus Port B Data Bus Port C Data Bus

0 0 1

0 1 0

0 0 0

1 1 1

0 0 0

Control Word Data Bus OUTPUT OPERATION WRITE)

0 0 1 1

0 1 0 1

1 1 1 1

0 0 0 0

0 0 0 0

Data Bus Port A Data Bus Port B Data Bus Port C Data Bus Control DISABLE FUNCTION

X X

X X

X 1

X 1

1 0

Data Bus ThreeState Data Bus ThreeState

Ports A, B, and C The 82C55A contains three 8-bit ports (A, B, and C). All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibility of the 82C55A. Port A One 8-bit data output latch/buffer and one 8-bit data input latch. Both pull-up and pull-down bus-hold devices are present on Port A. Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control. Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B.

DMA INTERFACEING

A simple schematic for interfacing the 8257 with 8085 processor is shown. The 8257 can be either memory mapped or I/O mapped in the system. In the schematic shown in figure is I/O mapped in the system. Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices. The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS0 to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.

The address line A7 and the control signal IO/M (low) are used as enable for decoder. The D0-D7 lines of 8257 are connected to data bus lines D0-D7 for data transfer with processor during programming mode.

These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15 during the DMA mode.

The 8257 also supply two control signals ADSTB and AEN to latch the address supplied by it during DMA mode on external latches.

Two 8-bit latches are provided to hold the 16-bit memory address during DMA mode. During DMA mode, the AEN signal is also used to disable the buffers and latches used for address, data and control signals of the processor.

The 8257 provide separate read and write control signals for memory and I/O devices during DMA.

Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by a suitable logic circuit to generate separate read and write control signals f memory and I/O devices.

The output clock of 8085 processor should be inverted and supplied to 8257 clock input for proper operation.

The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD request to the processor.

The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the acknowledge signal from the processor once the HOLD request is accepted.

The RESET OUT of 8085 processor is connected to RESET of 8257. The I/O addresses of the internal registers of 8257 are listed in table. Binary address Direct input and Inputs to address pins enable A7 A6 A5 A4 of 8257 A3 A2 A1 A0 Hexa address

Register

Channel 0 DMA address register Channel 0 counter register Channel 1 DMA address register Channel 1 counter register Channel 2 DMA address register Channel 2 counter register Channel 3 DMA address register Channel 3 counter register Mode set register (write only)

0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 1

0 0 0 0 1 1 1 1 0

0 0 1 1 0 0 1 1 0

0 1 0 1 0 1 0 1 0

60 61 62 63 64 65 66 67 68