Anda di halaman 1dari 10

CD4066BMS

December 1992

CMOS Quad Bilateral Switch


Description
CD4066BMS is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin for pin compatible with CD4016B, but exhibits a much lower on state resistance. In addition, the on-state resistance is relatively constant over the full input signal range. The CD4066BMS consists of four independent bilateral switches. A single control signal is required per switch. Both the p and the n device in a given switch are biased on or off simultaneously by the control signal. As shown in Figure 1, the well of the n channel device on each switch is either tied to the input when the switch is on or to VSS when the switch is off. This conguration eliminates the variation of the switch transistor threshold voltage with input signal, and thus keeps the on-state resistance low over the full operating signal range. The advantages over single channel switches include peak input signal voltage swings equal to the full supply voltage, and more constant on-state impedance over the input signal range. For sample and hold applications, however, the CD4016B is recommended. The CD4066BMS is supplied in these 14-lead outline packages:
Braze Seal DIP H4Q Frit Seal DIP H1B Ceramic Flatpack H3W

Features
For Transmission or Multiplexing of Analog or Digital Signals High Voltage Types (20V Rating) 15V Digital or 7.5V Peak-to-Peak Switching 125 Typical On-State Resistance for 15V Operation Switch On-State Resistance Matched to Within 5 Over 15V Signal Input Range On-State Resistance Flat Over Full Peak-to-Peak Signal Range High On/Off Output Voltage Ratio - 80dB Typ. at FIS = 10kHz, RL = 1k High Degree of Linearity: <0.5% Distortion Typ. at FIS = 1kHz, VIS = 5Vp-p, VDD - VSS 10V, RL = 10k Extremely Low Off-State Switch Leakage Resulting in Very Low Offset Current and High Effective Off-State Resistance: 10pA Typ. at VDD - VSS = 10V, TA = +25oC Extremely High Control Input Impedance (Control Circuit Isolated from Signal Circuit): 1012 Typ. Low Crosstalk Between Switches: -50dB Typ. at FIS = 8MHz, RL = 1k Matched Control Input to Signal Output Capacitance: Reduces Output Signal Transients Frequency Response, Switch on = 40MHz (Typ.) 100% Tested for Quiescent Current at 20V 5V, 10V and 15V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. 13B, Standard Specications for Description of B Series CMOS Devices

Pinout
CD4066BMS TOP VIEW

IN/OUT A 1 OUT/IN A 2

14 VDD 13 CONT A 12 CONT D 11 IN/OUT D 10 OUT/IN D 9 OUT/IN C 8 IN/OUT C

Applications
Analog Signal Switching/Multiplexing - Signal Gating - Modulator - Squelch Control - Demodulator - Chopper - Commutating Switch Digital Signal Switching/Multiplexing Transmission Gate Logic Implementation Analog to Digital & Digital to Analog Conversion Digital Control of Frequency, Impedance, Phase, and Analog Signal Gain

OUT/IN B 3 IN/OUT B 4 CONT B 5 CONT C 6 VSS 7

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999

File Number

3319

7-966

Specications CD4066BMS
Absolute Maximum Ratings
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case for 10s Maximum

Reliability Information
Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1 2 VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VC = VDD or GND 3 1 2 3 Input Leakage Current IIH VC = VDD or GND 1 2 3 Input/Output Leakage Current (Switch OFF) IOZL VC = 0V, VIS = 18V, VOS = 0V, VIS = 0V, VOS = 18V VDD = 20 1 2 VDD = 18V IOZH VDD = 20 3 1 2 VDD = 18V On Resistance RON5 RON10 RON15 On Resistance RON5 VC = VDD, RL = 10kW VDD = 5V returned to VDD VDD = 10V VSS/2 VDD = 15V VIS = VSS to VDD VDD = 5V 3 1 1 1 1, 2 LIMITS TEMPERATURE +25
oC

PARAMETER Supply Current

SYMBOL IDD

CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND

MIN -100 -1000 -100 -100 -1000 -100 1050 400 240 -

MAX 0.5 50 0.5 100 1000 100 100 1000 100 1300 800 550 310 320 220

UNITS A A A nA nA nA nA nA nA nA nA nA nA nA nA V

+125oC -55oC +25o C

+125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +125oC -55oC +25oC +25oC +25oC +125oC -55oC

On Resistance

RON10

VDD = 10V

1, 2

+125oC -55oC

On Resistance

RON15

VDD = 15V

1, 2

+125oC -55oC

Functional (Note 3)

VDD = 2.8V, VIN = VDD or GND VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND

7 7 8A 8B 1, 2, 3 1, 2, 3 1 1

+25oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC

VOH > VOL < VDD/2 VDD/2

Switch Threshold RL = 100k to VDD N Threshold Voltage P Threshold Voltage

SWTHRH5 VDD = 5V, VC = 1.5V, VIS = GND SWTHRH15 VDD = 15V, VC = 2V, VIS = GND VNTH VPTH VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A

4.1 14.1 -2.8 0.7

-0.7 2.8

V V V V

7-967

Specications CD4066BMS
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 LIMITS TEMPERATURE +25oC, +125oC, -55oC +25oC, +125oC, -55oC MIN MAX 1 2 UNITS V V

PARAMETER Control Input Low Voltage (Note 2) |IIS| < 10a, VIS = VSS, VOS = VDD and VIS = VDD, VOS = VSS Control Input High Voltage (Note 2, Figure 2) VIS = VSS and VIS = VDD

SYMBOL VILC5 VILC15

CONDITIONS (NOTE 1) VDD = 5V VDD = 15V

VIHC

VDD = 5V, |IIS| = .51mA, 4.6V < VOS < 0.4V VDD = 5V, |IIS| = .36mA, 4.6V < VOS < 0.4V VDD = 5V, |IIS| = .64mA, 4.6V < VOS < 0.4V

1 2 3 1 2 3

+25oC +125oC -55oC +25oC +125oC -55oC

3.5 3.5 3.5 11 11 11

V V V V V V

VIHC

VDD = 15V, |IIS| = 3.4mA, 13.5V < VOS <1.5V VDD = 15V, |IIS| = 2.4mA, 13.5V < VOS < 1.5V VDD = 15V, |IIS| = 4.2mA, 13.5V < VOS <1.5V

NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs.

3. VDD = 2.8V/3.0V, RL = 100K to VDD VDD = 20V/18V, RL = 10K to VDD

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A SUBGROUPS TEMPERATURE 9 10, 11 9 10, 11 +25oC +125oC, -55oC LIMITS MIN MAX 40 54 70 95 UNITS ns ns ns ns

PARAMETER Propagation Delay Signal Input to Signal Output Propagation Delay Turn-On, Turn-Off NOTES:

SYMBOL TPLH TPHL

CONDITIONS VC = VDD = 5V, VSS = GND (Notes 2, 3)

TPHZ/ZH VIS = VDD = 5V (Notes 1, 2) TPLZ/ZL

+25oC +125oC, -55oC

1. CL = 50pF, RL = 1K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS VDD = 5V, VIN = VDD or GND NOTES 1, 2 TEMPERATURE -55oC, +25oC MIN MAX 0.25 7.5 0.5 15 0.5 30 2 UNITS A A A A A A V

+125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC

+125oC Control Input Low Voltage |IIS| < 10a, VIS = VSS, VOS = VDD and VIS = VDD, VOS = VSS VILC10 VDD = 10V 1, 2 +25oC, +125oC, -55oC

7-968

Specications CD4066BMS
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Control Input High Voltage (See Figure 2) Propagation Delay Signal Input to Signal Output Propagation Delay Turn-On, Turn-Off Input Capacitance NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current N Threshold Voltage N Threshold Voltage Delta P Threshold Voltage P Threshold Voltage Delta Functional SYMBOL IDD VNTH VTN VTP VTP F CONDITIONS VDD = 20V, VIN = VDD or GND VDD = 10V, ISS = -10A VDD = 10V, ISS = -10A VSS = 0V, IDD = 10A VSS = 0V, IDD = 10A VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 1, 2, 3, 4 +25oC NOTES 1, 4 1, 4 1, 4 1, 4 1, 4 1 TEMPERATURE +25oC +25oC +25oC +25oC +25oC +25oC MIN -2.8 0.2 VOH > VDD/2 MAX 25 -0.2 1 2.8 1 VOL < VDD/2 1.35 x +25oC Limit UNITS A V V V V V SYMBOL VIHC10 TPLH TPHL CONDITIONS VDD = 10V, VIS = VDD or GND VDD = 10V VDD = 15V NOTES 2 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2 TEMPERATURE +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC MIN 7 MAX 20 15 40 30 7.5 UNITS V ns ns ns ns pF

TPHZ/ZH VDD = 10V TPLZ/ZL VDD = 15V CIN Any Input

ns

NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.

3. See Table 2 for +25oC limit. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current - SSI ON Resistance SYMBOL IDD RONDEL10 0.1A 20% x Pre-Test Reading DELTA LIMIT

TABLE 6. APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test 1 (Post Burn-In) Interim Test 2 (Post Burn-In) PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 GROUP A SUBGROUPS 1, 7, 9 1, 7, 9 1, 7, 9 1, 7, 9, Deltas 1, 7, 9 1, 7, 9, Deltas IDD, IOL5, IOH5A, RONDEL10 READ AND RECORD IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10 IDD, IOL5, IOH5A, RONDEL10

7-969

Specications CD4066BMS
TABLE 6. APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Final Test Group A Group B Subgroup B-5 Subgroup B-6 Group D MIL-STD-883 METHOD 100% 5004 Sample 5005 Sample 5005 Sample 5005 Sample 5005 GROUP A SUBGROUPS 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas 1, 7, 9 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3 Subgroups 1, 2, 3, 9, 10, 11 READ AND RECORD

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD 1, 7, 9 POST-IRRAD Table 4 READ AND RECORD PRE-IRRAD 1, 9 POST-IRRAD Table 4

CONFORMANCE GROUPS Group E Subgroup 2

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION Static Burn-In 1 (Note 1) Static Burn-In 2 (Note 1) Dynamic Burn-In (Note 1) Irradiation (Note 2) NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K 5%, VDD = 18V 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V 0.5V OPEN 2, 3, 9, 10 2, 3, 9, 10 2, 3, 9, 10 GROUND 1, 4-8, 11-13 7 7 7 VDD 14 1, 4-6, 8, 11-14 14 1, 4-6, 8, 11-14 2, 3, 9, 10 5, 6, 12, 13 1, 4, 8, 11 9V -0.5V 50kHz 25kHz

Functional Diagram
TRUTH TABLE EACH SWITCH
IN/OUT SIG A OUT/IN 2 1 SW A 13 CONTROL A 14 VDD

INPUT VC 1 1 VIS 0 1 0 1

OUTPUT VOS 0 1 Open Open

OUT/IN SIG B IN/OUT

SW D

12

CONTROL D

0 0

4 SW B

11

IN/OUT SIG D

CONTROL B

10

OUT/IN

Positive Logic: Switch ON VC = 1 Switch OFF VC = 0

CONTROL C

6 SW C

OUT/IN SIG C

VSS

IN/OUT

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certication.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

970

CD4066BMS Schematic
SWITCH CONTROL IN VIS NORMAL OPERATION CONTROL LINE BIASING: SWITCH ON, VC I = VDD SWITCH OFF, VC O = VSS

VDD

N P N OUT VOS

ALL CONTROL INPUTS ARE PROTECTED BY THE CMOS PROTECTION NETWORK

CONTROL VC

N VSS SIGNAL LEVEL RANGE: VSS VIS VDD NOTE: All P Substrates Connected to VDD VSS

FIGURE 1. SCHEMATIC DIAGRAM OF 1 OF 4 IDENTICAL SWITCHES AND ITS ASSOCIATED CONTROL CIRCUITRY

VDD IIS VIS CD4066BMS 1 OF 4 SWITCHES |VIS - VOS| RON = |IIS| VOS VSS TG ON

KEITHLY 160 DIGITAL MULTIMETER 1k RANGE Y X-Y PLOT TER X

10k

HP MOSELEY 7030A

FIGURE 2. DETERMINATION OF RON AS A TEST CONDITION FOR CONTROL INPUT HIGH VOLTAGE (VIHC) SPECIFICATION

FIGURE 3. CHANNEL ON-STATE RESISTANCE MEASUREMENT CIRCUIT

CIOS VC = -5V VDD = +5V MEASURED ON BOONTON CAPACITANCE BRIDGE MODEL 75A (1MHz) TEST FIXTURE CAPACITANCE NULLED OUT

VC = VSS

VDD

CD4066BMS 1 OF 4 SWITCHES CIS VSS = -5V COS

VIS = VDD

CD4066BMS 1 OF 4 SWITCHES VSS

ALL UNUSED TERMINALS ARE CONNECTED TO VSS

FIGURE 4. CAPACITANCE TEST CIRCUIT

FIGURE 5. OFF SWITCH INPUT OR OUTPUT LEAKAGE

VC = VDD

VDD

ALL UNUSED INPUTS ARE CONNECTED TO VSS VOS 50 pF

+10V tr = tf = 20ns

VC

VDD

ALL UNUSED TERMINALS ARE CONNECTED TO VSS VOS

ViS

CD4066BMS 1 OF 4 SWITCHES

VIS 200k 1k

CD4066BMS 1 OF 4 SWITCHES

VDD tr = tf = 20ns

VSS

VSS

10k

FIGURE 6. PROPAGATION DELAY TIME SIGNAL INPUT (VIS) TO SIGNAL OUTPUT (VOS)

FIGURE 7. CROSSTALK CONTROL INPUT TO SIGNAL OUTPUT

7-971

CD4066BMS
VC tr = tf = 20ns VOS 90% 20ns 1 0 10% 20ns REP RATE

VC = VDD VDD tr = tf = 20ns VDD

VDD

ALL UNUSED TERMINALS ARE CONNECTED TO VSS VOS 50 pF

+10V tr = tf = 20ns

VC

VDD = +10V

ALL UNUSED INPUTS ARE CONNECTED TO VSS

CD4066BMS 1 OF 4 SWITCHES

VIS = +10V

CD4066BMS 1 OF 4 SWITCHES

VOS = 1/2VOS AT 1kHz 50 pF

1k VSS

1k

VSS

FIGURE 8. PROPAGATION DELAY TPLH, TPHL CONTROL SIGNAL OUTPUT. DELAY IS MEASURED AT VOS LEVEL OF +10% FROM GROUND (TURN ON) OR ON-STATE OUTPUT LEVEL (TURN OFF).

FIGURE 9. MAXIMUM ALLOWABLE CONTROL INPUT REPETITION RATE

10 10 CLOCK RESET 14 15 1 Q1 Q2 5 4 1
1/ 4

3 J2

7 J3

12

3 J2

7 J3

12 CLOCK 14 15 1 CD4066B 2 Q1 Q2 5 4 PE J1 J4 J5 EXT RESET

PE J1

J4 J5 13

CD4018B

CD4018B

1 3 2 3
1/ 3 CD4049B

7
1/ 3

6 CD4049B 10

13

12

5 4 6

CD4001B

CD4001B 8 10 9 12 11 13 6 5 13 12 11 2 CD4066B 3 9 4 10 10K


1/ CD4066B 4 1/ CD4049B 6

11

10

11

SIGNALS OUTPUTS LPF CHANNEL 1

SIGNALS INPUTS

12 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 1 4 8 11

12

2 10K 1 4 3 8 11 9 CD4066B 3 10K

LPF

CHANNEL 2

PACKAGE COUNT 2 - CD4001B 1 - CD4049B 3 - CD4066BMS 2 - CD4018B

LPF

CHANNEL 3

CLOCK MAX. ALLOWABLE SIGNAL LEVEL CHAN. 1 CHAN. 2 CHAN. 3 CHAN. 4

VDD 30% (VDD - VSS) VSS

10K CHANNEL 4

10 10K

LPF

FIGURE 10. 4 CHANNEL PAM MULTIPLEX SYSTEM DIAGRAM

7-972

CD4066BMS
+5 ANALOG INPUTS (5V) -5 VDD = 5V CD4066BMS 5V 0 SWB IN CD4054B SWC SWD DIGITAL CONTROL INPUTS VSS = 0V VEE = -5V SWA VDD = +5V

ANALOG OUTPUTS (5V)

VSS = -5V

FIGURE 11. BIDIRECTIONAL SIGNAL TRANSMISSION VIA DIGITAL CONTROL LOGIC

Typical Performance Characteristics


CHANNEL ON-STATE RESISTANCE (RON) () CHANNEL ON-STATE RESISTANCE (RON) () SUPPLY VOLTAGE (VDD - VEE) = 5V 600 500 400 300 200 100 0 -4 -3 -2 -1 0 1 2 3 4 INPUT SIGNAL VOLTAGE (VIS) (V) +25oC -55oC AMBIENT TEMPERATURE (TA) = +125oC SUPPLY VOLTAGE (VDD - VEE) = 10V 300 250 200 150 100 50 0 -10.0 -7.5 +25oC -55oC AMBIENT TEMPERATURE (TA) = +125oC

-5.0

-2.5

2.5

5.0

7.5

10.0

INPUT SIGNAL VOLTAGE (VIS) (V)

FIGURE 12. TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)
CHANNEL ON-STATE RESISTANCE (RON) ()

FIGURE 13. TYPICAL ON-STATE vs INPUT SIGNAL VOLTAGE (ALL TYPES).


CHANNEL ON-STATE RESISTANCE (RON) ()

SUPPLY VOLTAGE (VDD - VSS) = 15V 300 250 200 150 100 50 0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V)

600 500 400 300 200

AMBIENT TEMPERATURE (TA) = +25oC SUPPLY VOLTAGE (VDD - VSS) = 5V

AMBIENT TEMPERATURE (TA) = +125oC

+25oC -55oC

10V 100 0 -10.0 -7.5 -5.0 -2.5 0 2.5 5.0 7.5 10.0 INPUT SIGNAL VOLTAGE (VIS) (V) 15V

FIGURE 14. TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

FIGURE 15. ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES)

7-973

CD4066BMS Typical Performance Characteristics


3 OUTPUT VOLTAGE (VO) (V) 2 1 0 -1 VC = VDD AMBIENT TEMPERATURE (TA) = +25oC VDD = 2.5V, VSS = -2.5V INPUT = TERM 1, OUTPUT = TERM 2 RL = 100K

(Continued)
POWER DISSIPATION PER PACKAGE (PD) (W) 104
8 6 4 2

AMBIENT TEMPERATURE (TA) = +25oC

10K 1K 500 100 VDD

SUPPLY VOLTAGE (VDD) = 15V

103 8
6 4

10V VDD 14 5V f 5 6 12 13 7 VSS


2 4 6 8 2 4 6 8

100 500

VIS CD4066BMS VOS 1 OF 4 SWITCHES RL ALL UNUSED TERMINALS VSS ARE CONNECTED TO VSS -1 0 1 2 3 4

102

8 6 4 2

CD4066/ BMS

-2 1K 10K -3 -3 100K -2

10 10 102 SWITCHING FREQUENCY (f) (kHz)

INPUT VOLTAGE (VI) (V)

103

FIGURE 16. TYPICAL ON CHARACTERISTICS FOR 1 OF 4 CHANNELS

FIGURE 17. POWER DISSIPATION PER PACKAGE vs SWITCHING FREQUENCY

Chip Dimensions and Pad Layout

Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch).

Special Considerations In applications that employ separate power sources to drive VDD and the signal inputs, the VDD current capability should exceed VDD/RL (RL = effective external load of the four CD4066B bilateral switches). This provision avoids any permanent current ow or clamp action on the VDD supply when power is applied or removed from the CD4066B. In certain applications, the external load-resistor current may include both VDD and signal line components. To avoid drawing VDD current when switch current ows into terminals 1, 4, 8 or 11 the voltage drop across the bidirectional switch must not exceed 0.8 volts (calculated from RON values shown). No VDD current will ow through RL if the switch current ows into terminals 2, 3, 9, or 10. METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11k 14k,

AL.

10.4k - 15.6k, Silane 0.004 inches X 0.004 inches MIN

DIE THICKNESS: 0.0198 inches - 0.0218 inches

7-974

This datasheet has been downloaded from: www.DatasheetCatalog.com Datasheets for electronic components.