ISSCC 2010, Session 13.1 M.H. Perrott, S. Pamarti1, E. Hoffman2, F.S. Lee, S. Mukherjee, C. Lee, V. Tsinker3, S. Perumal4, B. Soto5, N. Arumugam, B.W. Garlepp
SiTime Corporation, Sunnyvale, CA, USA 1 UCLA, Los Angeles, CA, USA 2 Global Foundries, Sunnyvale, CA, USA 3 Invensense, Sunnyvale, CA, USA 4 Consultant 5 SLAC National Accelerator Laboratory, Palo Alto, CA USA
source: www.ecliptek.com
- Non-typical frequencies
require long lead times
5 MHz Oscillator Sustaining Circuit and Charge Pump MEMS Resonator Digital Frequency Setting
1 to 115 MHz
Continuously Programmable
Fractional-N synthesizer multiplies 5 MHz MEMS reference to a programmable range of 750 to 900 MHz Programmable frequency divider enables 1 to 115 MHz output
Oscillator Sustaining Circuit and Charge Pump MEMS Resonator Temperature Sensor Digital Logic Digital Frequency Setting
Fractional-N Synthesizer
High resolution control of fractional-N synthesizer allows simple method of compensating for MEMS frequency variation with temperature
Oscillator Sustaining Circuit and Charge Pump MEMS Resonator Temperature Sensor Digital Logic Digital Frequency Setting
Fractional-N Synthesizer
How do we achieve a fractional-N synthesizer with low area, low power, and low design complexity?
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up(t) vtune(t)
ref(t)
R1
down(t)
C1
C2
Divider
Digital PLL
out(t)
Analog PLL wins in 0.18u CMOS for low power Can we achieve a low area (and low power) analog PLL with reduced design effort?
ref(t)
1 D Q reset
Inoise
vtune(t)
div(t)
1 D Q
Reg
R1
down(t)
C1
C2
Divider
Loop filter noise (primarily from charge pump) often dominates PLL phase noise at low offset frequencies We will show that
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- The common approach of reducing loop filter noise leads to increased loop filter area (i.e., C for charge pump PLL) - We can instead increase PD gain to lower the impact of
loop filter noise Loop filter area can be smaller
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ref(t)
1 D Q reset
Inoise
vtune(t)
div(t)
1 D Q
Reg
R1
down(t)
C1
C2
Divider
error(t) ref(t)
PFD PD Gain
div(t)
VCO 2 Kv s
out(t)
2 Inoise
2 Ipump
1 Ipump
VCO 2 Kv s
LFnoise
ref(t)
VCO Noise f
div(t)
PFD PD Gain
div(t)
VCO 2 Kv s
out(t)
Area gets larger since C2 is typically increased as well to maintain desired open loop gain
1 Ipump
ref(t)
PFD PD Gain
LFnoise
div(t)
Divider 1 N nom
VCO 2 Kv s
out(t)
VCO Noise f
LFnoise
N nom PD Gain
1 PD Gain
Loop filter area does not need to become larger But how do we increase the PD gain?
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Up(t)
Ref(t)
Down(t)
2
Ref(t) Div(t) Up(t) Down(t)
avg{Up(t)-Down(t)} 1 -2 PD Gain = 1 2 2
-1
error
- Note that tristate PFD has a phase error range of 2 Ref periods
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2
Ref(t) Div(t) Up(t) Down(t)
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avg{Vc1(t)} 1 -2 /8 PD Gain = 8 2 2 /8
-1
error
Up(t)
1
R1
Ref(t)
High Gain PD
Down(t)
Div(t)
C1
Vc1(t)
-1
Achieves full voltage range at Vc1 as phase error is swept across the reduced phase detector range Note: instead of being influenced by charge pump gain after the PD, we are influenced by (regulated) supply voltage
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Tref
Div_4x(t) Up(t) Down(t)
avg{Up(t) - Down(t)} 1
error
Tdiv
Last(t)
Tref
Div_4x(t) Up(t) Down(t) Mid(t) Last(t)
avg{Up(t) - Down(t)} 1
error
Tdiv
PD Gain
Supply Gain
Vdd
RC Network
8 2
PD Gain
2
Charge Pump
1 1+sR1_effC1
Integration Cap
div(t)
Ipump
2 2
Ipump
1 sC2
Ipump
H(w)
wz
Can we remove the charge pump to reduce the analog design effort?
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R3 Vtune(t)
C3
Capacitive feedforward path provides stabilizing zero Design effort is simply choosing switch sizes and RC values
wz
R3 Vtune(t)
C3
Ripple from Up/Down pulses passes through to VCO tuning input Is there an easy way to reduce reference spurs?
Vtune(t)
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C3
- Average current through resistance is reduced according to ratio of On time, T , versus pulsing Period, T - Effective resistance is actual resistance multiplied by ratio
period
Tperiod/Ton
Resistor multiplication allows a large RC time constant to be implemented with smaller area
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Tperiod Pulse_On(t) R/4 Cp Cp R/4 Cp R/4 Cp R/4 Cp Cp R_eff < Tperiod R Ton
- Leads to non-zero current through resistor during pulse Off time - Effective resistance reduced
Spice simulation and measured results reveal that >10X resistor multiplication can easily be achieved
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For robust stability, PLL zero should be set well below PLL bandwidth of 30 kHz
z f
1 wz = H(w)
1 R3_eff Cf Cf Cf +C3 w
- Assume desired w = 4 kHz - Set C = 2.5pF (for low area) - Required R = 16 MegaOhms
3_eff
Large area
wz
Proper choice of Ton and Tperiod allows R3_eff = 16 MegaOhms to be achieved with R3 = 500 kOhms!
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During initial frequency acquisition, Vtune(t) must be charged to proper bias point
3_eff
= 16 MegaOhms
Vdd Gnd
C3 Cc
Counter
Ref(t) Div_4x(t)
Count
Charge Low(t)
Tdiv_4x Tref
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External supply
- 1.8/3.3V
-140 dBc/Hz
Suitable for most serial applications, embedded systems and FPGAs, audio, USB 1.1 and 2.0, cameras, TVs, etc.
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40 30 20 10 0 10 20 30 40 50 50
1013 Parts
0 50 Temperature (degC)
100
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Conclusion
A MEMS-based programmable oscillator provides an efficient solution for industrial clocking needs
- Programmability of frequency value simplifies supply chain and inventory management - Leveraging of semiconductor processing, rather than
custom tools for quartz, allows low cost and low lead times
Proposed fractional-N synthesizer allows low area, low power, and reduced analog design effort
- High gain phase detector lowers impact of loop filter noise - Switched resistor technique eliminates the charge pump and reduces area through resistor multiplication - Switched capacitor frequency detection enables reasonable
frequency acquisition time with no noise penalty
Frequency references have entered the realm of integrated circuit design and manufacturing
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Supplemental Slides
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4kTR2_eff
4kTR3_eff R3_eff
ref(t)
8 2
R2_eff C1 C2 Cf
Vtune
C3
div(t)
Assumption: switched resistor time constants are much longer than on time of switches
Note: if switched resistor time constants are shorter than on time of switches
eff
- Resistors contribute kT/C noise instead of 4kTR - We would not want to operate switched resistor filter in
this domain since time constants would not be boosted
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Div_4x(t)
Nonlinearity is caused by
- Exponential response of RC filter to pulse width modulation Variation of Thold due to Sigma-Delta dithering of divide value
Note: to avoid additional nonlinearity, design divide value control logic to keep Ton a constant value
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Div_4x(t)
- If T/(R C ) is small:
1 1
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Div_4x(t)
Hold time nonlinearity is reduced as changes in Thold (due to divide value dithering) are reduced
Benefits are offset by reduced noise shaping of lower order Sigma-Delta Reduce step size of MASH Achieved with higher VCO frequency
Vc1
Vc1[k-1]
Vc1[k]
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Folded quantization noise due to nonlinearity is reasonably below other noise sources for this design
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Down(t)
Div(t)
2
Ref(t) Div_4x(t) Up(t) Down(t)
avg{Up(t)-Down(t)} 1 -2 2 PD Gain = 2 2
-1
error
- Reduced phase error range and max/min current occurs - Similar to XOR PD, but noise is reduced
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