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A Low Area, Switched-Resistor Loop Filter Technique for Fractional-N Synthesizers Applied to a MEMS-based Programmable Oscillator

ISSCC 2010, Session 13.1 M.H. Perrott, S. Pamarti1, E. Hoffman2, F.S. Lee, S. Mukherjee, C. Lee, V. Tsinker3, S. Perumal4, B. Soto5, N. Arumugam, B.W. Garlepp
SiTime Corporation, Sunnyvale, CA, USA 1 UCLA, Los Angeles, CA, USA 2 Global Foundries, Sunnyvale, CA, USA 3 Invensense, Sunnyvale, CA, USA 4 Consultant 5 SLAC National Accelerator Laboratory, Palo Alto, CA USA

Why Switch to MEMS-based Programmable Oscillators?


Quartz Oscillators MEMS-based Oscillator

source: www.ecliptek.com

A part for each frequency and non-plastic packaging

- Non-typical frequencies
require long lead times

Same part for all frequencies and plastic packaging


without extra lead time

- Pick any frequency you want


2

We can achieve high volumes at low cost using IC fabrication

Architecture of MEMS-Based Programmable Oscillator

5 MHz Oscillator Sustaining Circuit and Charge Pump MEMS Resonator Digital Frequency Setting

750-900 MHz Fractional-N Synthesizer

1 to 115 MHz

Programmable Frequency Divider

Continuously Programmable

MEMS device provides high Q resonance at 5 MHz

- CMOS circuits provide DC bias and sustaining amplifier

Fractional-N synthesizer multiplies 5 MHz MEMS reference to a programmable range of 750 to 900 MHz Programmable frequency divider enables 1 to 115 MHz output

Compensation of Temperature Variation


Freq Error (ppm) Temp 5 MHz 750-900 MHz Programmable Frequency Divider Freq Error (ppm) Temp

Oscillator Sustaining Circuit and Charge Pump MEMS Resonator Temperature Sensor Digital Logic Digital Frequency Setting

Fractional-N Synthesizer

Freq Compensation (ppm) Temp

Continuously Programmable 1 to 115 MHz

High resolution control of fractional-N synthesizer allows simple method of compensating for MEMS frequency variation with temperature

- Simply add temperature sensor and digital compensation logic

The Focus of This Talk


Freq Error (ppm) Temp 5 MHz 750-900 MHz Programmable Frequency Divider Freq Error (ppm) Temp

Oscillator Sustaining Circuit and Charge Pump MEMS Resonator Temperature Sensor Digital Logic Digital Frequency Setting

Fractional-N Synthesizer

Freq Compensation (ppm) Temp

Continuously Programmable 1 to 115 MHz

How do we achieve a fractional-N synthesizer with low area, low power, and low design complexity?
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Analog Versus Digital Fractional-N Synthesizer?


1 D Q reset div(t) 1 D Q
Reg

up(t) vtune(t)

Analog PLL + Low power - Large loop filter (Dominated by C2)

ref(t)

R1
down(t)

C1

C2
Divider

Digital PLL

+ Smaller loop filter - Difficult in 0.18 CMOS (Higher power)

ref(t) Time-to-Digital Converter div(t)

Digital Loop Filter DCO Divider

out(t)

Analog PLL wins in 0.18u CMOS for low power Can we achieve a low area (and low power) analog PLL with reduced design effort?

The Issue of Area: What Causes a Large Loop Filter?


up(t)

ref(t)

1 D Q reset

Inoise
vtune(t)

Output Phase Noise


Charge Pump Noise VCO Noise f

div(t)

1 D Q
Reg

R1
down(t)

C1

C2
Divider

Loop filter noise (primarily from charge pump) often dominates PLL phase noise at low offset frequencies We will show that
2

- The common approach of reducing loop filter noise leads to increased loop filter area (i.e., C for charge pump PLL) - We can instead increase PD gain to lower the impact of
loop filter noise Loop filter area can be smaller
7

First Step: Model PLL with Charge Pump Noise


up(t)

ref(t)

1 D Q reset

Inoise
vtune(t)

Output Phase Noise


Charge Pump Noise VCO Noise f

div(t)

1 D Q
Reg

R1
down(t)

C1

C2
Divider

error(t) ref(t)

PFD PD Gain

div(t)

RC Charge Inoise Network Pump Z(s) Ipump C2 Divider 1 N nom

VCO 2 Kv s

out(t)

Increasing Ipump Reduces Input-Referred Loop Filter Noise


LFnoise 2 1 Ipump
PFD PD Gain Divider 1 N nom
error(t) ref(t)

2 Inoise

2 Ipump

1 Ipump
VCO 2 Kv s

Output Phase Noise


Loop Filter Noise
out(t)

LFnoise

ref(t)

Loop Filter Ipump Z(s) C2

VCO Noise f

div(t)

PFD PD Gain

div(t)

RC Charge Inoise Network Pump Z(s) Ipump C2 Divider 1 N nom

VCO 2 Kv s

out(t)

Area gets larger since C2 is typically increased as well to maintain desired open loop gain

Increasing PD Gain Reduces Impact of Loop Filter Noise


PD Gain
Output Phase Noise
Loop Filter Noise

1 Ipump
ref(t)

PFD PD Gain

LFnoise

div(t)

Divider 1 N nom

Loop Filter Ipump Z(s) C2

VCO 2 Kv s

out(t)

VCO Noise f

Impact of Loop Filter Noise on Output


PD Gain Ipump PD Gain

Keep Open Loop Gain Constant

LFnoise

N nom PD Gain

1 PD Gain

Loop filter area does not need to become larger But how do we increase the PD gain?
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PD Gain of Classical Tristate PFD


1 D Q reset Div(t) 1 D Q
Reg

Up(t)

Ipump RC Network Ipump


Phase Detector Characteristic

Ref(t)

Down(t)

2
Ref(t) Div(t) Up(t) Down(t)

avg{Up(t)-Down(t)} 1 -2 PD Gain = 1 2 2
-1
error

Compute gain by averaging Up/Down pulses vs. phase error

- Note that tristate PFD has a phase error range of 2 Ref periods

11

Proposed Method of Increasing Phase Detector Gain


2
Ref(t) Div_4x(t) Up(t) Down(t)

avg{Up(t) - Down(t)} 1 -2 /8 PD Gain = 8 2 2 /8


-1
error

2
Ref(t) Div(t) Up(t) Down(t)

avg{Up(t) - Down(t)} 1 -2 PD Gain = 1 2 2


-1
error

Reduce phase detection range to 1/4 of the Ref period

- Achieves 8X increase in phase detector gain

How do we capitalize on this reduced range in the filter?

12

Simple RC Network Can Be Utilized


2
Ref(t) Div_4x(t) Up(t) Down(t)

avg{Vc1(t)} 1 -2 /8 PD Gain = 8 2 2 /8
-1
error

Up(t)

1
R1

See also: Hedayati, Bakkaloglu RFIC 2009

Ref(t)

High Gain PD

Down(t)

Div(t)

C1

Vc1(t)

-1

Achieves full voltage range at Vc1 as phase error is swept across the reduced phase detector range Note: instead of being influenced by charge pump gain after the PD, we are influenced by (regulated) supply voltage

13

Implementation of High Gain Phase Detector


Delay Buffer For Non-Overlapping Up/Down Pulses
Down(t) Up(t)
D Q Q D Q Q D Q Q D Q Q D Q Q

Ref(t) Div_4x(t) Ref(t)

Phase Detector Characteristic

Tref
Div_4x(t) Up(t) Down(t)

avg{Up(t) - Down(t)} 1
error

Tdiv

Use 4X higher divider frequency

- Simple digital implementation

-1 Tdiv 2 Tref 1 Tref 8 PD Gain = 2 = 2 Tdiv 2


14

Multi-Phase Pulse Generation (Well Use it Later)


Mid(t) Down(t) Up(t)
D Q Q D Q Q D Q Q D Q Q D Q Q

Ref(t) Div_4x(t) Ref(t)

Short Pulse Generator

Last(t)

Phase Detector Characteristic

Tref
Div_4x(t) Up(t) Down(t) Mid(t) Last(t)

avg{Up(t) - Down(t)} 1
error

Tdiv

-1 Tdiv 2 Tref 1 Tref 8 PD Gain = 2 = 2 Tdiv 2


15

Overall Loop Filter Consider Using Charge Pump


Ref(t) Up(t) Vdd Vtune(t) (Low Kv) R1 C1 Gnd
ref(t)

PD Gain

Supply Gain
Vdd

RC Network

High Gain Div_4x(t) PD Down(t)

8 2
PD Gain

2
Charge Pump

1 1+sR1_effC1
Integration Cap

div(t)

See also: Craninckx, JSSC, Dec 1998

Ipump

Vtune(t) (High Kv) C2

2 2

Ipump

1 sC2

Ipump

H(w)

We can use the high gain PD in a dual-path loop filter topology

- But we want a simple design!

wz

Can we remove the charge pump to reduce the analog design effort?

16

Passive RC Network Offers a Simpler Implementation


Regulated Vdd Ref(t) Div_4x(t) High Gain Phase Detector Up(t) R1 Down(t) Vc1(t) Gnd Ref(t) Div_4x(t) Up(t) Down(t) C1 C2 R2 Cf

R3 Vtune(t)

C3

DC Gain = 1 H(w) Cf Cf +C3 w


17

Capacitive feedforward path provides stabilizing zero Design effort is simply choosing switch sizes and RC values

wz

The Issue of Reference Spurs


Regulated Vdd Ref(t) Div_4x(t) High Gain Phase Detector Up(t) R1 Down(t) Vc1(t) Gnd Ref(t) Div_4x(t) Up(t) Down(t) Vc1(t) C1 C2 R2 Cf

R3 Vtune(t)

C3

Ripple from Up/Down pulses passes through to VCO tuning input Is there an easy way to reduce reference spurs?

Vtune(t)
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Leverage Multi-Phase Pulsing


Last(t) Mid(t) Regulated Vdd Ref(t) Div_4x(t) High Gain Phase Detector Up(t) R1 Down(t) Vc1(t) Gnd Ref(t) Div_4x(t) Up(t) Down(t) Vc1(t) Mid(t) Last(t) Vtune(t) C1 C2 R2/2 R2/2 Cf R3/2 R3/2 Vtune(t)

C3

Ripple from Up/Down pulses blocked before reaching VCO

- Reference spurs reduced! - Similar to sample-and-hold

technique (such as Zhang et. al., JSSC, 2003)

There is a nice side benefit to pulsing resistors


19

Pulsing Resistor Multiplies Resistance!


Ton

Tperiod Pulse_On(t) R/2 R/2 R_eff Tperiod = R Ton

Resistor only passes current when pulsed on


on

- Average current through resistance is reduced according to ratio of On time, T , versus pulsing Period, T - Effective resistance is actual resistance multiplied by ratio
period

Tperiod/Ton

Resistor multiplication allows a large RC time constant to be implemented with smaller area
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Parasitic Capacitance Reduces Effective Resistance


Ton

Tperiod Pulse_On(t) R/4 Cp Cp R/4 Cp R/4 Cp R/4 Cp Cp R_eff < Tperiod R Ton

Parasitic capacitance stores charge during the pulse On time

- Leads to non-zero current through resistor during pulse Off time - Effective resistance reduced
Spice simulation and measured results reveal that >10X resistor multiplication can easily be achieved
21

Switched Resistor Achieves PLL Zero with Low Area


Last(t) Regulated Vdd Up(t) R1 Down(t) Vc1(t) Gnd C1 C2 R2/2 R2/2 Vtune(t) Cf C3 Mid(t) R3/2 R3/2 Ton Tperiod

For robust stability, PLL zero should be set well below PLL bandwidth of 30 kHz
z f

1 wz = H(w)

1 R3_eff Cf Cf Cf +C3 w

- Assume desired w = 4 kHz - Set C = 2.5pF (for low area) - Required R = 16 MegaOhms
3_eff

Large area

wz

Proper choice of Ton and Tperiod allows R3_eff = 16 MegaOhms to be achieved with R3 = 500 kOhms!

22

The Issue of Initial Frequency Acquisition


Regulated Vdd Up(t) R1 Down(t) Vc1(t) Gnd C1 C2 R2/2 R3_eff = 16MegaOhms R2/2 Vtune(t) Cf C3 = 35pF

During initial frequency acquisition, Vtune(t) must be charged to proper bias point

- This takes too long with R

3_eff

= 16 MegaOhms

How do we quickly charge capacitor C3 during initial frequency acquisition?


23

Utilize Switched Capacitor Charging Technique


Regulated Vdd Up(t) R1 Down(t) Vc1(t) Gnd C1 C2 R2/2 R2/2 Cf R3/2 R3/2 Vtune(t)

Vdd Gnd

C3 Cc

Counter
Ref(t) Div_4x(t)

Count > 4 Count < 4

Charge Low Charge High Connect


Ref(t)

Count

Charge Low(t)

Tdiv_4x Tref

Charge High(t) Connect(t)

Charge C3 high or low only when frequency error is detected

- No steady-state noise penalty, minimal power consumption

24

CppSim Behavioral Simulation of Frequency Locking


1 0.5 0 1 charge_high 0 1 charge_low 0 0 10 20 30 40 Time (microseconds) 50 60 vtune

Switched capacitor technique allows relatively fast frequency locking

25

CMOS and MEMS Die Photos Show Low Area of PLL


Active area:

- VCO & buffer & bias: 0.25mm - PLL (PFD, Loop


2

Filter, divider): 0.09 mm2 Output divider: 0.02 mm2

External supply

- 1.8/3.3V

Current (20 MHz output, no load)

- ALL: 3.2/3.7mA - VCO: 1.3mA - PLL & Output


Divider: 0.7mA
26

Measured Phase Noise (100 MHz output)

Ref. Spur: -65 dBc


-90 dBc/Hz

-140 dBc/Hz

Integrated Phase Noise: 17 ps (rms) from 1 kHz to 40 MHz


100 Hz 30 kHz 40 MHz

Suitable for most serial applications, embedded systems and FPGAs, audio, USB 1.1 and 2.0, cameras, TVs, etc.

27

Frequency Variation After Single-Temperature Calibration


50

Frequency Variation (PPM)

40 30 20 10 0 10 20 30 40 50 50

1013 Parts

0 50 Temperature (degC)

100

< 30 ppm across industrial temperature range with single-temperature calibration

28

Conclusion
A MEMS-based programmable oscillator provides an efficient solution for industrial clocking needs

- Programmability of frequency value simplifies supply chain and inventory management - Leveraging of semiconductor processing, rather than
custom tools for quartz, allows low cost and low lead times

Proposed fractional-N synthesizer allows low area, low power, and reduced analog design effort

- High gain phase detector lowers impact of loop filter noise - Switched resistor technique eliminates the charge pump and reduces area through resistor multiplication - Switched capacitor frequency detection enables reasonable
frequency acquisition time with no noise penalty

Frequency references have entered the realm of integrated circuit design and manufacturing
29

Supplemental Slides

30

Noise Analysis (Ignore Parasitic Capacitance of Resistors)


PD Gain Supply 4kTR1_eff Gain R1_eff Vdd 2
Voltage Signal

4kTR2_eff

4kTR3_eff R3_eff

ref(t)

8 2

R2_eff C1 C2 Cf

Vtune

C3

div(t)

Assumption: switched resistor time constants are much longer than on time of switches

- Single-sided voltage noise contributed by each resistor


is simply modeled as 4kTReff (same as for a resistor of the equivalent value)

Note: if switched resistor time constants are shorter than on time of switches
eff

- Resistors contribute kT/C noise instead of 4kTR - We would not want to operate switched resistor filter in
this domain since time constants would not be boosted
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Issue: Nonlinearity in Switched Resistor Loop Filter


Ref(t) Phase Detector & Pulse Gen Vdd Up R1 Down Vc1 Gnd Ref(t) Div_4x(t) Up Down Ton Thold Tperiod Vc1 Vc1[k-1] Vc1[k] Vc1[k+1] C1 R2/2

Div_4x(t)

Nonlinearity is caused by

- Exponential response of RC filter to pulse width modulation Variation of Thold due to Sigma-Delta dithering of divide value

Note: to avoid additional nonlinearity, design divide value control logic to keep Ton a constant value

32

Nonlinearity Due to Pulse Width Modulation


Ref(t) Phase Detector & Pulse Gen Vdd Up R1 Down Vc1 Gnd Ref(t) Div_4x(t) Up Down Thold Ton Ton/2+T Vc1 Vc1[k-1] Ton/2-T Vc1[k] C1 R2/2

Div_4x(t)

Pulse width modulation nonlinearity is reduced as ratio T/(R1C1) is reduced

- If T/(R C ) is small:
1 1

Keep Ton constant to avoid increased nonlinearity!

33

Nonlinearity Due to Hold Time Variation


Ref(t) Phase Detector & Pulse Gen Vdd Up R1 Down Vc1 Gnd Ref(t) Div_4x(t) Up Down Thold Ton C1 R2/2

Div_4x(t)

Hold time nonlinearity is reduced as changes in Thold (due to divide value dithering) are reduced
Benefits are offset by reduced noise shaping of lower order Sigma-Delta Reduce step size of MASH Achieved with higher VCO frequency

- Reduce order of MASH -

Vc1

Vc1[k-1]

Vc1[k]

34

Nonlinearity Is Not An Issue For This Design

Other PLL Noise Sources Folded Sigma-Delta Quant Noise

Phase noise referred to VCO carrier frequency

Folded quantization noise due to nonlinearity is reasonably below other noise sources for this design

- However, could be an issue for a wide bandwidth PLL design

Use (CppSim) behavioral simulation to evaluate this issue

35

What If We Use A Pure Charge Pump Loop Filter?


Up(t) Ref(t)
High Gain PD

Ipump RC Network Ipump

Down(t)

Div(t)

2
Ref(t) Div_4x(t) Up(t) Down(t)

Phase Detector Characteristic

avg{Up(t)-Down(t)} 1 -2 2 PD Gain = 2 2
-1
error

PD Gain increased by 2 compared to tristate PFD

- Reduced phase error range and max/min current occurs - Similar to XOR PD, but noise is reduced
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High linearity despite charge pump current mismatch

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