Duke University
Digital Clock
ECE 261 Final Project Report
Fangming Ye Bhawana Singh
December 3, 2009
Copyright reserved
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Table of content
1 Introduction ................................................................................................................................... 4 1.1 1.2 1.3 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 3 3.1 3.2 3.3 4 Project Function .................................................................................................................... 4 Performance Estimation ....................................................................................................... 6 System Power Consumption ................................................................................................ 7 D-flipflop ................................................................................................................................ 7 JK-flipflop .............................................................................................................................. 9 JK-flipflop with reset function .............................................................................................. 11 0-5 counter .......................................................................................................................... 13 0-9 counter .......................................................................................................................... 15 0-9 counter with reset function ........................................................................................... 18 4-7 segment decoder .......................................................................................................... 20 Logic implementation .......................................................................................................... 23 Layout ................................................................................................................................. 26 Simulation ........................................................................................................................... 27
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List of Figures
Figure 1-1 system block diagram ......................................................................................................... 5 Figure 1-2 System Layout Floor Plan ................................................................................................... 6 Figure 2-1 schematic of D-flipflop ......................................................................................................... 8 Figure 2-2 layout of D-flipflop ............................................................................................................... 8 Figure 2-3 ELDO simulation of D-flipflop .............................................................................................. 9 Figure 2-4 schematic of JK-flipflop ..................................................................................................... 10 Figure 2-5 layout of JK-flipflop ............................................................................................................ 10 Figure 2-6 ELDO simulation of JK-flipflop .......................................................................................... 11 Figure 2-7 schematic of JK-flipflop with reset function ....................................................................... 12 Figure 2-8 layout of JK-flipflop with reset function.............................................................................. 12 Figure 2-9 ELDO simulation of JK-flipflop with reset function ............................................................ 13 Figure 2-10 schematic of 0-5 counter ................................................................................................. 14 Figure 2-11 layout of 0-5 counter ....................................................................................................... 14 Figure 2-12 ELDO simulation of 0-5 counter ...................................................................................... 15 Figure 2-13 schematic of 0-9 counter ................................................................................................. 16 Figure 2-14 layout of 0-9 counter ....................................................................................................... 17 Figure 2-15 ELDO simulation of 0-9 counter ...................................................................................... 18 Figure 2-16 schematic of 0-9 counter with reset function................................................................... 19 Figure 2-17 layout of 0-9 counter with reset function ......................................................................... 19 Figure 2-18 ELDO simulation of 0-9 counter with reset function ........................................................ 20 Figure 2-19numerical designation and display ................................................................................... 20 Figure 2-20 7 segment identification .................................................................................................. 20 Figure 2-21 schematic of 4-7 segment decoder ................................................................................. 22 Figure 2-22 layout of 4-7 segment decoder ....................................................................................... 22 Figure 2-23 ModelSIM simulation of 4-7 segment decoder ............................................................... 23 Figure 3-1 flow chart of full system ..................................................................................................... 24 Figure 3-2 top view schematic ............................................................................................................ 25 Figure 3-3 top view layout .................................................................................................................. 26 Figure 3-4 topview layout DRC clean ................................................................................................. 27 Figure 3-5 topview layout LVS clean .................................................................................................. 27 Figure 3-6 top view simulation (part I) ................................................................................................ 28 Figure 3-7 top view simulation (part II) ............................................................................................... 29 Figure 3-8 top view simulation (part III) .............................................................................................. 30
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Introduction
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Blocks in Top view Inverter NAND2 D flipflop Resettable JK flipflop 0-5 Counter 0-9 Counter Resettable 0-9 Counter 4-7 Decoder
Area of sub-block (m2) 262.5 350 2450 6750 14700 19240 44000 15600
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ECE261 CMOS VLSI Design Final Project Report From this, we have calculated the total number of transistors and total area asTotal number of transistors: 1238 Total area: 195650 m2
2.1 D-flipflop
We use D-flipflops in the main digital block connection, in order to create a delay to match the time flow. While D-flipflop is a common block in design, we briefly introduce the function of D-flipflop. The Q output always takes on the state of the D input at the moment of a rising clock edge (or falling edge if the clock input is active low). It is called the D flip-flop for this reason, since the output takes the value of the D input or Data input, and Delays it by one clock count. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise.
Clock Rising edge Rising edge Non-Rising D 0 1 X Q 0 1 Qprev Qprev X X
The schematic and layout of D-flipflop are shown in Figure 2-1 schematic of D-flipflop and Figure 2-2, in this design, we used 5 inverters and 4 transmission gates. The ELDO analog simulation result can be seen in Figure 2-3.
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The schematic and layout of JK-flipflo are show in Figure 2-4 and Fi e c t op wn e igure 2-5, , in this design, we use 1 inverter, 6 NAND2 gates and 2NAND3 g ed 2 gates. The E ELDO analo og simulation resu can be se in Figure 2-6. <Re ult een eference use for schematic was ed http://www.play-hookey.com/ /digital/jk_na and_flip-flop.html>
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The schematic and layout of 0-5 counter are shown in Figure 2-10and Figure 2-11, in this design, we used 3 JK flipflops, 3 inverters, and 3 NAND2 gates. In layout, in order to fit the floor plan, we designed it not in a rectangular shape.
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The ELDO analog simulation result can be seen in Figure 2-12. We can see that the counter starts from 000 to 101 and returns to 000.
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The schematic and layout of 0-9counter are shown in Figure 2-13and Figure 2-14, in this design, we used 4 JK flipflops, 1 inverter, 3 NAND2 gates and 1 NAN3 gate.
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ELDO analog simulation result can be seen in Figure 2-15. We can see that the counter starts from 0000 to 1001 and returns to 0000.
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flipflops with reset function, 1 inverter, 3 NAND2 gates and 1 NAN3 gate.
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ELDO analog simulation result can be seen in Figure 2-18. We can see that the counter starts from 0000 to 1001 and returns to 0000. We gave a reset signal during the operation, all digits are set to 0 immediately.
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To implement this function, we generate the truth table for a 4-7 segment decoder as below and get its corresponding 7 segment output and annotate them in decimal.
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DECIMAL OR FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BI
INPUTS D L L L L L L L L H H H H H H H H X C L L L L H H H H L L L L H H H H X B L L H H L L H H L L H H L L H H X A L H L H L H L H L H L H L H L H X ~BI H H H H H H H H H H H H H H H H L 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 X a H L H H L H L H H H L L L H L L L b H H H H H L L H H H L L H L L L L c H H L H H H H H H H L H L L L L L
The schematic and layout of a 4-7 segment decoder are shown in Figure 2-20Error! Reference source not found.Figure 2-4 and Figure 2-22. In this design, we used 12 inverters, 14 NAND2 gates, 13 NAN3 gates and 1 NAND4 gate.
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ModelSIM digital simulation result can be seen in Figure 2-23. We can see that the different input from 0000 to 1111 correspond to different output according to the truth table in Table 1, thus verifying our design.
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We implemented the function shown in Figure 3-1, and include all the sub-blocks we set up before, draw the top view schematic as below, and then top view layout Figure 3-3.
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3.2 Layout
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3.3 Simulation
In the top view simulation, we can simultaneously look at all the 12 outputs. These have been shown in the three following figures. In the first figure, we can see all the four bits of
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ECE261 CMOS VLSI Design Final Project Report the unit digit of minute, and two of the three bits of tens digit of minute. If we look at MU1, MU2, MU3 and MU4, counting starts from 0, goes up till 9, and then again goes back to 0 and so on. At every transition from 9 to 0, a clock pulse is sent to the tens digit of minute, i.e., to the 0-5 counter. So, as soon as MU4 transitions from high to low, we can see a transition in MT1 as well. MT1, MT2 and MT3 form the three bits of the tens digit of minute. These start counting from 0, go up till 5, and then again go back to zero. This counting from o to 5 and back to zero can be clearly seen in the second figure.
In this figure, we can clearly see the tens digit of minute and the transition on the unit digit of hour after sixty minutes elapse. As long as both MT3 and MT1 are high, the time that is displayed on the minute part of the clock varies from 50 to 59. After this, all the bits in the minute display become zero, and a clock pulse is sent to the 0-9 counter which is used for the unit digit of hour. So, every time MT3 transitions from high to low, there is a transition in HU1.
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In this figure, we can see the both the unit and the tens digit of hour. HU1, HU2, HU3 and HU4 together make up the unit digit of hour, and HT1 is for the tens digit. HU1, HU2, HU3 and HU4 count from 0 to 9 and then go back to 0 again. As soon as the transition from 9 to 0 takes place, a clock pulse is sent to the resettable JK-flipflop used for the tens digit display of hour. This stays high for one complete clock period on HU1, and then all the bits in HOUR display become zero (except for a spike in HU2 which is too short to be noticed in practice). A high pulse on HT1 and a simultaneous low and then high on HU1, while HU2 and HU3 stay low, implies display 10 and 11 on the hour digits. After 11, the hour display shows 00 since all of the bits, HU1, HU2, HU3 and HU4 become 0. For as long as there is a zero on HU1 or a 1 on HU1, the minutes digit would count from 00 to 59. Thus, overall the clock would display from00:00 to 11:59 and back to 00:00.
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References
N. H. E. Weste and D. Harris, CMOS VLSI design : a circuits and systems perspective: Boston : Pearson/Addison-Wesley, c2005. TI, system on chip: sn74ls47, BCD-TO-SEVEN-SEGMENT DECODERS/DRIVERS,1998 ST, system on chip: M74HC107, DUAL J-K FLIP FLOP WITH CLEAR,2000
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