Lecture # 07

Dr. Rehan Hafiz

<rehan.hafiz@seecs.edu.pk>

Course Website for ADSD Fall 2011

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http://lms.nust.edu.pk/
Acknowledgement: Material from the following sources has been consulted/used in these slides: 1. [CIL] Advanced Digital Design with the Verilog HDL, M D. Ciletti 2. [SHO] Digital Design of Signal Processing System by Dr Shoab A Khan 3. [STV] Advanced FPGA Design, Steve Kilts 4. Some slides from : [ECEN 248 Dr Shi]

Lectures: Contact: Office:

Tuesday @ 5:30-6:20 pm, Friday @ 6:30-7:20 pm By appointment/Email VISpro Lab above SEECS Library

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Introduction Verilog+ Combinational Logic Verilog + Sequential Logic Synthesis in Verilog Micro-Architecture <Micro-Coded-Machines> Optimizing Speed Optimizing Area FIR Implementation CDC Issues Fixed-Point Arithmetic Adders Multipliers CORDIC Algorithmic Transformations for System Design Algorithmic Transformations Project Project

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Outline & Introduction, Initial Assessment of students, Digital design methodology & design flow Combinational Logic Review + Verilog Introduction, Combinational Building Blocks in Verilog Sequential Common Structure in Verilog (LFSR /CRC+ Counters + RAMS), Sequential Logic in Verilog Synthesis of Blocking/Non-Blocking Statements Design Partitioning + RISC Microprocessor + Micro architecture Document Architecting Speed in Digital System Design: [Throughput, Latency, Timing] Architecting Area in Digital System Design: [Area Optimization] FIR Implementations + Pipelining & Parallelism in Non Recursive DFGs Cross-Clock Domain Issues & RESET circuits Arithmetic Operations: Review Fixed Point Representation Adders & Fast Adders Multi-Operand Addition Multiplication , Multiplication by Constants + BOOTH Multipliers CORDIC (sine, cosine, magnitude, division, etc), CORDIC in HW DFG representation of DSP Algorithms, Iteration Bound & Retiming

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Unfolding Look ahead transformations Course Review & Project Presentations

Project Presentations

Why different clock domains Metastability Solutions

Double Flopping Asynchronous FIFO Buffers

.issues in Multiple Clock Domains

Why multiple clock domains

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Clock Domain:

A section of logic where all synchronous elements (ipops, synchronous RAM blocks, pipelined multipliers, etc) are clocked by the same net. Gated clocks, derived clocks, and event-driven ip-ops, external clocks, asynchronous clocks ! Usually characterised by an unknown phase difference to pass data between two systems with pre-dened clock frequencies receive and transmit data over multiple I/O interfaces process asynchronous signals
Chapter 6, [STV Book]

Multiple Clock Domains

Example

Metastability
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A Flip Flop can go into Metastable state if its timing constraints are not met due to Setup & Holdtime Violation !

This becomes impossible/difficult for the case of multiple clock domains --- for synthesizers to predict !
A Metastable value is neither One nor Zero; however practically it becomes stable (correct or in-correct) within a cycle !

Metastability
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Mean Time Between Failures (MTBF)

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MTBF is a measure of the mean time between failures; where failure is defined as the event when Flip Flop enters into a metastable state !

The mean time between failures, or MTBF, due to metastability provides an estimate of the average time between instances when metastability could cause a design failure.
A higher MTBF (such as hundreds or thousands of years between metastability failures) indicates a more robust design.

MTBF (t resolve )

t resolve

f clk f dataC

Resolve Time: The amount of time the Flip Flop's output must return to a valid level before it's used. This is [1/clock frequency] [Tclk2q + Troute + Tsu ] T & C are device dependent and typically provided by ASIC/FPGA vendors

CDC signals Cross-Clock Domain Crossing - Issues

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CDC Signals
Control, Data

CDC Issues
Failures

are not always repeatable/predictable Technology Dependence

Newer technologies requires less TS & TH

EDA

Tools many not detect these errors

Meta-stability Solution-1: Phase Control

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Where Applicable:
Clk-1 controllable inside

the FPGA via an internal PLL (Phase locked loop) or DLL (Delay locked loop) Clk-2 has a period that is a multiple of Clk-1

Solution
DLL

adjusts the phase of the faster (capture) clock domain to match that of the slower (transmitting) clock domain

What it does

Meta-stability Solution-1: Phase Control

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Built-in IP Cores usually available

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http://www.xilinx.com/support/documenta tion/user_guides/ug331.pdf

Solution 2: Double Flopping

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Where Applicable

When passing single-bit signals between two asynchronous clock domains Synchronization bits, dual rank ip-ops, or dual rank synchronizers

Solution

Double Flopping What it does ?

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Double Flopping Why: ONLY for Control signals

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Case: Asynchronous Signal

Not possible to predict when the desired transition will occur

i.e. current rising edge or next rising edge

Data BUS: Different bits of same word may arrive at different time Problematic:

Data bus Where timings are crucial

Solution-3 FIFO Buffering

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Implement a FIFO Buffer

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Soution-4 Gray Code for multiple Control/Data bits

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Each successive number changes by only ONE bit Gray codes can be used to pass multibit counter data between asynchronous clock domains and are often used inside FIFOs If the one bit that changes is not captured by the next clock edge, the old address will remain as the synchronized value.

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FIFO Addressing as Circular FIFO

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FIFO is managed as a circular buffer using pointers. Let the read & write address Rollover ! First write will occur at address 00h. Next write will occur at 01h. After writing at FFh, next write will wrap to 00h. Reads work the same way.

Circular FIFO : Empty/Full Signals

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We use one extra bit to address a Circular FIFO

i.e. Use 4 bits to address 8 locations 3 LSB bits shall point towards the actual address The MSB shall inform IF the pointer has rolled over the Circular FIFO

The next address after 0111 shall be 1000. Which means the actual address pointer shall point at location 000. The MSB indicates that the Write pointer has done one iteration of the FIFO This helps in knowing if either the Write Pointer is about to overtake Read Pointer (MSB shall be different)OR the Read Pointer is about to overtake the Write Pointer (MSB shall be same)

Empty Signal

Write Pointer [3:0] == Read Pinter [3:0] Write Pointer [2:0] == Read Pinter [2:0] Write Pointer [3] != Read Pinter [3]

Full Signal

In case of Packets of data we may use Shadow Pointers

Generating Status Signals for Circular FIFO

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RB = Rest of bits !

{RB of Write Pointer} {RB of Read Pointer}

{MSB of Write Pointer} {MSB of Read Pointer}

{MSB of Write Pointer, RB of Write Pointer} {MSB of Read Pointer, RB of Read Pointer}