International Journal of Computational Intelligence and Information Security, December 2011 Vol. 2, No.

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An Application of Direct Modulation to Generate SPWM Waveform Using VHDL for FPGA Interfaced H-Bridge Power Inverter
Akhilesh Kumar1, Puspa Kumari2, Archana Kumari Sinha3
1

Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India headeced@gmail.com 2 Department of E&C Engineering, NIT Jamshedpur, Jharkhand, India kumarisonu27@gmail.com 3 Department of Physics, S.G.G.S College, Patna Saheb, Bihar, India aksinha58@gmail.com Abstract
We propose a novel, simple and very much convincing scheme to generate sinusoidal pulse width modulated (SPWM) switching pulses using Direct Modulation Strategy. In this work, implementation of generation of SPWM switching pulses has been done through software developed using VHDL code. In the given proposed scheme, the periodic PWM signals are generated, separated by positive and negative group of polarity control switching pulse and evoked at the output as a control signal for FPGA interfaced H-Bridge power inverter circuit. Keywords - VHDL; MUX; polarity control; multiple circuit switching. Sinusoidal pulsewidth modulation (SPWM)).

1. Introduction
Sinusoidal Pulse Width Modulation, abbreviated as SPWM, is a method of transmitting information on a series of pulses. In order to reduce the circuit complexity as well as memory consumption, a proper use of signal generator can be utilized. By varying pulse width in accordance with amplitude of sine wave, an approximated sine wave can be produced by averaging its output pulses [1]. In direct modulation scheme PWM pulses are generated directly and thus require less memory space as compared to conventional sine-triangular scheme [2]. This effectively simplifies the circuit and reduces the power consumption during the process of PWM signal generation without subtle loss or no loss at all. The proposed scheme is based on VHDL coded software developed with flexibility in its algorithm for generation of N number of control SPWM pulses in each cycle and easily be implemented to produce AC power using FPGA interfaced H bridge power inverter circuit.

2. Software scheme for PWM generation

The source code is written in a high level programming language. He algorithm for generation of the pulses is shown below: The sinusoidal amplitude modulated pulse width Pi ( i = 1,2..N) of each cycle is fed to the MUX unit for outputting N number of PWM control pulses and is outputted by the logical expression (Eq. 1). q(N) = w00 + w11+ w22wii where, i =1,2 .. N = Number of PWM pulses in each half of a cycle q = MUX output (PWM Main Switching Signal) w00 = Pulse width P( i = 1) w11 = Pulse width P( i =2) wii = Pulse width P( i =N) The positive half cycle and negative half cycle group of PWM control pulses are extracted with the following logical expression (Eq. 2 and Eq. 3). mss_p = q AND w33 (positive group) mss_n = q AND (NOT w33) ( negative group) (2) (3) (1)

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The truth table of MUX for PWM pulses (N=3) is shown in Table 1.
Table 1: Truth table of MUX for N=3
Selection Line Inputs
S[1] S[0]

Output
q(N)

0 0 1 1

0 1 0 1

w00 w11 w22 w22

The algorithm has been implemented using VHDL code. VHDL is the acronym for Very High Speed Integrated Circuit (VH_SIC) hardware Descriptive Language. It is a high level programming language used for designing, simulating and synthesizing both simple and complex digital logic circuits. The flexibility offered by the language made its immensely popular among the chip designers. In the given proposed scheme, a MUX is used for multiplexing the individual pulses of SPWM wave of varying pulse width i.e. Pi which are generated by signal generators. The scheme is applicable for both periodic and a-periodic wave form consisting different frequencies with N number of PWM pulses. A polarity control is introduced in order to fetch the positive and negative group of signal required to generate a AC sine wave as shown in combinational logic block of schematic diagram (Figure 1 (a) and (b)). The entity of the control circuit with its architecture is shown in Figure 2 and Figure 3. The selection line for MUX is shown as output signal S(1:0).

(a)

(b) Figure 1: (a) Block diagram of the PWM waveform (b) Power H- Bridge inverter module

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International Journal of Computational Intelligence and Information Security, December 2011 Vol. 2, No. 12

The program has been downloaded on FPGA board using Xilinx ISE Simulator (version 9.2i) to generate base drive signal for H Bridge Inverter circuit which can produce approximated sine wave output of variable frequency.

Figure 2. Entity of the circuit

Figure 3. The internal architecture of the circuit

The outputs w00, w11, w22 are the specified generated input by signal generator signals and w33 is the polarity control signal as stated before. mss_p and mss_n are the multiplexed signals for the positive and negative group signal respectively. The CLKIN is the master clock synchronized with input and output signals. The positive and the negative parts i.e. mss_p and mss_n are obtained after ANDing with MUX output (mss) with the polarity control signal. A counter is used to generate the selection lines S(1: 0). The reset pin (RST) is used as like a key to switch on the circuit i.e when the RST is 0 the output is zero and when RST is made 1 we get the signal according to the switching. At the output we affectively get the Control base drive pulses which can be interfaced with H Bridge Inverter circuit to get approximated sine wave.

3. Programming with VHDL

The programming in VHDL is done in two stages. The first stage is known as entity declaration in which the whole circuit can be seen as a black box of which a set of input and outputs are defined. This portion of programming is done with an external view. The entity of the given programme is shown in Figure 2. In the second stage, the internal architecture is defined. The detailed connections and the circuit logic is defined in this section. The internal architecture of the circuit is shown in Figure 3.

4. Program Design
In order to write the program, the programmer needs to declare the libraries in which the definition or prototype are defined similar like Java. In Java we need to import the packages and in VHDL we need to declare the libraries 55

International Journal of Computational Intelligence and Information Security, December 2011 Vol. 2, No. 12

by use keyword. After that the entity is declared where all the inputs and outputs (like inputs and outputs of a black box) are specified. Next comes the architecture defining. In VHDL architecture can be defined in mainly three ways as follows [4]: Structural Style Dataflow Style Behavioral Style.

Another possible way of defining the architecture is Mixed Style in which all of the above three can be used in combination. During coding sometimes we need to use some internal signals which we make invisible from the outside. By maintain such abstraction we can reduce the complexities and able to maintain hierarchy. The source code of the program in VHDL[5][6] developed for generation of PWM sinewave Such signals need to be declared before using them in the logic. The keyword signal is used for this purpose. Even it is possible to assign a specific value (for example signal CLK_0: std_logic := '0'; is used in the code) to them otherwise they are associated with the default values by the compiler. In our code there is a master clock which is fed to the signal generator in order to generate all the signals. There is a use of counter which selects the input channels of the MUX. The output of the MUX is ANDed with the polarity control signal to produce the mss_p output. The other output is the mss_n which is produced by ANDing the MUX output with the inverted polarity control signal. Here the use of polarity control signal is to extract the positive half (mss_p) and the negative half(mss_n) from the MUX output. From the output (Figure 4) it is clearly seen that both of the mss_p and mss_n can drive positive and negative group of inverter module to get the sinusoidal signal across load (Figure 5a and 5b).

Figure 4 : Output control pulses; PWM Main Switching Signal (Top); positive group of the PWM signal (Middle); Negative group for H bridge inverter circuit.(Bottom)

Figure 5(a): Voltage waveform across load

Figure 5(b): Showing sinewave in voltage across load simulated Output

The output of the simulated PWM control pulses are shown in Figure 6. We are giving input signal in interval of 220ns at 0, 90 and 180 degree and repeat this sequence for 8 intervals to get corresponding simulated sine wave in output. 56

International Journal of Computational Intelligence and Information Security, December 2011 Vol. 2, No. 12

.
Figure 6. Simulated output waveform

5. Application
The proposed scheme can be used for qualitative AC power generation from conventional as well as renewable energy input sources like PV, wind, tidal etc. Since the output waveform is a PWM sine wave and hence on averaging it, an approximation to a sine wave containing fewer harmonics is achievable. The realization of simulated waveform through hardware circuit can be easily implemented using FPGA module or in embedded ASIC chip.

6. Conclusion
In this paper, direct modulaion scheme has been used to generate Sinusoidal Pulse Width Modulated pulses and it has been carried out using VLSI technology on Spartan3 FPGA kit. This scheme has been successfully implemented. The base drive pulses generated by Spartan3 FPGA kit is fed to bridge converter power modulated circuit to get the required waveforms.

References
[1] [2] [3] [4] [5] [6] [7]

[8]

Rashid M., Power electronics: circuits, devices and application Prentice Hall India, 2004. R. Seyezhai and Dr. B. L. Mathur, Performance evaluation of inverted sine pwm technique for an asymmetric cascaded multilevel inverter JATIT, 2005. www.xilinx.com/applications/industrial/index.html. Jayaram Bhaskar, A VHDL primer Prientice Hall, 1992 pp. 6-12. Mayer-Lindenberg F.,High-Level FPGA Programming through Mapping Process Networks to FPGA Resources, 2009. Stephen Brown and Zvonko Vranesic, Fundamentals of digital logic design with VHDL, TMH, 2009, pp.341344 Puspa Kumari et al., Simulation and generation of SPWM waveform using VHDL for FPGA interfaced H bridge power inverter, IEEE international conference on Industrial Electronics, Control and Robotics, 2010, pp. 39-42 Charles H. Roth, Jr., Digital Design using VHDL PWS Publication, 1998.

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Authors Prof. Akhilesh Kumar received B.Tech degree from Bhagalpur University, Bihar, India in 1986 and M.Tech degree from Ranchi, Bihar, India in 1993. He has been working in teaching and research profession since 1989. He is now working as H.O.D. in Department of Electronics and Communication Engineering at N.I.T. Jamshedpur, Jharkhand, India. His interests of fields are communication systems, image processing, VLSI design and embedded systems.

Ms. Puspa Kumari had published one papers in National and two papers in International journal. She is pursuing B.Tech.(Hons) course in the Department of Electronics & Communication Engineering in National Institute of Technology (An Autonomous Institution under MHRD, Govt. of India) Jamshedpur (India) Her interest of field of research is VHDL in FPGA based digital circuit design.

Prof. A. K. Sinha is presently Associate Professor and Head of the Department of Physics at S.G.G.S College, Patna Saheb, Bihar, India. She did her M.Sc (Physics) and Ph.D Degree from Magadh University, Bodh Gaya,Bihar in the month/year August 1981 and June 2003 respectively. Her fields of interest are Material Science, Semi-Conductor Devices, Electronic Spectra, Structure of Polyatomic Molecules, VLSI and its related fields.

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