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SH1101A

132 X 64 Dot Matrix OLED/PLED Segment/Common Driver with Controller


Row re-mapping and column re-mapping (ADC) Vertical scrolling On-chip oscillator Available internal DC-DC converter 256-step contrast control on monochrome passive OLED panel Low power consumption - Sleep mode: <5A Wide range of operating temperatures: -40 to +85C Available in COG and TCP form

Preliminary Features
Support maximum 132 X 64 dot matrix panel Embedded 132 X 64 bits SRAM Operating voltage: - Logic voltage supply: VDD1 = 2.4V - 3.5V - DC-DC voltage supply: VDD2 = 2.4V - 3.5V - OLED Operating voltage supply: VPP = 7.0V - 16.0V Maximum segment output current: 320A Maximum common sink current: 45mA 8-bit 6800-series parallel interface, 8-bit 8080-series parallel interface, serial peripheral interface Programmable frame frequency and multiplexing ratio

General Description
SH1101A is a single-chip CMOS OLED/PLED driver with controller for organic/polymer light emitting diode dot-matrix graphic display system. SH1101A consists of 132 segments, 64 commons that can support a maximum display resolution of 132 X 64. It is designed for Common Cathode type OLED panel. SH1101A embeds with contrast control, display RAM oscillator and efficient DC-DC converter, which reduces the number of external components and power consumption. SH1101A is suitable for a wide range of compact portable applications, such as sub-display of mobile phone, calculator and MP3 player, etc.

V0.14

NC
VSS SW VDD2 FB SENSE 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 D2 D3 D4 D5 D6 D7 IREF VCOMH VPP NC 23 24 25 26 27 28 29 30 31 170 169 168 NC SEG95 SEG94 179 178 177 COM3 COM1 NC 5 4 3 2

NC 211 210 209 208 NC NC COM63 COM61

VPP

249 248 247 246

NC NC COM62 COM60

Pin Configuration

VCOMH

IREF

D7 217 216 215


VBREF NC NC NC VDD1 C86 P/S NC CS RES A0 WR RD D0 D1

5 COM2 COM0 NC

D6

D5

D4

D3

D2 205 204 203 202 NC SEG0 SEG1 SEG2

10

D1

11

D0

12

RD

13

WR

14

A0

15

RES

16

SH1101A-TCP03 (Copper Side View)

SH1101A-TCP06 (Copper Side View)

2
75 74 73 72 SEG129 SEG130 SEG131 NC 66 65 64 NC COM1 COM3 35 34 33 32 COM61 COM63 NC NC

CS

17

NC

18

P/S

19

C86

20

VDD1

21

75 74 73

SEG1 SEG0 NC

NC

22

NC

23

NC

24

VBREF

25

SENSE

26

66 65 64

NC COM0 COM2

FB

27

VDD2

28

SW

29

VSS

30

SH1101A

NC

31

35 34 33 32

COM60 COM62 NC NC

SH1101A
Pad Configuration
269

238 237

106 105

74

xx Y

xx

SH1101A
X 1

(0,0)

Dummy Pad

X 73

SH1101A
Block Diagram
SEG0 SEG131 COM0 COM63

VDD1 VDD2 VSS

VCOMH VCL VSL IREF VREF Shift register VPP SW SENSE FB VBREF Output status selector circuit I/O buffer circuit DC-DC Display data latch Initial display line register line address decoder Power supply circuit Segment driver Common driver

132 X 64-dots Display Data RAM

Column address decoder Page Address Register 8-bit column address counter Display Timing Generator Circuit 8-bit column address counter CL

Bus Holder

Command Decoder

Bus Holder

Line counter

Oscillator

CLS

Microprocessor Interface

I/O Buffer

CS

A0

RD

WR P/S C86

RES

D7 D6 D5 D4 D3 D2

D1 (SI)

D0 (SCL)

(E) (R/W)

SH1101A
Pad Description
Power Supply Pad No. 28 - 31 34, 44, 62 17 - 20 7 - 13 21, 32, 36, 42, 64 49 - 53, 71 - 73 66 4-6 1-3 OLED Driver Supplies Pad No. 70 65 45 - 48, 67 - 69 14 - 16 22 23 24 Symbol VREF IREF VCOMH SW FB SENSE VBREF I/O I O O O I I O Description This is a voltage reference pad for pre-charge voltage in driving OLED device. Voltage should be set to match with the OLED driving voltage in current drive phase. It can either be supplied externally or by connecting to VPP. This is a segment current reference pad. A resistor should be connected between this pad and VSS. Set the current at 10A. This is a pad for the voltage output high level for common signals. A capacitor should be connected between this pad and VSS. This is an output pad driving the gate of the external NMOS of the booster circuit. This is a feedback resistor input pad for the booster circuit. It is used to adjust the booster output voltage level, VPP. This is a source current pad of the external NMOS of the booster circuit. This is an internal voltage reference pad for booster circuit. A stabilization capacitor, typical 1F, should be connected to VSS. Symbol VDD1 VDD1 VDD2 VSS VSS VPP VPP VSL VCL I/O Supply Supply Supply Supply Supply Supply Supply Supply Supply 2.4 - 3.5V power supply input. 2.4 - 3.5V power supply output for pad option. 2.4 - 3.5V power supply pad for the internal buffer of the DC-DC voltage converter. Ground. Ground output for pad option. This is the most positive voltage supply pad of the chip. It should be supplied externally. This is the most positive voltage output for pad option, which cannot be used as the most positive voltage input. This is a segment voltage reference pad. This pad should be connected to VSS externally. This is a common voltage reference pad. This pad should be connected to VSS externally. Description

SH1101A
System Bus Connection Pads Pad No. Symbol 37 CL I/O I/O Description This pad is the system clock input. When internal clock is enabled, this pad should be Left open. The internal clock is output from this pad. When internal oscillator is disabled, this pad receives display clock signal from external clock source. This is the internal clock enable pad. CLS = H: Internal oscillator circuit is enabled. CLS = L: Internal oscillator circuit is disabled (requires external input). When CLS = L, an external clock source must be connected to the CL pad for normal operation. This is the MPU interface switch pad. C86 = H: 8080 series MPU interface. C86 = L: 6800 series MPU interface. This is the parallel data input/serial data input switch pad. P/S = H: Parallel data input. P/S = L: Serial data input. When P/S = L, D2 to D7 are HZ. D2 to D7 may be H, L or Open. RD (E) and WR ( R / W ) are fixed to either H or L. With serial data input, RAM display data reading is not supported. These are MPU interface input selection pads. See the following table for selecting different interfaces:

63

CLS

33

C86

35

P/S

6800-Parallel Interface C86 P/S 0 1

8080-Parallel Interface 1 1

Serial Interface 0 0

38
39

CS RES

I I

This pad is the chip select input. When CS = L, then the chip select becomes active, and data/command I/O is enabled. This is a reset signal input pad. When RES is set to L, the settings are initialized. The reset operation is performed by the RES signal level. This is the Data/Command control pad which determines whether the data bits are data or a command. A0 = H: the inputs at D0 to D7 are treated as display data. A0 = L: the inputs at D0 to D7 are transferred to the command registers. This is a MPU interface input pad. When connected to an 8080 MPU, this is active LOW. This pad connects to the 8080
MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R / W = H: Read. When R / W = L: Write. This is a MPU interface input pad. When connected to an 8080 series MPU, it is active LOW. This pad is connected to the

40

A0

41

WR (R/W )

43

RD (E)

RD signal of the 8080 series MPU, and the SH1101A data bus is in an output status when this signal is L. When connected to a 6800 series MPU , this is active HIGH. This is used as an enable clock input of the 6800 series MPU. This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected, then D0 serves as the serial clock input pad (SCL) and D1 serves as the serial data input pad (SI). At this time, D2 to D7 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance.

54 - 61 54 55

D0 - D7 (SCL) (SI)

I/O I I

SH1101A
OLED Drive Pads Pad No.
105 - 74, 238 - 269 106 - 237

Symbol
COM0 - 63 SEG0 - 131

I/O
O O

Description
These pads are Common signal output for OLED display. These pads are Segment signal output for OLED display.

Test Pads Pad No.


25 27 26 -

Symbol
TEST1 TEST2 TEST3 NC

I/O
I O I -

Description
Test pads, internal pull low, no connection for user. Test pads, no connection for user. Test pads, no connection for user. NC pads, no connection for user.

SH1101A
Functional Description
Microprocessor Interface Selection
The 8080-Parallel Interface, 6800-Parallel Interface or Serial Interface (SPI) can be selected by different selections of C86, P/S as shown in Table 1.

Table. 1 6800-Parallel Interface C86 P/S 6800-series Parallel Interface


The parallel interface consists of 8 bi-directional data pads (D7-D0), WR ( R / W ), RD (E), A0 and CS . When WR ( R / W ) = H, read operation from the display RAM or the status register occurs. When WR ( R / W ) = L, Write operation to display data RAM or internal command registers occurs, depending on the status of A0 input. The RD (E) input serves as data latch signal (clock) when it is H, provided that CS = L as shown in Table. 2. 0 1

8080-Parallel Interface
1 1

Serial Interface
0 0

Table. 2 P/S
1

C86
0

Type
6800 microprocessor bus

CS

A0
A0

RD E

WR

D0 to D7 D0 to D7

CS

R/W

In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline processings are internally performed, which require the insertion of a dummy read before the first actual display data read. This is shown in Figure. 1 below.
A0 E R/W

MPU

DATA

n+1

Address preset

Internal timing

Read signal Preset Column address BUS holder N N n Incremented N+1 N+2 n+1 n+2

Set address n

Dummy read

Data Read address n

Data Read address n+1

Figure. 1

SH1101A
8080-series Parallel Interface The parallel interface consists of 8 bi-directional data pads (D7-D0), WR ( R / W ), RD (E), A0 and CS . The RD (E) input serves as data read latch signal (clock) when it is L provided that CS = L. Display data or status register read is controlled by A0 signal. The WR ( R / W ) input serves as data write latch signal (clock) when it is L and provided that CS = L. Display data or command register write is controlled by A0 as shown in Table. 3. Table. 3 P/S 1 C86 1 Type 8080 microprocessor bus CS CS A0 A0 RD RD WR WR D0 to D7 D0 to D7

Similar to 6800-series interface, a dummy read is also required before the first actual display data read. Data Bus Signals The SH1101A identifies the data bus signal according to A0, RD (E) and WR ( R / W ) signals. Table. 4 Common A0 1 1 0 0 6800 processor (R / W ) 1 0 1 0 8080 processor RD 0 1 0 1 WR 1 0 1 0 Reads display data. Writes display data. Reads status. Writes control data in internal register. (Command) Function

SH1101A
Serial Interface (SPI) The serial interface consists of serial clock SCL, serial data SI, A0 and CS . SI is shifted into an 8-bit shift register on every rising edge of SCL in the order of D7, D6, and D0. A0 is sampled on every eighth clock and the data byte in the shift register is written to the display data RAM or command register in the same clock. See Figure. 2. Table. 5 P/S 0 C86 0 Type Serial Interface (SPI) CS CS A0 A0 RD WR D0 SCL D1 SI D2 to D7 (HZ)

Note: - Must always be HIGH or LOW.

CS SI (D1) D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5

SCL(D0) 1 A0 2 3 4 5 6 7 8 9 10 11

Figure. 2 When the chip is not active, the shift registers and the counter are reset to their initial statuses. Read is not possible while in serial interface mode. Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend the operation be rechecked on the actual equipment. Access to Display Data RAM and Internal Registers This module determines whether the input data is interpreted as data or command. When A0 = H, the inputs at D7 - D0 are interpreted as data and be written to display RAM. When A0 = L, the inputs at D7 - D0 are interpreted as command, they will be decoded and be written to the corresponding command registers. Display Data RAM The Display Data RAM is a bit mapped static RAM holding the bit pattern to be displayed. The size of the RAM is 132 X 64 bits. For mechanical flexibility, re-mapping on both segment and common outputs can be selected by software. For vertical scrolling of the display, an internal register storing display start line can be set to control the portion of the RAM data to be mapped to the display.

10

SH1101A
The Page Address Circuit As shown in Figure. 3, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. The Column Address As shown in Figure. 3, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/ write command. This allows the MPU display data to be accessed continuously. Because the column address is independent of the page address, when moving, for example, from page0 column 83H to page 1 column 00H, it is necessary to re-specify both the page address and the column address. Furthermore, as shown in Table. 6, the Column re-mapping (ADC) command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the OLED module is assembled can be minimized. Table. 6 Segment Output ADC 0 ADC 1 SEG0 0 (H) 83 (H) Column Address Column Address SEG131 83 (H) 0 (H)

The Line Address Circuit The line address circuit, as shown in Figure. 3, specifies the line address relating to the common output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 output for SH1101A, when the common output mode is reversed. The display area is a 64-line area for the SH1101A from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. that can be performed relationship between display data RAM and address (if initial display line is 1DH).

11

SH1101A
Page Address
D3 0 D2 0 D1 0 D0 0

Data
D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0=1 D0=0 00H 01H 02H

Line Address
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 82H 83H

OUTPUT
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63

PAGE 0

D3 0

D2 0

D1 0

D0 1

PAGE1

D3 0

D2 0

D1 1

D0 0

PAGE2

D3 0

D2 0

D1 1

D0 1

PAGE3

D3 0

D2 1

D1 0

D0 0

PAGE4

D3 0

D2 1

D1 0

D0 1

PAGE5

D3 0

D2 1

D1 1

D0 0

PAGE6

D3 0

D2 1

D1 1

D0 1

PAGE7

Column Address

ADC

83H

82H

81H

02H

81H

01H SEG130

SEG129

Figure. 3

12

SEG131

LCD OUT

SEG0

SEG1

SEG2

00H

SH1101A
The Oscillator Circuit This is a RC type oscillator (Figure. 4) that produces the display clock. The oscillator circuit is only enabled when CLS = H. When CLS = L, the oscillation stops and the display clock is inputted through the CL terminal.

Internal OSC MUX CL CLS

CLK

DIVIDER

DCLK Internal Display Clock

Figure. 4

13

SH1101A
DC-DC Voltage Converter It is a switching voltage generator circuit, designed for hand held applications. In SH1101A, built-in DC-DC voltage converter accompanied with an external application circuit (shown in Figure. 5) can generate a high voltage supply VPP from a low voltage supply input VDD2. VPP is the voltage supply to the OLED driver block.
L VDD2 C1 + VSS VDD2 C2 + SW C4 + Q R1 R3 D VPP

VBREF C3 + VSS

DC-DC

SENSE

FB R2 + C5

VSS

VSS

Figure. 5 VPP = (1+ R1 ) X VBREF, (R2: 80 - 120k ) R2

Current Control and Voltage Control This block is used to derive the incoming power sources into different levels of internal use voltage and current. VPP and VDD2 are external power supplies. VREF, a reference voltage, which is used to derive the driving voltage for segments and commons. IREF is a reference current source for segment current drivers. Common Drivers/Segment Drivers Segment drivers deliver 132 current sources to drive OLED panel. The driving current can be adjusted up to 320A with 256 steps. Common drivers generate voltage scanning pulses. Reset Circuit When the RES input falls to L, these reenter their default state. The default settings are shown below: 1. Display is OFF. Common and segment are in high impedance state. 2. 132 X 64 Display mode. 3. Normal segment and display data column address and row address mapping (SEG0 is mapped to column address 00H and COM0 mapped to row address 00H). 4. Shift register data clear in serial interface. 5. Display start line is set at display RAM line address 00H. 6. Column address counter is set at 0. 7. Normal scanning direction of the common outputs. 8. Contrast control register is set at 80H. 9. Internal DC-DC is selected.

14

SH1101A
Commands The SH1101A uses a combination of A0, RD (E) and WR ( R / W ) signals to identify data bus signals. As the chip analyzes and executes each command using internal timing clock only regardless of external clock, its processing speed is very high and its busy check is usually not required. The 8080 series microprocessor interface enters a read status when a low pulse is input to the RD pad and a write status when a low pulse is input to the WR pad. The 6800 series microprocessor interface enters a read status when a high pulse is input to the R / W pad and a write status when a low pulse is input to this pad. When a high pulse is input to the E pad, the command is activated. (For timing, see AC Characteristics.). Accordingly, in the command explanation and command table, RD (E) becomes 1(HIGH) when the 6800 series microprocessor interface reads status of display data. This is an only different point from the 8080 series microprocessor interface. Taking the 8080 series, microprocessor interface as an example command will explain below. When the serial interface is selected, input data starting from D7 in sequence. Command Set 1. Set Lower Column Address: (00H - 0FH) 2. Set Higher Column Address: (10H - 1FH) Specifies column address of display RAM. Divide the column address into 4 higher bits and 4 lower bits. Set each of them into successions. When the microprocessor repeats to access to the display RAM, the column address counter is incremented during each access until address 132 is accessed. The page address is not changed during this time. A0 Higher bits Lower bits A7 0 0 1 A6 0 0 0 0 0 A5 0 0 0 E RD 1 1 A4 0 0 : 0 0 0 1 1 R/W WR 0 0 A3 0 0 D7 0 0 A2 0 0 D6 0 0 A1 0 0 D5 0 0 D4 1 0 A0 0 1 D3 A7 A3 D2 A6 A2 D1 A5 A1 D0 A4 A0

Line address 0 1 : 131

Note: Dont use any commands not mentioned above. 3 - 5. Reserved Command These three commands are reserved for user. 6. Set Display Start Line: (40H - 7FH) Specifies line address (refer to Figure. 3) to determine the initial display line or COM0. The RAM display data becomes the top line of OLED screen. It is followed by the higher number of lines in ascending order, corresponding to the duty cycle. When this command changes the line address, the smooth scrolling or page change takes place. A0 0 A5 0 0 1 1 A4 0 0 1 1 E RD 1 A3 0 0 : 1 1 1 1 1 1 0 1 R/W WR 0 A2 0 0 D7 0 D6 1 A1 0 0 D5 A5 D4 A4 A0 0 1 D3 A3 D2 A2 D1 A1 D0 A0

Line address 0 1 : 62 63

15

SH1101A
7. Set Contrast Control Register: (Double Bytes Command) This command is to set contrast setting of the display. The chip has 256 contrast steps from 00 to FF. The segment output current increases as the contrast step value increases. Segment output current setting: ISEG = /256 X IREF X scale factor Where: is contrast step; IREF is reference current equals 10A; Scale factor = 32. The Contrast Control Mode Set: (81H) When this command is input, the contrast data register set command becomes enabled. Once the contrast control mode has been set, no other command except for the contrast data register command can be used. Once the contrast data set command has been used to set data into the register, then the contrast control mode is released. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 1

Contrast Data Register Set: (00H - FFH) By using this command to set eight bits of data to the contrast data register; the OLED segment output assumes one of the 256 current levels. When this command is input, the contrast control mode is released after the contrast data register has been set. A0 0 0 0 0 0 0 0 0 E RD 1 1 1 1 1 1 1 1 R/W WR 0 0 0 0 0 0 0 0 D7 0 0 0 1 1 1 D6 0 0 0 0 1 1 D5 0 0 0 0 1 1 D4 0 0 0 0 1 1 D3 0 0 0 : 0 : 1 1 D2 0 0 0 0 1 1 D1 0 1 1 0 1 1 D0 0 0 1 0 0 1 ISEG Small

: POR : Large

When the contrast control function is not used, set the D7 - D0 to 1000,0000. 8. Set Segment Re-map: (A0H - A1H) Change the relationship between RAM column address and segment driver. The order of segment driver output pads can be reversed by software. This allows flexible IC layout during OLED module assembly. For details, refer to the column address section of Figure. 3. When display data is written or read, the column address is incremented by 1 as shown in Figure. 1. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 0 D1 0 D0 ADC

When ADC = L, the right rotates (normal direction). (POR) When ADC = H, the left rotates (reverse direction). 9. Set Entire Display OFF/ON: (A4H - A5H) Forcibly turns the entire display on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This command has priority over the normal/reverse display command. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 0 D0 D

When D = L, the normal display status is provided. (POR) When D = H, the entire display ON status is provided.

16

SH1101A
10. Set Normal/Reverse Display: (A6H -A7H) Reverses the display ON/OFF status without rewriting the contents of the display data RAM. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 0 D2 1 D1 1 D0 D

When D = L, the RAM data is high, being OLED ON potential (normal display). (POR) When D = H, the RAM data is low, being OLED ON potential (reverse display) 11. Set Multiplex Ration: (Double Bytes Command) This command switches default 64 multiplex modes to any multiplex ratio from 1 to 64. The output pads COM0-COM63 will be switched to corresponding common signal. Multiplex Ration Mode Set: (A8H) A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 0 D1 0 D0 0

Multiplex Ration Data Set: (00H - 3FH) A0 0 0 0 0 0 0 E RD 1 1 1 1 1 1 R/W WR 0 0 0 0 0 0 D7 * * * * * D6 * * * * * D5 0 0 0 1 1 D4 0 0 0 1 1 D3 0 0 0 : 1 1 D2 0 0 0 1 1 D1 0 1 1 1 1 D0 0 0 1 0 1 Multiplex Ratio 1 2 3 : 63 64 (POR)

12. Set DC-DC OFF/ON: (Double Bytes Command) This command is to control the DC-DC voltage converter. The converter will be turned on by issuing this command then display ON command. The panel display must be off while issuing this command. DC-DC Control Mode Set: (ADH) A0 0 E RD 1

R/W
WR 0

D7 1

D6 0

D5 1

D4 0

D3 1

D2 1

D1 0

D0 1

DC-DC ON/OFF Mode Set: (8AH - 8BH) A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 0 D4 0 D3 1 D2 0 D1 1 D0 D

When D = L, DC-DC is disable. When D = H, DC-DC will be turned on when display on. (POR) Table. 7 DC-DC STATUS 0 0 1 1 DISPLAY ON/OFF STATUS 0 1 0 1 Description Sleep mode External VPP must be used. Sleep mode Built-in DC-DC is used, Normal Display

17

SH1101A
13. Display OFF/ON: (AEH - AFH) Alternatively turns the display on and off. A0 0 E RD 1 R/W WR 0 D7 1 D6 0 D5 1 D4 0 D3 1 D2 1 D1 1 D0 D

When D = L, Display OFF OLED. (POR) When D = H, Display ON OLED. When the display OFF command is executed, power saver mode will be entered. Sleep mode: This mode stops every operation of the OLED display system, and can reduce current consumption nearly to a static current value if no access is made from the microprocessor. The internal status in the sleep mode is as follows: (1) Stops the oscillator circuit and DC-DC circuit. (2) Stops the OLED drive and outputs HZ as the segment/common driver output. (3) Holds the display data and operation mode provided before the start of the sleep mode. (4) The MPU can access to the built-in display RAM. 14. Set Page Address: (B0H - B7H) Specifies page address to load display RAM data to page address register. Any RAM data bit can be accessed when its page address and column address are specified. The display remains unchanged even when the page address is changed. A0 0 A3 0 0 0 0 0 0 0 0 E RD 1 A2 0 0 0 0 1 1 1 1 R/W WR 0 A1 0 0 1 1 0 0 1 1 D7 1 D6 0 D5 1 A0 0 1 0 1 0 1 0 1 D4 1 D3 A3 D2 A2 D1 A1 D0 A0

Page address 0 1 2 3 4 5 6 7

Note: Dont use any commands not mentioned above for user.

18

SH1101A
15. Set Common Output Scan Direction: (C0H - C8H) This command sets the scan direction of the common output allowing layout flexibility in OLED module design. In addition, the display will have immediate effect once this command is issued. That is, if this command is sent during normal display, the graphic display will be vertically flipped. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 0 D4 0 D3 D D2 * D1 * D0 *

When D = L, Scan from COM0 to COM [N -1]. (POR) When D = H, Scan from COM [N -1] to COM0. 16. Set Display Offset: (Double Bytes Command) This is a double byte command. The next command specifies the mapping of display start line to one of COM0-63 (it is assumed that COM0 is the display start line, that equals to 0). For example, to move the COM16 towards the COM0 direction for 16 lines, the 6-bit data in the second byte should be given by 010000. To move in the opposite direction by 16 lines, the 6-bit data should be given by (64-16), so the second byte should be 100000. Display Offset Mode Set: (D3H) A0 0 E RD 1

R/W
WR 0

D7 1

D6 1

D5 0

D4 1

D3 0

D2 0

D1 1

D0 1

Display Offset Data Set: (00H~3FH) A0 0 0 0 0 0 0 E RD 1 1 1 1 1 1 R/W WR 0 0 0 0 0 0 D7 * * * * * D6 * * * * * D5 0 0 0 1 1 D4 0 0 0 1 1 D3 0 0 0 : 1 1 D2 0 0 0 1 1 D1 0 1 1 1 1 D0 0 0 1 0 1 COMx 0 (POR) 1 2 : 62 63

Note: * stands for Dont care

19

SH1101A
17. Set Display Clock Divide Ratio/Oscillator Frequency: (Double Bytes Command) This command is used to set the frequency of the internal display clocks (DCLKs). It is defined as the divide ratio (Value from 1 to 16) used to divide the oscillator frequency. POR is 1. Frame frequency is determined by divide ratio, number of display clocks per row, MUX ratio and oscillator frequency. Divide Ratio/Oscillator Frequency Mode Set: (D5H) A0 0 E RD 1

R/W
WR 0

D7 1

D6 1

D5 0

D4 1

D3 0

D2 1

D1 0

D0 1

Divide Ratio/Oscillator Frequency Data Set: (00H - 3FH) A0 0 E RD 1 R/W WR 0 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0

A3 - A0 defines the divide ration of the display clocks (DCLK). Divide Ration = A[3:0]+1. A3 0 A2 0 A1 0 : 1 1 1 1 A0 0 Divide Ration 1 (POR) : 16

A7 - A4 sets the oscillator frequency. Oscillator frequency increase with the value of A[7:4] and vice versa. A7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Oscillator Frequency of OSC -25% -20% -15% -10% -5% OSC (POR) +5% +10% +15% +20% +25% +30% +35% +40% +45% +50%

20

SH1101A
18. Set Dis-charge/Pre-charge Period: (Double Bytes Command) This command is used to set the duration of the pre-charge period. The interval is counted in number of DCLK. POR is 2 DCLKs. Pre-charge Period Mode Set: (D9H) A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 0 D0 1

Dis-charge/Pre-charge Period Data Set: (00H - FFH) A0 0 E RD 1 R/W WR 0 D7 A7 D6 A6 D5 A5 D4 A4 D3 A3 D2 A2 D1 A1 D0 A0

Pre-charge Period Adjust: (A3 - A0) A3 0 0 0 1 1 Dis-charge Period Adjust: (A7 - A4) A7 0 0 0 1 1 A6 0 0 0 1 1 A5 0 0 1 : 1 1 A4 0 1 0 0 1 Dis-charge Period INVALID 1 DCLKs 2 DCLKs (POR) : 14 DCLKs 15 DCLKs A2 0 0 0 1 1 A1 0 0 1 : 1 1 0 1 A0 0 1 0 Pre-charge Period INVALID 1 DCLKs 2 DCLKs (POR) : 14 DCLKs 15 DCLKs

19. Set Common pads hardware configuration: (Double Bytes Command) This command is to set the common signals pad configuration (sequential or alternative) to match the OLED panel hardware layout Common Pads Hardware Configuration Mode Set: (DAH) A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 1 D0 0

Sequential/Alternative Mode Set: (02H - 12H) A0 0 When D = L, Sequential. COM31, 30 - 1, 0 When D = H, Alternative. (POR) COM62, 60 - 2, 0 SEG0, 1 - 130, 131 COM1, 3 - 61, 63 SEG0, 1 - 130, 131 COM32, 33 - 62, 63 E RD 1 R/W WR 0 D7 0 D6 0 D5 0 D4 D D3 0 D2 0 D1 1 D0 0

21

SH1101A
20. Set VCOM Deselect Level: (Double Bytes Command) This command is to set the common pad output voltage level at deselect stage. VCOM Deselect Level Mode Set: (DBH) A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 0 D4 1 D3 1 D2 0 D1 1 D0 1

VCOM Deselect Level Data Set: (00H - FFH) A0 0 A[7:0] 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 40H - FFH E RD 1 R/W WR 0 0.430 D7 A7 D6 A6 D5 A5 A[7:0] 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH D4 A4 D3 A3 D2 A2 D1 A1 D0 A0

VCOM = X VREF = (0.430 + A[7:0] X 0.006415) X VREF

0.770 (POR)

22

SH1101A
21. Read-Modify-Write: (E0H) A pair of Read-Modify-Write and End commands must always be used. Once read-modify-write is issued, column address is not incremental by read display data command but incremental by write display data command only. It continues until End command is issued. When the End is issued, column address returns to the address when read-modify-write is issued. This can reduce the microprocessor load when data of a specific display area is repeatedly changed during cursor blinking or others. A0 0 Cursor display sequence: E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 0 D0 0

Set Page Address Set Column Address Read-Modify-Write Dummy Read No Read Data Data process Write Data

Completed?

Yes End

Figure. 6 22. End: (EEH) Cancels Read-Modify-Write mode and returns column address to the original address (when Read-Modify-Write is issued.) A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 1
Return Column address N N+1 N+2 N+3 N+m N End

D2 1

D1 1

D0 0

Read-Modify-Write mode is selected

Figure. 7

23

SH1101A
23. NOP: (E3H) Non-Operation Command. A0 0 E RD 1 R/W WR 0 D7 1 D6 1 D5 1 D4 0 D3 0 D2 0 D1 1 D0 1

24. Write Display Data Write 8-bit data in display RAM. As the column address is incremental by 1 automatically after each write, the microprocessor can continue to write data of multiple words. A0 1 25. Read Status A0 0 BUSY: E RD 0 R/W WR 1
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0

E RD 1

R/W WR 0

D7

D6

D5

D4

D3

D2

D1

D0

Write RAM data

BUSY ON/OFF

When high, the SH1101A is busy due to internal operation or reset. Any command is rejected until BUSY goes low. The busy check is not required if enough time is provided for each cycle. ON/OFF: Indicates whether the display is on or off. When goes low the display turns on. When goes high, the display turns off. This is the opposite of Display ON/OFF command. 26. Read Display Data Reads 8-bit data from display RAM area specified by column address and page address. As the column address is increment by 1 automatically after each write, the microprocessor can continue to read data of multiple words. A single dummy read is required immediately after column address being setup. Refer to the display RAM section of FUNCTIONAL DESCRIPTION for details. Note that no display data can be read via the serial interface. A0 1 E RD 0 R/W WR 1 D7 D6 D5 D4 D3 D2 D1 D0

Read RAM data

24

SH1101A
Command Table
Command A0 1. Set Column Address 4 lower bits 2. Set Column Address 4 higher bits 3. Reserved Command 4. Reserved Command 5. Reserved Command 6. Set Display Start Line 7. The Contrast Control Mode Set Contrast Data Register Set 8. Set Segment Re-map (ADC) 9. Set Entire Display OFF/ON 10. Set Normal/ Reverse Display 11. Multiplex Ration Mode Set Multiplex Ration Data Set 12. DC-DC Control Mode Set DC-DC ON/OFF Mode Set 0 RD 1 WR 0 D7 0 D6 0 Code D5 0 D4 0 D3 D2 D1 D0 Function Sets 4 lower bits of column Lower column address address of display RAM in register. (POR = 00H) Sets 4 higher bits of column Higher column address address of display RAM in register. (POR = 10H) 0 0 1 1 1 1 0 1 1 0 0 D Reserved Reserved Reserved Specifies RAM display line for COM0. (POR = 40H) 0 1 This command is to set Contrast Setting of the display. The chip has 256 contrast steps from 00 to FF. (POR = 80H) The right (0) or left (1) rotation. (POR = A0H) Selects normal display (0) or Entire Display ON (1). (POR = A4H) Normal indication (0) when low, but reverse indication (1) when high. (POR = A6H) This command switches default 63 multiplex mode to any multiplex ratio from 1 to 64. (POR = 3FH) This command is to control the DC-DC voltage DC-DC will be turned on when display on converter (1) or DC-DC OFF (0). (POR = 8BH)

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 0 0 0 1

0 0 0 0 1 0

0 1 1 1

1 0 0 0

Line address 0 0 0 0

Contrast Data 1 0 1 0 0 0 0 ADC

0 0 0 0 0

1 1 1 1 1

0 0 0 0 0

1 1 * 1 1

0 0 * 0 0

1 1

0 0

0 1

1 0

1 0

D 0

Multiplex Ratio 1 0 0 0 1 1 1 0 0 1 1 D

25

SH1101A
Command Table (Continued)
Command A0 13. Display OFF/ON 0 RD 1 WR 0 D7 1 D6 0 Code D5 1 D4 0 D3 1 D2 1 D1 1 D0 D Turns on OLED panel (1) or turns off (0). (POR = AEH) Specifies page address to load display RAM data to page address register. (POR = B0H) * 1 Scan from COM0 to COM [N - 1] (0) or Scan from COM [N -1] to COM0 (1). (POR = C0H) This is a double byte command which specifies the mapping of display start line to one of COM0-63. (POR = 00H) This command is used to set the frequency of the internal display clocks. (POR = 50H) Function

14. Set Page Address

Page Address

15. Set Common Output Scan Direction 16. Display Offset Mode Set Display Offset Data Set 17. Set Display Divide Ratio/Oscillator Frequency Mode Set Divide Ratio/Oscillator Frequency Data Set 18. Dis-charge / Pre-charge Period Mode Set Dis-charge /Pre-charge Period Data Set 19. Common Pads Hardware Configuration Mode Set Sequential/Alternat ive Mode Set 20. VCOM Deselect Level Mode Set VCOM Deselect Level Data Set 21. Read-Modify-Write 22. End 23. NOP 24. Write Display Data 25. Read Status 26. Read Display Data

0 0 0

1 1 1

0 0 0

1 1 *

1 1 *

0 0

0 1

D 0

* 0

* 1

COMx

0 0

1 1

0 0

Oscillator Frequency 1 1 0 1 1

Divide Ratio 0 0 1 This command is used to set the duration of the dis-charge and pre-charge period. (POR = 22H)

Dis-charge Period

Pre-charge Period This command is to set the common signals pad configuration. (POR = 12H)

0 0 0 0 0 0 1 0 1

1 1 1 1 1 1 1 0 0

0 0 0 0 0 0 0 1 1

0 1

0 1

0 0

D 1

0 1

0 0

1 1

0 1 This command is to set the common pad output voltage level at deselect stage. (POR = 35H) Read-Modify-Write start. Read-Modify-Write end. Non-Operation Command

VCOM ( X VREF) 1 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 0 0 1 1 0 0 1

Write RAM data


BUSY ON/ OFF

Read RAM data

Note: Do not use any other command, or the system malfunction may result.

26

SH1101A
Command Description
Instruction Setup: Reference 1. Power On and Initialization 1.1. When the built-in DC-DC pump power is being used immediately after turning on the power:

VDD1 - VSS is off VDD2 - VSS is off

Turn on the VDD1 - VSS and VDD2 - VSS power keeping the RES pin = "L"

Function setup by command input (User setup): (12) DC-DC Control set: ADH Built-in DC-DC turn on: 8BH (POR)

When the power is stabilized

Function setup by command input (User setup): (13 ) Display ON set: AFH

Release the reset state. ( RES pin = "H"). Reset timing depends on SH1101A data sheet.

Typically, 150ms delay is recommended to wait.

Initialized state (Default)

Function setup by command input (User setup): (8) Segment Re-map (ADC) selection (19) COM Sequential / Alternative Mode selection (15) COM Output Scan Direction selection (11) Multiplex Ration Mode selection (17) Display Divide Ratio / Oscillator Frequency Mode selection

Function setup by command input (User setup): (6) Display Start Line set (14) Page Address set (1, 2) Column Address set

Display Data Send

Function setup by command input (User setup): (20) VCOM Deselect Level set (7) Contrast set

Function setup by command input (User setup): Clear internal RAM to "00H"

27

SH1101A
1.2. When the external DC-DC pump power is being used immediately after turning on the power:

VDD1 - VSS is off External DC-DC is off Turn on the VDD1 - VSS power keeping the RES pin = "L" Turn on the external DC-DC Power and VPP is on.

When the power is stabilized

When the external DC-DC Power ( VPP )is stabilized . Typically, 100ms delay is recommended to wait.

Release the reset state. ( RES pin = "H"). Reset timing depends on SH1101A data sheet.

Function setup by command input (User setup): (12) DC-DC Control set: ADH Built-in DC-DC turn off: 8AH

Initialized state (Default) Function setup by command input (User setup): (13) Display ON set: AFH

Function setup by command input (User setup): (8) Segment Re-map (ADC) selection (19) COM Sequential / Alternative Mode selection (15) COM Output Scan Direction selection (11) Multiplex Ration Mode selection (17) Display Divide Ratio / Oscillator Frequency Mode selection

Typically, 50ms delay is recommended to wait.

Function setup by command input (User setup): (20) VCOM Deselect Level set (7) Contrast set

Function setup by command input (User setup): (6) Display Start Line set (14) Page Address set (1, 2) Column Address set

Display Data Send Function setup by command input (User setup): Clear internal RAM to "00H"

28

SH1101A
2. Power Off
Optional status

Function setup by command input (User setup): (13) Display OFF set: AEH Turn off the External DC-DC Power off and V PP is off.

When the external DC-DC Power (V PP) reach 0V. Typically, 100ms delay is recommended to wait.

Turn off the V DD1 - VSS and VDD2 - VSS power

29

SH1101A
Absolute Maximum Rating*
DC Supply Voltage (VDD1, VDD2) . . . . . . . .. . -0.3V to +3.6V DC Supply Voltage (VPP) . . . . . . . . . . . . . . . . -0.3V to +18V Input Voltage . . . . . . . . . . . . . . . . . . . . -0.3V to VDD1 + 0.3V Operating Ambient Temperature . . . . . . . . . -40C to +85C Storage Temperature . . . . . . . . . .. . . . . . . -55C to +125C

*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device under these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Characteristics
DC Characteristics (VSS = 0V, VDD1 = 2.4 - 3.5V TA =+25C, unless otherwise specified) Symbol VDD1 VDD2 VPP VBREF IDD1 Parameter Operating voltage Operating voltage OLED Operating voltage Internal voltage reference Dynamic current consumption 1 Dynamic current consumption 2 OLED dynamic current consumption Sleep mode current consumption in VDD1 & VDD2 Sleep mode current consumption in VPP Min. 2.4 2.4 7.0 1.20 Typ. 1.26 110 Max. 3.5 3.5 16.0 1.32 160 Unit V V V V With one 1F capacitor VDD1 = 3V, VDD2 = 3V, IREF = 10A, Contrast = 256, Bulid-in DC-DC OFF, Display ON, display data = All ON, No panel attached. VDD1 = 3V, VDD2 = 3V, VPP = 12V, IREF = -10A, Contrast = 256, Bulid-in DC-DC ON, Display ON, Display data = All ON, No panel attached. VDD1 = 3V, VDD2 = 3V, VPP = 12V, IREF = -10A, Contrast = 256, Display ON, All ON, No panel attached. During sleep, TA = +25C, VDD1 = 3V, VDD2 = 3V. During sleep, TA = +25C, VPP = 12V. VDD1 = 3V, VPP = 12V, IREF = -10A, RLOAD = 20k, Display ON. Contrast = 256. VDD1 = 3V, VPP = 12V, IREF = -10A, RLOAD = 20k, Display ON. Contrast = 176. VDD1 = 3V, VPP = 12V, IREF = -10A, RLOAD = 20k, Display ON. Contrast = 96. VDD1 = 3V, VPP = 12V, IREF = -10A, RLOAD = 20k, Display ON. Contrast = 16. ISEG1 = (ISEG - IMID)/IMID X 100% IMID = (IMAX + IMIN)/2 ISEG [0:131] at contrast = 256. ISEG2 = (ISEG [N] - ISEG [N+1])/(ISEG [N] + ISEG [N+1]) X 100% ISEG [0:131] at contrast = 256. Condition

IDD2

190

285

IPP

-308 -

550 0.01 0.01 -320 -220 -120 -20 -

825 5 5 -342 -

A A A A A A A
% %

ISP

ISEG

Segment output current -

ISEG1 ISEG2

Segment output current uniformity Adjacent segment output current uniformity

3 2

30

SH1101A
DC Characteristics (Continued)
Symbol VIHC VILC VOHC VOLC ILI IHZ fOSC fFRM Parameter High-level input voltage Low-level input voltage High-level output voltage Low -level output voltage Input leakage current HZ leakage current Oscillation frequency Frame frequency for 64 Commons Min. 0.8 X VDD1 VSS 0.8 X VDD1 VSS -1.0 -1.0 315 Typ. 360 104 Max. VDD1 0.2 X VDD1 VDD1 0.2 X VDD1 1.0 1.0 420 Unit V V V V Condition A0, D0 - D7, RD (E), WR ( R / W ), CS , CLS, CL, C86, P/S and RES . IOH = -0.5mA (D0 - D7, and CL). IOL = 0.5mA (D0 - D7, and CL). VIN = VDD1 or VSS (A0, RD (E), WR ( R / W ), CS , CLS, C86, P/S and RES ). When the D0 - D7, and CL are in high impedance.

A A

kHz TA = +25C. Hz When fOSC = 360kHz, Divide ratio = 1, common width = 54 DCLKs.

31

SH1101A
AC Characteristics
(1) System buses Read/Write characteristics 1 (For the 8080 Series Interface MPU)

A0 tAS8 tF tAH8 tR tCYC8 WR , RD tCCLW tCCLR tCCHW tCCHR

CS

tDS8 D0~D7 (WRITE) tACC8 D0~D7 (READ)

tDH8

tCH8

(VDD1 = 2.4 - 3.5V, TA = +25C) Symbol tCYC8 tAS8 tAH8 tDS8 tDH8 tCH8 tACC8 tCCLW tCCLR tCCHW tCCHR tR tF Parameter System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time RD access time Control L pulse width (WR) Control L pulse width (RD) Control H pulse width (WR) Control H pulse width (RD) Rise time Fall time Min. 300 0 0 40 15 10 100 120 100 100 Typ. Max. 70 140 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 100pF CL = 100pF Condition

32

SH1101A
(2) System buses Read/Write Characteristics 2 (For the 6800 Series Interface MPU)
A0 R/W tAS6 CS tF tEWHW tEWHR E tEWLW tDS6 D0~D7 (WRITE) tACC6 D0~D7 (READ) tOH6 tDH6 tEWLR tR tCYC6 tAH6

(VDD1 = 2.4 - 3.5V, TA = +25C) Symbol tCYC6 tAS6 tAH6 tDS6 tDH6 tOH6 tACC6 tEWHW tEWHR tEWLW tEWLR tR tF Parameter System cycle time Address setup time Address hold time Data setup time Data hold time Output disable time Access time Enable H pulse width (Write) Enable H pulse width (Read) Enable L pulse width (Write) Enable L pulse width (Read) Rise time Fall time Min. 300 0 0 40 15 10 100 120 100 100 Typ. Max. 70 140 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 100pF CL = 100pF Condition

33

SH1101A
(3) System buses Write characteristics 3(For the Serial Interface MPU)
CS tCSS tCSH

tSAS

tSAH

A0 tSCYC tSLW SCL tSHW

tF tSDS SI

tR tSDH

tF

(VDD1 = 2.4 - 3.5V, TA = +25C) Symbol tSCYC tSAS tSAH tSDS tSDH tCSS tCSH tSHW tSLW tR tF Parameter Serial clock cycle Address setup time Address hold time Data setup time Data hold time CS setup time CS hold time time Serial clock H pulse width Serial clock L pulse width Rise time Fall time Min. 250 150 150 100 100 120 60 100 100 Typ. Max. 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns Condition

(4) Reset Timing


tRW RES tR

Internal circuit status

During reset

End of reset

(VDD1 = 2.4 - 3.5V, TA = +25C) Symbol tR tRW Parameter Reset time Reset low pulse width Min. 5.0 Typ. Max. 1.0 Unit Condition

s s

34

SH1101A
Application Circuit (for reference only)
Reference Connection to MPU: 1. 8080 series interface: (Internal oscillator, External VPP)
VDD C1 + VDD1 VDD2 VCL VSL VSS SW FB SENSE VBREF C86 P/S

SH1101A

CS RES A0 WR RD D7~D0

CS RES A0 WR RD D7~D0 CL CLS C2 VCOMH

MPU

External VPP

C3 +

VREF VPP

IREF R1

Figure. 8 Note: C1 - C3: 4.7F. R1: about 910k, R1 = (Voltage at IREF - VSS)/IREF

35

SH1101A
2. 6800 Series Interface: (Internal oscillator, Built-in DC-DC)
VDD1 C6 + VDD1

VDD2 C1 + C2 L D C4 + R1 FB C5 + R2 R3 C3 + SENSE VBREF Q + VDD2 VCL VSL VSS SW

SH1101A

C86 P/S CS RES A0 R/W E D7~D0 CS RES A0 WR RD D7~D0 CL CLS C7 VCOMH

MPU

VREF VPP

IREF R4

Figure. 9 Note: L, D, Q, R1, R2, R3, C1 - C6: Please refer to following description of DC-DC module. C6, C7: 4.7F R3: about 910k, R4 = (Voltage at IREF - VSS)/IREF

36

SH1101A
3. Serial Interface: (External oscillator, External VPP)
VDD C1 + VDD1 VDD2 VCL VSL VSS SW FB SENSE VBREF C86 P/S CS RES A0 CS RES A0 WR RD SI SCL D7~D2 D1 D0 CL CLS C2 + VCOMH

SH1101A

MPU

External Clock

External VPP

C3 +

VREF VPP

IREF R1

Figure. 10 Note: C1 - C3: 4.7F R1: about 910k, R1 = (Voltage at IREF - VSS)/IREF

37

SH1101A
DC-DC:
Below application circuit is an example for the input voltage of 3V VDD2 to generate VPP of about 12V@10mA-25mA application.
L VDD2 C1 + VSS VDD2 C2 + SW C4 + Q R1 R3 D VPP

VBREF C3 + VSS

DC-DC

SENSE

FB R2 + C5

VSS

VSS

Figure. 11 Symbol L D Q R1 R2 R3 C1 C2 C3 C4 C5 10H SCHOTTKY DIODE MOSFET 930k 110k 0.12 1 - 10F 0.1 - 1F 1F 6.8F 1000pF Value Recommendation LQH3C100K24 20V@0.5A, MBR0520 N-FET with low RDS(ON) and low VTH, MGSF1N02LT1 1%, 1/8W 1%, 1/8W 1%, 1/2W Low ESR/6.3V Ceramic/16V Ceramic/16V Low ESR/16V Ceramic/16V

38

SH1101A
Bonding Diagram
9140um
269 238 237 106 105 74

xx Y

xx

SH1101A
X 1

(0,0)

Dummy Pad

948um

X 73

Pad Location (Total: 269 pads)


Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Designation VCL VCL VCL VSL VSL VSL VSS VSS VSS VSS VSS VSS VSS SW SW SW VDD2 VDD2 VDD2 VDD2 VSS FB SENSE VBREF TEST1 TEST3 TEST2 VDD1 VDD1 VDD1 X -4359.45 -4239.45 -4119.45 -3999.45 -3879.45 -3759.45 -3639.45 -3519.45 -3399.45 -3279.45 -3159.45 -3039.45 -2919.45 -2799.45 -2679.45 -2559.45 -2439.45 -2319.45 -2199.45 -2079.45 -1959.45 -1839.45 -1719.45 -1599.45 -1479.45 -1359.45 -1239.45 -1119.45 -999.45 -879.45 Y -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 Pad No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 Designation VDD1 VSS C86 VDD1 P/S VSS CL CS RES A0 WR VSS RD VDD1 VCOMH VCOMH VCOMH VCOMH VPP VPP VPP VPP VPP D0 D1 D2 D3 D4 D5 D6 X -759.45 -639.45 -519.45 -399.45 -279.45 -159.45 -39.45 80.55 200.55 320.55 440.55 560.55 680.55 800.55 920.55 1040.55 1160.55 1280.55 1400.55 1520.55 1640.55 1760.55 1880.55 2000.55 2120.55 2240.55 2360.55 2480.55 2600.55 2720.55 unit: m Y -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15

39

SH1101A
Pad Location (continued)
Pad No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Designation D7 VDD1 CLS VSS IREF VPP VCOMH VCOMH VCOMH VREF VPP VPP VPP COM62 COM60 COM58 COM56 COM54 COM52 COM50 COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10 X 2840.55 2960.55 3080.55 3200.55 3320.55 3440.55 3560.55 3680.55 3800.55 3920.55 4040.55 4160.55 4280.55 4432.95 4387.95 4342.95 4297.95 4252.95 4207.95 4162.95 4117.95 4072.95 4027.95 3982.95 3937.95 3892.95 3847.95 3802.95 3757.95 3712.95 3667.95 3622.95 3577.95 3532.95 3487.95 3442.95 3397.95 3352.95 3307.95 3262.95 Y -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 -414.15 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 Designation COM8 COM6 COM4 COM2 COM0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 X 3217.95 3172.95 3127.95 3082.95 3037.95 2947.95 2902.95 2857.95 2812.95 2767.95 2722.95 2677.95 2632.95 2587.95 2542.95 2497.95 2452.95 2407.95 2362.95 2317.95 2272.95 2227.95 2182.95 2137.95 2092.95 2047.95 2002.95 1957.95 1912.95 1867.95 1822.95 1777.95 1732.95 1687.95 1642.95 1597.95 1552.95 1507.95 1462.95 1417.95 Y 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6

40

SH1101A
Pad Location (continued)
Pad No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Designation SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 X 1372.95 1327.95 1282.95 1237.95 1192.95 1147.95 1102.95 1057.95 1012.95 967.95 922.95 877.95 832.95 787.95 742.95 697.95 652.95 607.95 562.95 517.95 472.95 427.95 382.95 337.95 292.95 247.95 202.95 157.95 112.95 67.95 22.95 -22.05 -67.05 -112.05 -157.05 -202.05 -247.05 -292.05 -337.05 -382.05 Y 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 Pad No. 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 Designation SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 X -427.05 -472.05 -517.05 -562.05 -607.05 -652.05 -697.05 -742.05 -787.05 -832.05 -877.05 -922.05 -967.05 -1012.05 -1057.05 -1102.05 -1147.05 -1192.05 -1237.05 -1282.05 -1327.05 -1372.05 -1417.05 -1462.05 -1507.05 -1552.05 -1597.05 -1642.05 -1687.05 -1732.05 -1777.05 -1822.05 -1867.05 -1912.05 -1957.05 -2002.05 -2047.05 -2092.05 -2137.05 -2182.05 Y 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6

41

SH1101A
Pad Location (continued)
Pad No. 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 Designation SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 COM1 COM3 COM5 COM7 COM9 COM11 COM13 COM15 X -2227.05 -2272.05 -2317.05 -2362.05 -2407.05 -2452.05 -2497.05 -2542.05 -2587.05 -2632.05 -2677.05 -2722.05 -2767.05 -2812.05 -2857.05 -2902.05 -2947.05 -3037.05 -3082.05 -3127.05 -3172.05 -3217.05 -3262.05 -3307.05 -3352.05 Y 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 Pad No. 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 Designation COM17 COM19 COM21 COM23 COM25 COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 COM57 COM59 COM61 COM63 X -3397.05 -3442.05 -3487.05 -3532.05 -3577.05 -3622.05 -3667.05 -3712.05 -3757.05 -3802.05 -3847.05 -3892.05 -3937.05 -3982.05 -4027.05 -4072.05 -4117.05 -4162.05 -4207.05 -4252.05 -4297.05 -4342.05 -4387.05 -4432.05 Y 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6 406.6

42

SH1101A
Dummy Pad Location (Total: 6 pads)
unit: m NO 0 1 X -4479.45 4400.55 Y -414.15 -414.15 NO 2 3 X 4522.95 4477.95 Y 406.6 406.6 NO 4 5 X -4477.05 -4522.05 Y 406.6 406.6

Alignment Mark Location


unit: m NO L R X -4195 4195 Y -344 -344

43

SH1101A
Package Information
269 238 237 106 105 74

SH1101A
1

Dummy Pad

73

Chip Outline Dimensions


unit: m Item Chip boundary Chip height Pad No. X All pads 1~73 Bump size 74~269 Dummy 0, Dummy 1 Dummy 2~ Dummy 5 Dummy 0, 1~73, Dummy 1 Dummy 2~Dummy3, 74~105 Pad pitch 106~237 238~269, Dummy 4~Dummy 5 105~106 237~238 Bump height All pads 90 15 45 90 30 90 30 120 9140 482.6 55 70 55 70 Size Y 948

44

SH1101A
Tray Information

45

SH1101A
SH1101A-TCP03 TCP Pin Layout

(Copper Side View)

46

SH1101A
SH1101A-TCP03 TCP Pin Assignment (Total: 211 pins) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Designation NC VSS SW VDD2 FB SENSE VBREF NC NC NC VDD1 C86 P/S NC CS Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Designation COM48 COM46 COM44 COM42 COM40 COM38 COM36 COM34 COM32 COM30 COM28 COM26 COM24 COM22 COM20 COM18 COM16 COM14 COM12 COM10 COM8 COM6 COM4 COM2 COM0 NC NC NC NC NC NC NC NC SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Designation SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Designation SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86

RES A0
WR RD D0 D1 D2 D3 D4 D5 D6 D7 IREF VCOMH VPP NC NC NC COM62 COM60 COM58 COM56 COM54 COM52 COM50

47

SH1101A
SH1101A-TCP03 TCP Pin Assignment (continued) Pin No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 Designation SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 NC NC NC NC NC NC Pin No. 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 Designation NC NC COM1 COM3 COM5 COM7 COM9 COM11 COM13 COM15 COM17 COM19 COM21 COM23 COM25 Pin No. 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 Designation COM27 COM29 COM31 COM33 COM35 COM37 COM39 COM41 COM43 COM45 COM47 COM49 COM51 COM53 COM55 Pin No. 206 207 208 209 210 211 Designation COM57 COM59 COM61 COM63 NC NC

Note: Following is the details of pad connection in SH1101A-TCP03 (TCP Form). CLS pad connects to VDD1 pad, Internal oscillator circuit is enabled. VREF pad connects to VPP pad. VCL & VSL pad connects to VSS pad. C86 & P/S pad options can be selected by user. So SH1101A-TCP03 (TCP Form) supports 8-bit 6800-series parallel interface, 8-bit 8080-series parallel interface or serial peripheral interface. SH1101A-TCP03 (TCP Form) supports internal DC-DC converter function.

48

SH1101A
External View of SH1101A-TCP03 TCP Pins

49

SH1101A

Cautions Concerning Storage: 1. When storing the product, it is recommended that it be left in its shipping package. After the seal of the packing bag has been broken, store the products in a nitrogen atmosphere. 2. Storage conditions: Storage state unopened (less than 90 days) After seal of broken (less than 30 days) Storage conditions Temperature: 5 to 30J ; humidity: 80%RH or less. Room temperature, dry nitrogen atmosphere

3. Don't store in a location exposed to corrosive gas or excessive dust. 4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature. 5. Don't store the product such that it subjected to an excessive load weight, such as by stacking. 6. Deterioration of the plating may occur after long-term storage, so special care is required. It is recommended that the products be inspected before use.

50

SH1101A
SH1101A-TCP06 TCP Pin Layout

(Copper Side View)

51

SH1101A
SH1101A-TCP06 TCP Pin Assignment (Total: 249 pads) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Designation NC VPP VCOMH IREF D7 D6 D5 D4 D3 D2 D1 D0 RD WR A0 RES CS NC P/S C86 VDD1 NC NC NC VBREF SENSE FB VDD2 SW VSS NC NC NC COM63 COM61 COM59 COM57 COM55 COM53 COM51 Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Designation COM49 COM47 COM45 COM43 COM41 COM39 COM37 COM35 COM33 COM31 COM29 COM27 COM25 COM23 COM21 COM19 COM17 COM15 COM13 COM11 COM9 COM7 COM5 COM3 COM1 NC NC NC NC NC NC NC SEG131 SEG130 SEG129 SEG128 SEG127 SEG126 SEG125 SEG124 Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Designation SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 SEG99 SEG98 SEG97 SEG96 SEG95 SEG94 SEG93 SEG92 SEG91 SEG90 SEG89 SEG88 SEG87 SEG86 SEG85 SEG84 Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 139 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Designation SEG83 SEG82 SEG81 SEG80 SEG79 SEG78 SEG77 SEG76 SEG75 SEG74 SEG73 SEG72 SEG71 SEG70 SEG69 SEG68 SEG67 SEG66 SEG65 SEG64 SEG63 SEG62 SEG61 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44

52

SH1101A
TCP Pin Assignment (continued) Pin No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 Designation SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 Pin No. 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 Designation SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 NC NC Pin No. 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 Designation NC NC NC NC NC NC NC NC NC COM0 COM2 COM4 COM6 COM8 COM10 COM12 COM14 COM16 COM18 COM20 COM22 COM24 COM26 Pin No. 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 Designation COM28 COM30 COM32 COM34 COM36 COM38 COM40 COM42 COM44 COM46 COM48 COM50 COM52 COM54 COM56 COM58 COM60 COM62 NC NC

Note: Following is the details of pad connection in SH1101A-TCP06 (TCP Form). CLS pad connects to VDD1 pad, Internal oscillator circuit is enabled. VREF pad connects to VPP pad. VCL & VSL pad connects to VSS pad. C86 & P/S pad options can be selected by user. So SH1101A-TCP06 (TCP Form) supports 8-bit 6800-series parallel interface, 8-bit 8080-series parallel interface or serial peripheral interface. SH1101A-TCP06 (TCP Form) supports internal DC-DC converter function.

53

SH1101A
External View of SH1101A-TCP06 TCP Pins

54

SH1101A

PATTERN SIDE S/R ADHESIVE

UP I LEX-S

UP I LEX-S

BACKSIDE Flex Coating

Cautions Concerning Storage: 1. When storing the product, it is recommended that it be left in its shipping package. After the seal of the packing bag has been broken, store the products in a nitrogen atmosphere. 2. Storage conditions: Storage state unopened (less than 90 days) After seal of broken (less than 30 days) Storage conditions Temperature: 5 to 30J ; humidity: 80%RH or less. Room temperature, dry nitrogen atmosphere

3. Don't store in a location exposed to corrosive gas or excessive dust. 4. Don't store in a location exposed to direct sunlight of subject to sharp changes in temperature. 5. Don't store the product such that it subjected to an excessive load weight, such as by stacking. 6. Deterioration of the plating may occur after long-term storage, so special care is required. It is recommended that the products be inspected before use.

55

SH1101A
Ordering Information
Part No. SH1101A-COG01 SH1101A-TCP03 SH1101A-TCP06 Package Gold bump on chip tray TCP Form TCP Form

56