PDF VLSI DSP Embedded System Design

Embedded System Design Using FPGAs
Copyright 2005 Altera Corporation
Agenda
Traditional Embedded System Design Embedded Processor in FPGAs Design Flow with FPGAs Conclusion
Embedded Systems
Computing Systems inside a specific device application Embedded System = Embedded Processor + Peripherals + Software Must Work in Real Time ! Usually Responds to External Stimulus
Incoming Call on a Cell Phone
Design Flow
System Specification Algorithm Modeling HW/SW Partitioning Processor System Specification Selection Peripheral Algorithm Modeling Design Custom IP HW/SW Partitioning Design HW/SW HW Integration System HW Validation RTOS Selection Data Flow & Control Flow Development Driver Development SW Integration Verify using Emulation/Simulation Model
HW/SW Integration System Validation
Nios II Embedded Processor
What is Nios II?

Alteras Second Generation Soft-Core 32 Bit RISC Microprocessor
Nios II Plus Internally By Altera - Developed All Peripherals Written In HDL Can Be Targeted For All Altera FPGAs - Harvard Architecture Synthesis Using Quartus II Integrated Synthesis - Royalty-Free
Avalon Switch Fabric
Cache
Nios II CPU
Debug
UART GPIO Timer SPI SDRAM Controller
On-Chip ROM On-Chip RAM
FPGA
6 Copyright 2005 Altera Corporation
Nios II Block Diagram

Nios II Processor Core
reset clock
JTAG interface to Software Debugger HardwareAssisted Debug Module Program Controller & Address Generation Exception Controller General Purpose Registers r0 to r31 Instruction Master Port Instruction Cache
irq[31..0]
Interrupt Controller
Control Registers ctl0 to ctl4 Data Master Port
Custom I/O Signals
Custom Instruction Logic
Arithmetic Logic Unit
Data Cache
Nios II: Faster & Smaller

250 200
Performance (DMIPS)
Fast 4X Faster
150 100 50
Economy 50% Smaller Standard 10% Smaller Over 2X Faster
0 0
Results Based on Stratix II FPGA Copyright 2005 Altera Corporation
500
1000
CPU Core Size (Logic Elements)
1500
2000
Binary Compatibility / Flexible Performance

Nios II /f Fast
Pipeline H/W Multiplier & Barrel Shifter Branch Prediction Instruction Cache Data Cache Logic Usage (Logic Elements) Custom Instructions 6 Stage 1 Cycle Dynamic Configurable Configurable 1400 - 1800
Nios II /s Standard
5 Stage 3 Cycle Static Configurable None 1200 1400 Up to 256
Nios II /e Economy
None Emulated In Software None None None 600 700
Hardware Multiplier Acceleration

Nios II Economy version - No Multiply Hardware
Uses GNUPro Math Library to Implement Multiplier
Nios II Standard - Full Hardware Multiplier

32 x 32 32 in 3 Clock Cycles if DSP block present, else uses software only multiplier
Nios II Fast - Full Hardware Multiplier

32 x 32 32 in 1 Clock Cycles if DSP block present, else uses software only multiplier Acceleration Clock Cycles Hardware (32 x 32 32)
None Standard MUL in Stratix Fast MUL in Stratix
250 3 1
Nios II: Hard Numbers

Nios II/f Stratix II
200 DMIPS @ 175MHz 1180 LEs 1 of 8 DSP 4K Icache, 2K Dcache Stratix 2S10-C5 150 DMIPS @ 135MHz 1800 LEs 1 of 8 DSP 4K Icache, 2K Dcache Stratix 1S10-C5 100 DMIPS @ 125MHz 1800 LEs 4K Icache, 1K Dcache Cyclone 1C4-C6
Nios II/s
90 DMIPS @ 175MHz 800 LEs 4K Icache, No Dcache Stratix 2S10-C5 67 DMIPS @ 135MHz 1200 LEs 4K Icache, No Dcache Stratix 1S10-C5 62 DMIPS @ 125MHz 1200 LEs 2K Icache, No Dcache Cyclone 1C4-C6
Nios II/e
28 DMIPS @ 190MHz 400 LEs No Icache, No Dcache Stratix 2S10-C5 22 DMIPS @ 150MHz 550 LEs No Icache, No Dcache Stratix 1S10-C5 20 DMIPS @ 140MHz 550 LEs No Icache, No Dcache Cyclone 1C4-C6
Stratix
Cyclone
* FMax Numbers Based Reference Design Running From On-Chip Memory (Nios II/f 1.15 DMIPS / MHz)
11
Peripherals for Nios II

Memory Interfaces
EPCS Flash Controller On-Chip
RAM, ROM
Serial Peripheral Interface

SPI
Off-Chip
SRAM CFI Flash
SDRAM Controller DMA UART Timers
Parallel l/O JTAG UART LCD Display Ethernet Port System ID Peripheral Interface to User Logic Interface to Altera IP
12
Nios II System Architecture

Instr. Nios II CPU On-Chip Debug Core Data Interrupt Controller Wait State Generation GPIO 0 Off-Chip Software Trace Memory Data in Multiplexer Master Arbitration Dynamic Bus Sizing Address Decoder Avalon Master/ Slave Port Interfaces UART 0 UART n Timer 0
Timer n
SPI 0
SPI n
GPIO n
DMA 0
DMA n
Memory Interface Memory Interface User-Defined User-Defined Interface Interface


Proprietary interconnect specification used with Nios II Principal design goals
Low resource utilization for bus logic Simplicity Synchronous operation
Nios II Processor
Address (32)
Switch PIO
Transfer Types
Slave Transfers Master Transfers Streaming Transfers Latency-Aware Transfers Burst Transfers
32-Bit Nios II Processor
Read
Write Data In (32) Data Out (32)
LED PIO
7-Segment LED PIO
IRQ IRQ #(6)
PIO-32
UserDefined Interface
ROM
(with Monitor)
UART
Timer
14

Custom-Generated for Peripherals
Contingencies are on a Per-Peripheral Basis System is Not Burdened by Bus Complexity
SOPC Builder Automatically Generates

Arbitration Address Decoding Data Path Multiplexing Bus Sizing Wait-State Generation Interrupts
15
Avalon Master Ports

Initiate Transfers with Avalon Switch Fabric Transfer Types
Fundamental Read Fundamental Write
All Avalon Masters Must Honor a waitrequest signal Transfer Properties

Latency Streaming Burst
16
User-Defined Custom Peripherals What if I need to add a peripheral not included with the Nios II system?
user wants to add own peripheral to perform some kind of proprietary Expand or accelerate system capabilities
Avalon switch fabric allows easy interface to custom peripherals
17
Custom Instructions
Augment Nios II Instruction Set
Mux User Logic Into ALU Path of Processor Pipeline
18
FPGA Hardware Design Flow

Design Specification
Design Entry/RTL Coding

RTL Simulation
- Behavioral or Structural Description of Design

Functional - FunctionalSimulation (Modelsim, Simulation (Modelsim, Quartus II) Quartus II) Verify Logic Model & Data Flow - Verify Logic Model & Data Flow (No Timing Delays) (No Timing Delays)
SOPC Builder
LE
M4K
M512
Synthesis
I/O
- Translate Design into Device Specific Primitives - Optimization to Meet Required Area & Performance Constraints - Spectrum, Synplify, Quartus II
Place & Route

- Map Primitives to Specific Locations Inside Target Technology with Reference to Area & Performance Constraints - Specify Routing Resources to Be Used
FPGA Hardware Design Flow

tclk
Timing Analysis
- Verify Performance Specifications Were Met - Static Timing Analysis
Gate Level Simulation

- Timing Simulation - Verify Design Will Work in Target Technology
Test FPGA on PC Board

- Program & Test Device on Board - Use SignalTap II for Debugging
20
SOPC Builder System Contents Page
Altera, Partner & User Cores

Processors Memory Interfaces Peripherals Bridges Hardware Accelerators Import User Logic (ie. custom peripherals)
Over 60 Cores Available Today
Web-Based IP Deployment
21
Nios II CPU Configured in SOPC Builder

Hardware designer selects which Nios II version to use when creating system
22
Selecting JTAG Debug Core

Configuration is chosen when hardware designer selects appropriate Nios II processor core
23
SOPC Builder More cpu Settings Page
24
SOPC Builder System Generation Page
25
SOPC Builder Produces a .PTF File

Text file that records SOPC Builder edits Describes Nios II System Used by software development tools
26
Integrate SOPC Builder O/P in Quartus II

Integrate SOPC Builder block symbol to Quartus II schematic (as shown below) and compile design Or, instantiate top module into your HDL design and compile
27
Project Directories
Hardware
HDL Source & Netlist db - Quartus project database
Software
Application source code Library files
Simulation
Testbench Automatically generated test memory and vectors
28
RTL Simulation
Nios II SOPC Builder Automatically Creates Simulation Models Plus:
ModelSim Project Testbench Simulation Scripts
Set Simulation Option

Simulation TestBench
Ethernet MAC/PHY Dev board SRAM Dev board FLASH Compact FLASH SDRAM
Nios II Processor
Address (32)
32-Bit Nios II Processor
Read Write Data In (32) Data Out (32)
Tri-State Bridge
Tri-State Bridge
Compact Flash PIOs
SDRAM Controller
On Chip ROM)
On Chip RAM
Custom Instruction UART
IRQ IRQ #(6)
User Defined Peripheral
User Defined Interface
Clock
Reset
User Device
User Peripheral
Included Not Included
30
User Device
User Additions to Nios II TestBench

SOPC Builder creates testbench embedded in top level file eg NiosII.v Sections within this file are reserved to add user files and code These sections are preserved if the SOPC builder is used to regenerate the Nios II system
31
Running an RTL Simulation

Launch ModelSim from Nios II IDE:
Highlight Software Project In C/C++ Projects panel Right click Run As Nios II ModelSim
32
Running an RTL Simulation
33
SignalTap II Logic Analyzer

Up to 200 MHz Multi-Analyzer Support 1,024 Channels 128K Samples 10 Trigger Levels No Probes! Can be used simultaneously with the Nios II IDE debugger and the FS2 console!
Capture the state of internal nodes In-system, at full system speeds

SignalTap II Logic Analyzer
35
Nios II Software Development
SOPC Builder Flow

SOPC Builder GUI
Processor Library Peripheral Library Configure Processor Select & Configure Peripherals, IP Connect Blocks
HDL Source Files Testbench
Custom Instructions IP Modules
Hardware Development
Software Development
Nios II IDE
C Header files Custom Library Peripheral Drivers
Generate
Hardware Configuration File Executable Code
Synthesis & Fitter
Verification & Debug

JTAG, Serial, or Ethernet
Compiler, Linker, Debugger
User Design Other IP Blocks
User Code
Quartus II
Altera PLD
On-Chip Debug
Software Trace Hard Breakpoints SignalTap II
Libraries RTOS
GNU Tools
37
Nios II IDE (Integrated Development Environment)*

Leading Edge Software Development Tool Target Connections
Hardware (JTAG) Instruction Set Simulator ModelSim-Altera Software
Advanced Hardware Debug Features

Software and Hardware Break Points, Data Triggers, Trace
Flash Memory Programming Support

* Based on Eclipse Project
Opening the Nios II IDE

Launch the Nios II IDE from the SOPC Builder or from the Windows Start menu
39
Nios II IDE
List of Open Projects
File Viewer Window (for C code, C++, and assembly*)
Terminal window
40
Note: C++ files must have extension .cpp In-line assembly code offset by asm();
Nios II IDE C/C++ Projects/Navigator

Lists all open projects Displays source files associated with project List all open and closed projects Allows you to drag and drop new files into existing projects
41
Creating a C/C++ Application

File > New > Project
42
Creating a C/C++ Application

Link to a System Library - Select a pre-existing library - Or create a new library
43
This Creates Two Software Projects

- Application and System Library Project
Application Project
- contains application source code
System Library Project

- contains system header file, etc.
Drivers Directory
- contains all device drivers DO NOT DELETE !
44
Application and System Library Projects

Application Projects build executables System Library Projects contain interface to the hardware
Nios II device drivers (Hardware Abstraction Layer) Optional RTOS (MicroC/OS-II) Optional software components (Lightweight TCP/IP stack, Read Only Zip File System)
45
Other New Project Options

System Library
Only creates system library project Build C applications upon this later
Advanced C/C++ Project

Disable automatic tool features like makefile and linker script generation User defines own instead
Managed Library Project

Facilitates software library development Enables you to associate precompiled code into an Application Project Tool writes makefile for included files
46
Project Properties
Both Application and System Library have Properties pages
47
System Library Options

Select memory Specify theRTOS Partitionstdio devicesmap
48
Software Compilation
To compile a software application, highlight your project and select Build Project from the Projects menu
49
Directory Structure After Compilation

Application Project System Library Project
50
Hardware Abstraction Layer

A lightweight runtime environment for Nios II software
Provides a level of abstraction between application code and low level hardware
HAL libraries are generated by Nios II IDE A HAL contains:

device drivers initialization software file system stdio, stderr
51

Provides generic device models for classes of peripherals common in embedded systems
eg. timers, I/O peripherals, etc.
Gives a consistent POSIX-like API, regardless of underlying hardware Make programming as familiar as possible to software engineers who may not be familiar with the specific peripheral architectures
ANSI C (through the Newlib library) UNIX style interface (i.e. POSIX like) Altera extensions where standards dont exist or were inappropriate (watch for the alt_* extension)
52

Key features of the HAL
Uses standard interfaces where appropriate Close integration with the Newlib ANSI C library http://sources.redhat.com/newlib/ Device drivers automatically configured to match the PTF Drivers initialised before main() Scalable (i.e. packs down small) Clear distinction between system and application software
53
Nios II HAL: Runtime Library

The HAL UNIX Style Functions are the glue between the C library and the device drivers
User Program
HAL API _exit() close() closedir() fstat() getpid() gettimeofday() ioctl() isatty() kill() lseek() open() opendir read() readdir() rewinddir() sbrk() settimeofday() stat() usleep() wait() write()
C Standard Library C Standard Library
HAL API
Device Driver Device Driver Device Driver
Nios II Processor System Hardware
54
HAL File System

/
/dev
/mnt
/dev/jtag_uart0
/dev/lcd0
/mnt/rozipfs
/mnt/rozipfs/myfile1
Device names match those set in SOPC builder. Can only access nodes, not directories. All paths must be absolute (no current directory)
/mnt/rozips/myfile21
55
Familiar File/Device Access

ANSI C:
fp = fopen (/dev/lcd0, w); fprintf (fp, %s, msg);
UNIX Style:
fd = open (/dev/lcd0, O_WRONLY); write (fd, msg, strlen(msg));
Newlib also supports C++ streams:

ofstream ofp(/dev/lcd0, ios::out); ofp << msg;
Existing code (outside the Nios world) uses these interfaces. Porting is now much easier. Use of existing standards means theres nothing new to learn.
HAL System Header File

SOPC Builder System Contents
system.h
System Library Settings

system.h
Contains macro definitions for system parameters, including peripheral configuration, for instance:
Hardware configuration of the peripheral Base address IRQ priority (if any) Symbolic name for peripheral
Does not include: static information, function prototypes, or device structures (unlike the old excalibur.h) Located in the syslib project directory Rarely necessary to include it explicitly in your application code, which improves rebuild time
58
system.h - example
Defines system settings and peripheral configurations:
Replaces excalibur.h (from Nios)
/* * system configuration * */ #define ALT_SYSTEM_NAME "std_1s10ES" #define ALT_CPU_NAME "cpu" #define ALT_CPU_ARCHITECTURE "altera_nios2" #define ALT_DEVICE_FAMILY "STRATIX" #define ALTERA_NIOS_DEV_BOARD_STRATIX_1S10_ES #define ALT_STDIN "/dev/jtag_uart" #define ALT_STDOUT "/dev/jtag_uart" #define ALT_STDERR "/dev/jtag_uart" #define ALT_CPU_FREQ 50000000 #define ALT_CPP_CONSTRUCTORS #define ALT_IRQ_BASE NULL
. . .
/* * button_pio configuration * */ #define BUTTON_PIO_NAME "/dev/button_pio" #define BUTTON_PIO_TYPE "altera_avalon_pio" #define BUTTON_PIO_BASE 0x00920830 #define BUTTON_PIO_IRQ 2 #define BUTTON_PIO_HAS_TRI 0 #define BUTTON_PIO_HAS_OUT 0 #define BUTTON_PIO_HAS_IN 1 #define BUTTON_PIO_CAPTURE 1 #define BUTTON_PIO_EDGE_TYPE "ANY" #define BUTTON_PIO_IRQ_TYPE "EDGE" #define BUTTON_PIO_FREQ 50000000
. . .
HAL References
Each HAL project references library routines and drivers for the components included in your Nios II system
60
Reading/Writing Hardware in Nios

Nios Classic used volatile pointers to access hardware e.g.
volatile *my_led_pointer = (int *) LED_BASE;
Volatiles will no longer provide access to hardware registers in Nios II

They are still used to tell the compiler not to optimize code No longer disable cache access
61
Reading/Writing Hardware in Nios II

Instead use I/O macros to access hardware
I/O macros bypass the cache for hardware accesses They set bit 31 of address bus high (ie. control bit) IORD(BASE, REGNUM) Reads value at register REGNUM offset from base address BASE IOWR(BASE,REGNUM,DATA) Writes DATA to register REGNUM offset from base address BASE
BASE BASE+2 BASE+4
REGNUM = 0 REGNUM = 1 REGNUM = 2 REGNUM = 3 REGNUM = 4
Header Files for Nios II Peripherals

Each Nios II peripheral has specific read/write macros for each register
Example: UART (altera_avalon_uart_regs.h)
#define IORD_ALTERA_AVALON_UART_RXDATA(base) #define IOWR_ALTERA_AVALON_UART_RXDATA(base, data) IORD(base, 0) IOWR(base, 0, data)
#define IORD_ALTERA_AVALON_UART_TXDATA(base) #define IOWR_ALTERA_AVALON_UART_TXDATA(base, data)
IORD(base, 1) IOWR(base, 1, data)
#define IORD_ALTERA_AVALON_UART_STATUS(base) #define IOWR_ALTERA_AVALON_UART_STATUS(base, data)
IORD(base, 2) IOWR(base, 2, data)
63
Interrupts
HAL API for ISRs - Functions
alt_irq_register()
Associates interrupt with your ISR function.
alt_irq_disable_all()
Disables all IRQs
alt_irq_enable_all()
Enables all IRQs
alt_irq_interruptible()
Used in ISR function body. Allows ISR to be interrupted by higher priority IRQs.
alt_irq_non_interruptible()
Used to make ISRs uninterruptible (default behavior).
HAL API for ISRs - Useful Info

sample_isr ( void* context, alt_u32 id);
Write your ISR (Follow prototype)
id == irq number (0 to 31) context == void pointer to data produced by or consumed by ISR.
alt_irq_register ( alt_u32 id, void* context, void (*irq_handler) (void*, alt_u32));
Register your ISR Using alt_irq_register()
Sample Usage: alt_irq_register ( 3, &some_data, sample_isr);
65
HAL API for ISRs - Useful Info

Creating interruptible code blocks in ISR Use alt_irq_interruptible() & alt_irq_non_interruptible() Do not use standard C library or RTOS software functions inside ISR that may pend for any reason
Eg. printf()
Keep it simple. Use ISR to trigger execution of slow processing tasks outside of interrupt context Do NOT perform these tasks within ISR References: Exception Handling Chapter in Nios II Software Developers Handbook
66
Software Run & Debug
Software Run and Debug

Nios II Run Nios II IDE JTAG Debugger Nios II ISS Nios II Console Third Party tools
68
Running Code On A Target

Nios II IDE can be used to download code to target board
69
Running Code On A Target

Download messages, stdout and stdin appear in console window
70
Nios II IDE Run Options

Nios II IDE > Run > Run
71
System ID Peripheral Revisited

When downloading code to a target, Nios II IDE computes expected System ID peripheral values from PTF file
If computed ID values do not match System ID variables stored on the target board then an error is flagged Generally, to fix this you should recompile your hardware
72
Nios II IDE JTAG Debugger

Requirements
Must have JTAG Debug Core enabled in CPU
73
Nios II IDE Debug Perspective
Basic Debug
Run Controls Stack View Active Debug Sessions
Double-click to add breakpoints
Memory View
Variables Registers Signals
74
Nios II IDE Debugger

Step Return Step Over Step Into Step with Filters
Disconnect Terminate Suspend Resume Run last Configuration Debug last Configuration
75
Nios II IDE Debugger

Standard debug windows
memory registers Variables breakpoints expressions signals
76
Nios II Instruction Set Simulator

Instruction Set Simulators are software models of an Instruction Set Architecture
Generally used to debug code if a target board is unavailable. Provides limited models of a few hardware peripherals.
Timer UART Memory (flash, SDRAM, on-chip, etc)
77

Launch an ISS Debug session from the Run Menu
78

Targets .elf file to ISS and opens debugger
Application can then be debugged as normal
79
Customizing Views in the IDE GUI

You can turn windows on or off in either the Run or Debug Perspective
80
Nios II SDK Shell

SDK shell is still provided with Nios II Used to support legacy SDK flow (eg.. n2b, n2c) as well as other general commands Can launch terminal to interface to JTAG UARTs nios2-terminal And compile code nios2-elf-gcc
81
Nios II / FS2 Console

Command line debugger
82
Nios II Console Launch

FS2 Console Launches then minimizes
83
Nios II Console
Allows for hardware breakpoints and trace data
2 HWBPs and 16 Frames of OnChip Trace Included
Displays C Source, Assembly, Mixed
84
Nios II Debug Solutions

Product
* Nios II IDE
Provider
Altera
Description
Features
IDE / Debugger JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace, FS2 Trace Probe IDE / Debugger JTAG Target Connection, H/W Breakpoints, Data Triggers, On-Chip Trace , FS2 Trace Probe Debugger Supports FS2 ISA-Nios/T
** code|lab
ATI Mentor
Watchpoint
Sophia Systems First Silicon Solution (FS2)
ISA-Nios/T
JTAG Trace Probe
External Trace Capture, Timestamp, Complex Data Triggers
* Included in Nios II Development Kits ** Evaluation Version Included in Nios II Development Kits
Upgrades from FS2

(see www.fs2.com for details)
Feature
Hardware Execution Breakpoints Data Triggers Trace (PC) Trace (Load / Store) Trace (Timestamp) Target Connection Cost
Nios II IDE
2 2 On-Chip 16 Frames No No Altera USB/B Blaster Included
FS2 S/W Upgrade

4 4 On-Chip 128 Frames Yes No Altera USB/B Blaster See FS2
FS2 H/W Upgrade

4 4 Off-Chip 128K Frames Yes Yes FS2 Black Box (USB, Ethernet) See FS2
86
FS2 System Analyzer Upgrade

ISA-Nios II System Analyzer
10-pin JTAG Target Connection Unlimited Software Breakpoints 2 Hardware Breakpoints (upgradable to 4) Supports On-Chip Trace (upgrades available for deeper trace)
ISA-Nios II/T System Analyzer

38-pin Mictor Connection Blackbox probe Supports 128k frames Off-Chip Trace in addition to Unlimited On-Chip Trace
87
User Logic Interfaces
How to Add Your Logic to Nios II?

Custom peripheral
Behaves like a peripheral to the Avalon Bus More Flexible than Custom Instruction
Custom Instruction
Add your logic to the ALU Stalls the CPU while running the Instruction
89
Custom Peripheral Interface

No Need to Worry about Bus Interface Implement Only Signals Needed Peripherals Adapted to by Avalon Switch Fabric Avalon Switch Fabric Timing Handled Automatically Register File Fabric Created for You User Arbiters Generated for You
Logic
Concentrate Effort on Peripheral Functionality!

New Component Editor
91
Creates Interface
Connect to Existing HDL or board component Map into Nios II Memory Space Can be Inside or Outside Nios II System
I/O Nios II CPU Avalon I/O I/O I/O Interface to User Logic External User Peripheral Nios II CPU Avalon I/O I/O I/O I/O Internal User Peripheral
Nios II System Module
Nios II System Module
92
Create External Component Interface

To communicate with off-chip peripherals Base interface type on data sheet
AMD29LV065AD CFI Flash Chip
93
Or Add HDL Files

For peripheral that has been encoded for FPGA
94
Summary
Nios II - Leads The Industry

Highest Highest Performance Performance Multi-Processor Hardware Acceleration Custom Instructions
Greatest Greatest Flexibility Flexibility
Processors Peripherals Optimized Interconnect SOPC Builder Nios II IDE On-Chip Processor Debug SignalTap II Logic Analyzer Concept to System in Minutes FPGA > HardCopy Structured ASIC
Most Powerful Most Powerful Design Tools Design Tools
Fastest Time Fastest Time to Market to Market
96

PDF VLSI DSP Embedded System Design

Diunggah oleh

Informasi Dokumen

Deskripsi Asli:

Hak Cipta

Format Tersedia

Bagikan dokumen Ini

Bagikan atau Tanam Dokumen

Opsi Berbagi

Apakah menurut Anda dokumen ini bermanfaat?

Apakah konten ini tidak pantas?

Hak Cipta:

Format Tersedia

PDF VLSI DSP Embedded System Design

Diunggah oleh

Hak Cipta:

Format Tersedia

Embedded System Design Using FPGAs

Copyright 2005 Altera Corporation

Copyright 2005 Altera Corporation

Copyright 2005 Altera Corporation

HW/SW Integration System Validation

Copyright 2005 Altera Corporation

Nios II Embedded Processor

Copyright 2005 Altera Corporation

What is Nios II?

UART GPIO Timer SPI SDRAM Controller

On-Chip ROM On-Chip RAM

Nios II Block Diagram

Control Registers ctl0 to ctl4 Data Master Port

Custom I/O Signals

Custom Instruction Logic

Arithmetic Logic Unit

Copyright 2005 Altera Corporation

Nios II: Faster & Smaller

Binary Compatibility / Flexible Performance

Copyright 2005 Altera Corporation

Hardware Multiplier Acceleration

Nios II Standard - Full Hardware Multiplier

Nios II Fast - Full Hardware Multiplier

Nios II: Hard Numbers

Copyright 2005 Altera Corporation

Peripherals for Nios II

Serial Peripheral Interface

SDRAM Controller DMA UART Timers

Copyright 2005 Altera Corporation

Nios II System Architecture

Memory Interface Memory Interface User-Defined User-Defined Interface Interface

Avalon Switch Fabric

Avalon Switch Fabric

32-Bit Nios II Processor

Avalon Switch Fabric

Write Data In (32) Data Out (32)

7-Segment LED PIO

IRQ IRQ #(6)

Copyright 2005 Altera Corporation

Avalon Switch Fabric

SOPC Builder Automatically Generates

Copyright 2005 Altera Corporation

Avalon Master Ports

All Avalon Masters Must Honor a waitrequest signal Transfer Properties

Copyright 2005 Altera Corporation

Avalon switch fabric allows easy interface to custom peripherals

Copyright 2005 Altera Corporation

Copyright 2005 Altera Corporation

FPGA Hardware Design Flow

Design Entry/RTL Coding

- Behavioral or Structural Description of Design

Place & Route

FPGA Hardware Design Flow

Gate Level Simulation

Test FPGA on PC Board

Copyright 2005 Altera Corporation

SOPC Builder System Contents Page

Altera, Partner & User Cores

Over 60 Cores Available Today

Copyright 2005 Altera Corporation

Nios II CPU Configured in SOPC Builder

Copyright 2005 Altera Corporation

Selecting JTAG Debug Core