The Pennsylvania State University The Graduate School

TOWARD UNDERSTANDING THE ELECTRICAL PROPERTIES OF METAL/SEMICONDUCTOR SCHOTTKY CONTACTS: THE EFFECTS OF BARRIER INHOMOGENEITIES AND GEOMETRY IN BULK AND NANOSCALE STRUCTURES

A Dissertation in Engineering Science and Mechanics by Karthik Sarpatwari

2009 Karthik Sarpatwari

Submitted in Partial Fulllment of the Requirements for the Degree of

Doctor of Philosophy

August 2009

UMI Number: 3381001

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The thesis of Karthik Sarpatwari was reviewed and approved by the following:

Osama O. Awadelkarim Professor of Engineering Science and Mechanics Dissertation Co-Advisor, Co-Chair of Committee Suzanne Mohney Professor of Materials Science and Engineering Dissertation Co-Advisor, Co-Chair of Committee Bernhard R. Tittmann Professor of Engineering Science and Mechanics Schell Professor Samia A. Suliman Assistant Professor of Engineering Science and Mechanics Suman Datta Associate Professor of Electrical Engineering Judith A. Todd P. B. Breneman Department Head of Engineering Science and Mechanics

Signatures are on le in the Graduate School.

Abstract

The work presented in this thesis comprises of two parts. Part I deals with Schottky contacts to the wide bandgap (WBG) semiconductors SiC, GaN and ZnO. These semiconductors oer great promise for a wide variety of electronic and optoelectronic applications. Schottky barriers to WBG semiconductors are attractive in particular for high temperature/high power diodes, photodetectors, and gas sensors. However, the Schottky barriers exhibit non-ideal behavior, due in part to inhomogeneities originating from immature crystal growth and device processing technologies. Apart from being a versatile electronic component, the Schottky diode is a valuable test structure. The Schottky contact is routinely used to probe substrate and epilayer quality by dierent electrical characterization techniques. It is well established that the current-voltage-temperature (I-V -T ) characteristics of Schottky contacts are routinely aected by the presence of barrier height inhomogeneities (BHI). Consequently, Schottky diode parameters such as the Schottky barrier height and the Richardson constant extracted using the I-V -T measurements can deviate from their actual values. The eects of BHI on the extracted Schottky barrier height have been studied in the literature. However, the eects of BHI on the Richardson constant have not been thoroughly explored and are the focus of the rst part of this thesis. Based on the inhomogeneous Schottky barrier model provided by Tung, a new method for the extraction of the Richardson constant is developed. The new method is applied to the Richardson constant determination of n-type ZnO and GaN. Excellent agreement with the theoretical value is obtained in both cases. The advent of the nanoelectronics era has resulted in the Schottky contact evolving from the relatively simple, planar structure into a more complex structure.

iii

Compared to bulk Schottky contacts, the Schottky barrier properties are expected to be widely dierent at the nanoscale. For example, the I-V characteristics of nanoscale Schottky contacts are aected by the contact size and geometry. Due to the increased surface-to-volume ratio, the conduction properties of nanoscale Schottky contacts are also inuenced by surface conditions such as surface charge and traps. Depending on contact size, geometry and surface conditions, an enhanced tunneling current contribution can be expected, further distorting the I-V characteristics from the simple thermionic emission model. Determination of the true Schottky barrier height in nanoscale contacts to semiconductor nanowires is important from both technological and fundamental scientic perspectives. In the second part of this thesis, we employ a simulation-based approach to study the conduction properties of an axial Schottky nanocontact to a surround-gate nanowire. A systematic study of the eects of surface charge on the I-V characteristics of the axial nano Schottky/nanowire system is undertaken. Based on the study, a method is proposed to extract the true Schottky barrier height from the I-V characteristics. The proposed method can serve as a valuable aid for interpreting experimental I-V data and can facilitate exploration of size eects on the Schottky barrier formation at the nanoscale.

iv

Table of Contents

List of Figures List of Tables Acknowledgments Chapter 1 Schottky barrier: Modeling and Physics 1.1 Semiconductor surface . . . . . . . . . . . . . . . . 1.2 MS interface . . . . . . . . . . . . . . . . . . . . . . 1.2.1 Gap state models . . . . . . . . . . . . . . . 1.3 Carrier transport . . . . . . . . . . . . . . . . . . . 1.3.1 Thermionic emission . . . . . . . . . . . . . 1.3.2 Observation of BHI . . . . . . . . . . . . . . 1.4 BHI framework . . . . . . . . . . . . . . . . . . . . 1.4.1 Zero-order model . . . . . . . . . . . . . . . 1.4.2 First-order interacting model . . . . . . . . 1.5 WBG semiconductors . . . . . . . . . . . . . . . . . 1.5.1 Substrate growth processes . . . . . . . . . . 1.5.2 Doping, etching and annealing processes . . 1.6 Contacts to WBG semiconductors . . . . . . . . . . 1.7 Thesis organization: Part I . . . . . . . . . . . . . . 1.8 Contacts at nano dimensions . . . . . . . . . . . . . 1.8.1 Scaling of Schottky contacts . . . . . . . . . 1.8.2 Interface and surface eects . . . . . . . . . 1.8.3 Size and geometry eects . . . . . . . . . . . 1.9 Thesis organization: Part II . . . . . . . . . . . . .

viii xii xiii 1 1 4 5 10 11 15 17 17 18 27 28 29 31 34 35 35 36 38 40

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Chapter 2 Minority carrier injection 42 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.2 Experimental procedure . . . . . . . . . . . . . . . . . . . . . . . . 44

2.3

2.4

2.2.1 Diode fabrication . . . . Electrical characterization . . . 2.3.1 I-V and C-V . . . . . . 2.3.2 Transient measurements Results and Discussion . . . . .

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44 47 47 48 51

Chapter 3 Eects of barrier height inhomogeneities son constant determination 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 3.2 Review of existing methods . . . . . . . . . . . . . 3.2.1 Temperature dependence of B . . . . . . . 3.2.2 Flat band barrier height analysis . . . . . . 3.2.3 Werner and Gttlers model . . . . . . . . . u 3.2.4 Tungs model . . . . . . . . . . . . . . . . . 3.3 Extended inhomogeneity analysis . . . . . . . . . . 3.3.1 n-B and T0 analysis . . . . . . . . . . . . . 3.3.2 Richardson plot . . . . . . . . . . . . . . . . 3.3.3 Application of existing methods . . . . . . . 3.4 Proposed approach . . . . . . . . . . . . . . . . . . 3.5 Application to IrOx /n-ZnO I-V -T characteristics . 3.6 Application to Au/Ni/n-GaN I-V -T data . . . . . . 3.6.1 Fabrication procedure . . . . . . . . . . . . 3.6.2 Device characterization . . . . . . . . . . . . 3.7 Summary of results . . . . . . . . . . . . . . . . . . Chapter 4 Extracting the Schottky barrier height tacts to semiconductor nanowires 4.1 Introduction . . . . . . . . . . . . . . . . . . . . 4.2 Simulated device structure and parameters . . . 4.3 Gate bias eects . . . . . . . . . . . . . . . . . . 4.4 n-B analysis . . . . . . . . . . . . . . . . . . . 4.4.1 Eect of NW doping density . . . . . . . 4.4.2 Eect of temperature . . . . . . . . . . . 4.4.3 Eect of interface traps . . . . . . . . . . 4.4.4 Eect of gate overlap . . . . . . . . . . . 4.4.5 Image force lowering eect . . . . . . . . 4.5 Application to experimental data . . . . . . . . 4.5.1 Fabrication procedure . . . . . . . . . . 4.5.2 Electrical characterization . . . . . . . . 4.6 Conclusions . . . . . . . . . . . . . . . . . . . .

on Richard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 61 63 65 66 68 69 74 74 79 80 84 88 93 93 93 97

from axial con. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 100 103 105 109 112 113 114 118 118 122 122 124 124

vi

Chapter 5 Low frequency three terminal charge pumping to silicon nanowire eld-eect-transistors 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Experimental procedure . . . . . . . . . . . . . . . . . . 5.3 Results and discussions . . . . . . . . . . . . . . . . . . . 5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . .

applied . . . . . . . . . . . . . . . . . . . . . . . . 127 127 129 131 138

Chapter 6 Conclusions and Future Work 139 6.1 Contacts to WBG Semiconductors . . . . . . . . . . . . . . . . . . . 139 6.2 Contacts to Nanowires . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.3 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Appendix A Non-technical abstract Bibliography 144 146

vii

List of Figures
1.1 1.2 1.3 1.4 1.5 1.6 Band bending and surface dipole under surface depletion and accumulation conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . Band diagram of the Schottky metal/semiconductor contact under equilibrium conditions . . . . . . . . . . . . . . . . . . . . . . . . . Pinch-o eect of the high barrier region on the embedded low barrier region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical current-voltage response of an ideal and inhomogeneous diode Energy topography in C1 and space for inhomogeneous diodes . . Barrier prole for the case of a nanoscale contact to a bulk semiconductor. Figure also shows the isopotential contours indicating the depletion region edge prole. . . . . . . . . . . . . . . . . . . . . Barrier prole for a nanocontact to a nanowire with positive charge placed along the nanowire length. Isopotential contours depicting the depletion region edge have also been shown. . . . . . . . . . . . Summary of Schottky diode fabrication process ow . . . . . . . . . Schematic of a general I-V -T /C-V -T measurement . . . . . . . . . Block diagram schematic of a typical DLTS experiment . . . . . . . Input voltage pulse train and corresponding capacitance transient output from the DUT . . . . . . . . . . . . . . . . . . . . . . . . . . Typical J-V characteristics of the Re and Ti/4H-SiC Schottky diodes. J The y-axis in this case is ln A T 2 and is denoted as ln(J ). The inset shows the parameter as a function of normalized current for titanium and rhenium diodes (as described in Section 2.4). . . . Current as a function of potential drop across SiC bulk showing typical space charge limited current behavior. . . . . . . . . . . . . DLTS signal from the Re/4H-SiC Schottky diode. Inset shows the Arrhenius plot for the Z1 trap. . . . . . . . . . . . . . . . . . . . . . Forward bias capacitance-voltage curve of Re and Ti/4H-SiC Schottky diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 20 21 24

38

1.7

39 45 47 49 50

2.1 2.2 2.3 2.4 2.5

52 55 56 58

2.6 2.7 2.8 3.1

I-V -T characteristics simulated using Tungs equations. A homogeneous barrier height of 1.2 eV, C1 of 107 cm2 and of 104 cm2/3 eV1/3 have been used in this case. . . . . . . . . . . . . . . . . . . . . . . 73 viii

3.2

3.3

3.4 3.5

3.6

3.7

3.8

3.9

3.10 3.11 3.12 3.13 3.14

n-Be plot for devices simulated with dierent values and a patch density of C1 = 107 cm2 . A homogeneous barrier height of 1.2 eV was used in the simulation. . . . . . . . . . . . . . . . . . . . . . . Temperature dependence of the extracted ideality factor for two different values. A patch density of 1 107 cm2 and a homogeneous barrier height of 1.2 eV is assumed. . . . . . . . . . . . . . . . . . Extracted ideality factor, T0 approximation and HBD approximation for a simulated device . . . . . . . . . . . . . . . . . . . . . . Eect of on the Richardson and modied Richardson plot. Larger values correspond to greater deviation from ideality and therefore larger ideality factor values. . . . . . . . . . . . . . . . . . . . . . Eect of on the extracted Richardson constant using the original Richardson plot (M1 ), modied Richardson plot (M2 ) and eective area method (M3 ). A Richardson constant of 26 A cm2 K2 , homogeneous barrier height of 1.2 eV and a patch density of 1107 cm2 were used in the simulations. In the case of extraordinarily high Richardson constant values, it has been found that the Richardson plot is longer linear and the method applicability is, therefore, questionable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eect of C1 on the Richardson constant extracted Richardson constant using the original Richardson plot (M1 ), modied Richardson plot (M2 ) and eective area method (M3 ). A Richardson constant of 26 A cm2 K2 , homogeneous barrier height of 1.2 eV and = 1 104 cm2/3 eV1/3 were used in the simulations. In the case of extraordinarily high Richardson constant values, it has been found that the Richardson plot is longer linear and the method applicability is, therefore, questionable. . . . . . . . . . . . . . . . Linear correlation between ln(A ) and Be extracted from the e original Richardson plot for several simulated devices. An input barrier height of 1.2 eV and Richardson constant of 26 A cm2 K2 have been assumed in this case. . . . . . . . . . . . . . . . . . . . Typical Richardson plot extracted from I-V -T data (shown in the inset) of a Schottky contact to n-ZnO. From the I-V data at dierent temperatures, n and Isat can be extracted using Eq. 3.1. . . . Linear correlation between ln(A ) and Be obtained from the e Richardson plots for several devices. . . . . . . . . . . . . . . . . . Be -n plot used to determine the homogeneous barrier height of the IrOx /n-ZnO Schottky diode. . . . . . . . . . . . . . . . . . . . Typical I-V -T characteristics measured for Au/Ni/n-GaN Schottky diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Richardson plot obtained for the Au/Ni/n-GaN Schottky diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear correlations between n-Be values and Be -ln(A ) values e ix

75

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4.2 4.3 4.4 4.5

4.6

4.7 4.8

4.9 4.10 4.11 4.12

4.13 4.14

4.15

4.16

(a) Schematic of a surround-gate nickel silicide/n-Si NW Schottky diode structure. The specic metals shown were used in the nanofabricated device described later in the paper, while the simulations are more general for metallic and Si segments. (b) Crosssectional schematic showing gate and silicide overlap. . . . . . . . Typical I-V characteristics simulated using SDEVICE for the structure shown in Figure 4.1. . . . . . . . . . . . . . . . . . . . . . . . Depletion region edge prole under (a) surface depletion and (b) surface accumulation conditions. . . . . . . . . . . . . . . . . . . . Typical n-Be plot constructed using values extracted from I-V characteristics at dierent gate biases. . . . . . . . . . . . . . . . Linear correlation between n and Be for two dierent input barrier height cases. Gate bias values ranging between 0.21 V were used in both cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eect of nanowire doping density on the n-Be plot. An input Schottky barrier height of 580 meV, oxide/nanowire interface trap density of 1 1012 cm2 eV1 and T = 300 K have been assumed. Extracted ideality factor as a function of Vgs for dierent nanowire doping densities. . . . . . . . . . . . . . . . . . . . . . . . . . . . Eect of temperature on the n-Be plot for the case of a nanowire doped to 1016 cm3 with an interface trap density of 1012 cm2 eV1 . In this case, an input Schottky height of 580 meV has been used. n-Vgs variation for dierent temperatures. . . . . . . . . . . . . . Trapped interface charge (for dierent interface trap densities) as a function of the applied gate bias. . . . . . . . . . . . . . . . . . . Eect of interface trap density on the n-Vgs plot. . . . . . . . . . . n-Be plot for dierent interface trap densities: (a) no interface traps with 0 < Vgs < 0.5 was used for the linear correlation, (b) 51011 cm2 eV1 traps with 0.2 < Vgs < 0.7 was used for the linear correlation, and (c) 11012 cm2 eV1 traps with 0.4 < Vgs < 1 was used for the linear correlation. An input Schottky barrier height of 580 meV, nanowire doping density of 1016 cm3 , and T = 300 K have been assumed. . . . . . . . . . . . . . . . . . . . . . . . . . . Eect of gate overlap over the n-Vgs plot. . . . . . . . . . . . . . . Eect of gate overlap over the n-Be variation. An input Schottky barrier height of 580 meV, nanowire doping density of 1016 cm3 , and interface trap density of 1012 cm2 eV1 have been assumed. Eect of image force lowering on the n-Be plot for the two dierent doping densities. An interface trap density of 1012 cm2 eV1 , input Schottky barrier height of 580 meV, and T = 300 K have been assumed. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear correlation between n and Be obtained from experimental I-V characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . x

. 102 . 103 . 106 . 107

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5.1 5.2 5.3 5.4

a) Cross sectional schematic of the active device segment b) Schematic of the 3T-CP setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer characteristics measured by sweeping Vgs from -3 to +3V while holding Vds at 100 mV. . . . . . . . . . . . . . . . . . . . . . . 3T-CP signal in a SG-NWFET measured at dierent pulse frequencies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . max ICP as a function of applied frequency and Qmax variation with CP ln(f ) measured in our SG-NWFET. . . . . . . . . . . . . . . . . . .

130 132 134 135

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List of Tables
1.1 3.1 3.2 Summary of basic properties and comparison between 4H-SiC, GaN and ZnO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Extracted eective Richardson constant and barrier height values for dierent devices obtained using the original Richardson plot . . Extracted Richardson constant values for dierent GaN Schottky diodes obtained using the original Richardson plot . . . . . . . . . . 28 90 96

xii

Acknowledgments
I have spent several days delaying to write this segment of the thesis and it is entirely due to the fact that it is hard to convey the immense sense of gratitude i feel towards everyone involved directly or indirectly in shaping my graduate life at Penn state. Any combination of words i come up with feel inadequate, and keeping this in mind, i feel a simple thank you is the best i can do. I thank my advisors for their guidance and support all through these years. Without their inputs, ideas and eort, i would not have been able to complete this work. I would like to thank Dr.Samia for serving on my committee and also oering help and encouragement on numerous occasions. My other committee members, Dr.Tittmann and Dr.Suman Datta, have been immensely gracious with their time and inputs that have been really useful to me. My thanks to several other faculty members across Penn state who have been very kind in clearing road blocks so that i could carry on my research smoothly. Dr.Vijaykrishnan, Dr. Jian Xu, Dr. Ashok, Dr. Tom Jackson, Dr. Theresa Mayer, Dr. Mark Horn have provided access to their lab equipment, resources and time that have helped me immensely. Interaction with their graduate students have often resulted in very fruitful discussions and for that i am grateful. Special thanks to Dr.Steve Durbin and Dr.Martin Allen for their fantastic collaborative eort that has formed the basis for a large part of this thesis. The department of Engineering Science and Mechanics has provided support for my graduate studies all through these years and i am really thankful for the help and support. The ESM faculty and sta have been kind to answer my questions and guide me through dierent stages of my graduate life. For that, i am really thankful. Over the few years, i have been at Penn State, i have had the opportunity to collaborate with several people. It will be hard to name each and every one of them but i will try: Lucas, Subbu, Shiva, Suresh, PP, HP, Charan, Martin, Fan, Alan, Brian, Bob, Chad, Nick, Heayoung. I am condent that i have forgotten several others but i still acknowledge their help on countless occasions. My friends at PCG and elsewhere have often readily oered help through their words (sometimes loaded with sarcasm) and actions (sometimes proven counter-productive). Finally, xiii

my family... Several years ago, i received a call some time in the night that i got into Penn state and I still remember the excitement i felt. Late in to the night, my parents and I discussed about the prospect of getting a PhD. My mother had named me Karthik based o a character in one of her favorite novels. Although i think she intended me to be a dierent kind of doctor, it will not be too bad if i do end up as the other doctor. I am really grateful to have a very dear, caring family and an incredible wife. They have oered their criticism in their own unique ways and made the whole job about ten times easier (approximately). Thank you all!

xiv

Chapter

Schottky barrier: Modeling and Physics

1.1

Semiconductor surface

The surface plays an important role and can often dictate the electronic properties of a semiconductor device. The surface is basically an extended defect where the periodic structure of the crystal is interrupted. An unpassivated surface such as a freshly cleaved wafer has an abundance of dangling bonds that represent a nonequilibrium energy state. Under such conditions, the surface can spontaneously reconstruct to form a lower energy surface structure. Surface re-construction is driven by the need to maintain charge neutrality and is dictated by chemical bonding [1]. For example, silicon is tetravalent and covalently bonds using sp3 orbitals. At the surface of a single crystal silicon cleaved along the <111> direction the tetragonal

2 bonding of the surface atoms are severed resulting in an sp2 hybridization and a lone pair. The lone pair has a higher energy as compared to a bond pair and contributes to the overall surface energy. The lone pair also interacts with the sp3 orbitals and distorts the tetrahedral structure. In response, the surface tends to re-construct to minimize the free energy of the surface, and also return to overall charge neutrality. Kinetic constraints imposed by growth conditions, foreign contaminants and defects can all aect the nal atomic structure of the surface. The surface of a semiconductor inherently contains some surface states that are characteristic of the semiconductor surface. Depending on the detailed electronic and atomic structure at the surface, discrete energy states can be distributed within the bandgap of the semiconductor. Surface states can be of either acceptor or donor types with the density of donor type being larger closer to the conduction band minima (CBM). On the other hand, the acceptor states tend to have larger density close to the valence band maxima (VBM), and at a certain energy location within the band gap the acceptor state density matches the donor state density. The cross-over point is known as the charge neutrality level (CNL) and has special signicance in the physics of heterojunctions and interfaces. The relative dierence between CNL and the equilibrium Fermi-energy level determines the intrinsic band bending, charge state and magnitude present at the semiconductor surface. When the Fermi-level is below the CNL, positive charge is stored in the surface states, and for an n-type semiconductor a slightly downward

Figure 1.1. Band bending and surface dipole under surface depletion and accumulation conditions

band bending and surface charge accumulation results. On the contrary, when the CNL is above the Fermi-level, a net negative charge appears in the surface states, and consequently, the bands bend upwards resulting in a surface depleted condition [2]. Figure 1.1 shows the two dierent scenarios discussed above. The charge stored in the surface states (Qss ) along with the charge induced in the semiconductor (Qsc ) forms a surface dipole layer. A at band condition arises when the CNL coincides with the Fermi-level position, but in most semiconductors, the CNL diers from the Fermi level by a few tenths of an eV giving rise to either surface depleted or accumulated conditions. The magnitude and direction of the surface dipole is dependent on the semiconductor band structure, semiconductor growth and surface preparation conditions. Apart from the dependence of the surface properties on the intricate atomic and electronic structure of the native surface, the surface properties can be also inuenced by the introduction of a metal layer on the semiconductor.

Figure 1.2. Band diagram of the Schottky metal/semiconductor contact under equilibrium conditions

1.2

Metal/semiconductor (MS) interface

A simple view of the MS interaction is shown as a band diagram in Figure 1.2. A Schottky contact results due to the workfunction dierence between the metal and semiconductor. The Schottky-Mott model predicts that the dierence between the metal workfunction (m ) and the semiconductor electron anity () would equal the resultant barrier height (B ):

B = m

(1.1)

The Schottky-Mott model predicts that for a given semiconductor the Schottky barrier height (SBH) changes along with the metal workfunction. However, experimentally measured SBH on several semiconductor systems often do not seem to follow eq. 1.1, as predicted by the Schottky-Mott theory. The simple view as-

5 sumed by the Schottky-Mott model is often violated at a real MS interface. The Schottky-Mott model is considered to describe the non-interacting limit of the SB formation models since it considers the SBH as a result of the bulk metal and semiconductor workfunction dierences. The Schottky-Mott model does not place any emphasis on the MS interface properties, and hence, does not account for the eect of the metal/semiconductor interaction on the resultant Schottky barrier. Over the past few decades, several studies have focused on extending the Schottky-Mott model to account for the wide range of deviations observed. Earlier approaches relied on the presence of a thin interfacial layer with high defect density to screen the eect of metal workfunction. Experimental evidence of SBH insensitivity to metal workfunction even in intimate MS contacts led to alternate approaches such as the metal-induced-gap-states. Subsequent approaches have almost always relied on the presence of the interface or surface states that can pin the Fermi level. The key dierence between the various models is the dominant source for these interface states or pinning traps. These models can be collectively classied as gap states based models and are briey examined next.

1.2.1

Gap state models

Apart from the intrinsic surface state distribution, gap states related to metal atoms, foreign contaminants or defects can also be present. A thin interfacial layer with inherently high defect density is often assumed to be present at the MS

6 interface. Surface states present at the interface have been suggested as a source for Fermi-level pinning. However, Fermi-level pinning has also been suggested at intimate MS interfaces, and to account for FL pinning, Heine proposed that the surface states are induced due to the interaction of metal with the semiconductor surface [3]. The metal-induced-gap-states (MIGS) model proposes that the electron wave function within the metal tails into the semiconductor giving rise to overlap of the metal and semiconductor conduction bands. As a result, electronic states can exist within the energy band gap, and for intimate MS interfaces these gap states can still pin the Fermi-level. The primary eect of the surface states is to pin the surface Fermi-level, limiting the workfunction dependence of the obtained SBH. On the other hand, gap states can be induced through the metal deposition process resulting in defect creation. The unied defect-induced-gap-state (DIGS) model relies on pinning due to defects generated by the metal deposition process [4, 5]. Based on the MIGS approach, the barrier height can be related to the CNL and the pinning parameter (S = B /m [6]) through

B = CN L + S(m s ).

(1.2)

In eq. 1.2, CNL is the CNL potential from the Fermi-level, m and s are the electronegativities of the metal and the semiconductor, respectively. In the case of strongly pinned interfaces, the SBH is independent of the metal workfunction and

7 is said to approach the Bardeen limit (S = 0). Strong surface Fermi-level pinning has been shown to occur for surface state densities exceeding 1013 cm2 eV1 [7]. For a weakly pinned surface, the SBH dependence on the metal workfunction approaches the Schottky-Mott limit, and in this case the value of S approaches 1. The MIGS approach accounts for the semiconductor contribution through CNL (CNL ) and the metal/semiconductor bulk contributions through the electronegativity dierence. The SBH is determined primarily by the CNL (solely determined by the semiconductor) and the eect of secondary factors such as surface dipoles due to the electronegativity dierence. Surface states or foreign contaminants can further contribute to the deviation. Another approach that has been recently developed by Tung is based on the chemical interaction between the metal and semiconductor right at the interface [8]. Bond polarization (BP) theory, as proposed by Tung, accounts for the interaction between the metal and the underlying semiconductor through charge re-distribution that occurs at a metal/semiconductor interface. For a stable MS contact, chemical bonding occurs to some degree and this involves breaking of surface bonds and formation of new bonds. Brillson reported the dependence of the pinning parameter on the heat of formation and emphasized that for the case of a reactive MS interface the pinning was weak [9]. In the BP scenario, the MS interface properties are aected by all three components of the MS system: metal, semiconductor and the interface-specic region (ISR). In contrast to other models,

8 which account for the observed metal workfunction dependence solely through the bulk metal and semiconductor properties, the ISR is a direct result of the chemical interaction between the metal and the semiconductor atoms at the interface, and the surface charge distribution depends on the electronegativity dierence between the atoms present at the interface. Prior to the metal deposition, the semiconductor atoms are involved in some kind of bonding with their nearest neighbors. The bond length is dierent from the bulk, and the surface structure is essentially disordered. A fraction of the surface atoms still have dangling bonds and are energetically favored to form new bonds. The presence of surface defects such as micropipes or dislocations further contributes to the complexity of the surface structure and introduces localized structural variations. In order to obtain a more intuitive understanding of the BP model, consider two planes of atoms A and B located at the surface and just below the surface, respectively. The bond polarity between the two planes depends on the electronegativity dierence and results in charge re-distribution between the involved atoms. When a plane of metal atoms (M) approaches the surface, the surface bonding picture changes to accommodate the incoming metal atoms. The interface structure is dictated by similar constraints of chemical bonding, free energy minimization and charge neutrality that govern the surface re-construction process. Depending on the electronegativity dierence between M, A and B, one can envision a partial bonding to emerge between M, A and B planes. This process involves charge

9 transfer across the interface, and the nal charge distribution is dictated by the interface structure and conversely the interface structure is rened by the charge transfer. The nal ISR structure determines the bond length between the metal and semiconductor surface atoms, and this bond length can vary spatially across the interface (especially for polycrystalline metal lms). The charge transfer across the MS interface results in an interface dipole that can vary spatially as well. The magnitude of charge transfer depends on the bulk metal and semiconductor properties (such as electronegativity dierence and semiconductor ionicity) and the equilibrium bond length is specic to the interface (depends critically on growth and processing conditions). Hence, the resultant interface dipole depends on the bulk metal and semiconductor properties and also is characteristic of the specic interface structure. The preceding discussion points to the fact that the barrier height depends on details of the interface structure. Specically, a surface dipole layer induced by intrinsic surface states, defects, MIGS or possibly other sources aects the interface barrier height. In the case of polycrystalline metal contacts to a semiconductor, the surface dipole can vary spatially and can result in lateral variations of barrier height. The interface barrier height variation has a profound impact on the carrier injection and transport properties of a Schottky diode. Early evidence of the inhomogeneous nature of the Schottky contact was observed as low barrier regions within a high barrier height background [10]. The inhomogeneous nature

10 of the contact was attributed to non-uniform interfacial reaction of the metal with the semiconductor. Careful analysis of transport properties can be a valuable aid to develop, validate and understand the Schottky barrier formation mechanism. Advanced surface characterization tools such as the ballistic electron emission microscopy (BEEM), as well as scanning electron microscopy coupled with the electrical characterization methods, provide essential and comprehensive experimental data required to validate any proposed models. In the next section, we review the basics of carrier transport across Schottky contacts with a special emphasis on the inhomogeneous barrier framework.

1.3

Carrier injection and transport across the M/S interface

Transport across the metal/semiconductor system is dictated by carrier injection, trapping and carrier transport processes. The relative rates of these processes are generally bias and temperature dependent, and the conduction properties of the system are a result of an interplay between these processes. For example, in a Schottky contact to a moderately-doped semiconductor, at low bias values the conduction properties are limited by carrier injection over the barrier. However, in the case of low mobility and large trapping density materials such as organic semiconductors, the injected carriers need not be transported eectively. In such

11 cases, carrier transport and trapping/de-trapping mechanisms would determine the conduction behavior of the system. Carrier trapping/de-trapping and injection phenomena are usually temperature activated processes, and hence, their eect on conduction properties are heavily aected by the measurement temperature. In the case of a Schottky contact to an ordered single crystal semiconductor, carrier injection rather than transport determines the conduction properties of the diode. Transport across a spatially homogeneous Schottky barrier, in the ideal case, is given by the thermionic emission theory. Carrier transport occurs by emission over the barrier, and the key assumption is that the Fermi-level remains constant across the depletion region. Under thermionic emission the emitted carries are termed hot carriers, since these carriers have higher energy compared to the carriers in thermal equilibrium within the metal. The emitted hot carriers loose their additional energy through collisions with the metal lattice and with other carriers.

1.3.1

Thermionic emission

Under thermionic emission theory, as proposed by Bethe, the current-voltagetemperature characteristics of the Schottky diode are given by

I = AA T 2 exp(B ) exp(

V ) {1 exp (V )} , n

(1.3)

12 where A is the geometric area of the Schottky contact, A is the Richardson constant, and n is a phenomenological term known as the ideality factor. V is the voltage drop across the diode and is related to the applied bias Va by V = Va IRs , where Rs is the parasitic resistance. Figure 1.4 shows the typical forward bias I-V characteristics measured at room temperature. For an ideal diode, at low forward bias values, the I-V characteristics are linear on a semi-log scale. At higher current levels, the I-V characteristics are dominated by series resistance, and a sub-linear behavior is seen on the semi-log scale. In the reverse-bias regime, the current-voltage relation is expected to approach the saturation current (Isat ) given by

Isat = AA T 2 exp (B )

(1.4)

Experimental current-voltage-temperature (I-V -T ) characteristics are often tted to the ideal thermionic emission equation, and this exercise provides a baseline from which deviations are measured and interpreted. Traditionally, the extent of deviation from ideality is inferred through the extracted values of the ideality factor (n) and the barrier height (B ). Under ideal conditions, the value of n equals 1 and the barrier height should equal the Schottky-Mott limit, m . If one considers the eects of image force lowering, then the ideal values of n and B would be slightly dierent. The eect of image force lowering is a slight increase in the ideality factor and a corresponding lowering of the barrier height.

13 The image force controlled ideality factor can be estimated using

1 4

q 3 Nd 1 nif 1 + 3 4 8 2 3 Vbb s

(1.5)

and the corresponding barrier lowering is given by

1 4

q 3 Nd Vbb 8 2 3 s

(1.6)

In equations 1.5 and 1.6, Nd is the semiconductor doping, Vbb is the band bending and
s

is the dielectric constant of the semiconductor. The value of nif depends on

the doping density and, typically, ranges between 1.01 for moderate doping levels to about 1.03 for a heavily doped semiconductor. Extracted ideality factor values, however, tend to be much larger than the image force limit, and this suggests other dominant mechanisms such as tunneling across the barrier. Minority carrier injection can also contribute to the total current. Depending on the barrier prole, these mechanisms can also dominate the total current. The extracted ideality factor and barrier height values exhibit bias and temperature dependence, and a variety of trends have been reported in the literature [11, 12]. The temperature dependence of the ideality factor and barrier height is often used to identify the dominant transport mechanisms (for example, [13, 14, 15]). Prior to the inhomogeneous Schottky barrier model, deviant trends exhibited by ideality factor and extracted barrier height were typically attributed to interface

14 and surface traps. A thin interfacial layer was assumed to be present at the MS interface that could inuence the I-V -T characteristics. Interface traps or surface states (in the case of intimate MS interfaces) along with other mechanisms (such as eld emission and generation-recombination) have been held responsible for greater-than-unity ideality factors. Recently, the notion of an inhomogeneous barrier has been gaining wide applicability and seems to be able to explain the wide variety of trends observed in real Schottky diodes [16, 17]. Prior to the inhomogeneous barrier models, analytic approaches implicitly assumed that the emission occurs over a spatially homogeneous barrier. Apart from high ideality factors, a Schottky diode can exhibit a larger reverse leakage current than expected from thermionic emission theory. In some cases, a double diode behavior can be seen and has been reported for several semiconductor systems. Preliminary analytical approaches handled this behavior using a parallel diode approach, wherein two (or more) distinct regions with dierent barrier heights were assumed to contribute to the total current. The current-voltage relation in this case is a sum of all the individual diode contributions and can be written as

I(Va ) = A T 2
i

Ai exp (bi ) {exp

Va ni

1},

(1.7)

where Ai , ni and bi are, respectively, the area, ideality factor and barrier height of the ith diode.

15

1.3.2

Observation of barrier height inhomogeneities (BHI)

Electrical characterization of Schottky contacts provides valuable insights into the metal/semiconductor interface, near-surface and bulk semiconductor properties. For this reason, the Schottky contact is often used as a test structure to assess intrinsic material quality, and the Schottky test structure is also a valuable process monitor (for deposition processes). Quasi-static electrical characterization such as current-voltage-temperature (I-V -T ) and capacitance-voltagetemperature-frequency (C-V -T -) measurements are simple to set-up but can provide a comprehensive set of information. Coupled with physical analysis methods such as ballistic electron emission microscopy (BEEM), scanning electron microscopy (SEM) and other microscopy methods, the interface and bulk semiconductor properties can be thoroughly investigated. Apart from quasi-static electrical characterization, transient measurements such as deep level transient spectroscopy (DLTS) and random telegraph signal (RTS) noise measurements can give information about energetically shallow and deep defects. Experimental evidence for lateral variations of the barrier height were observed in the form of double diode behavior, and the variations were attributed to a nonuniform interfacial reaction [18]. Several electrical, optical and physical characterization tools have been used for observing and verifying barrier inhomogeneities in dierent metal/semiconductor systems. The eect of barrier height inhomogeneities on I-V -T characteristics has been reported by several groups (for example,

16 [19, 20, 21, 22]). The I-V -T measurements are, by far, the most sensitive electrical characterization methods. On the other hand, capacitance-voltage measurements are more aected by the mean barrier height and are relatively insensitive to barrier height uctuations. Internal photoemission (IPE) studies have also revealed the presence of barrier inhomogeneities [23]. RTS noise from the inhomogeneous Schottky diode has been associated with charge trapping and de-trapping by interface traps in defective patches. RTS noise signal has been used to probe the energy location and density of traps in the patch [24]. Depth-resolved cathodoluminescence spectroscopy (DR-CLS) studies on Ni/SiC Schottky diodes reveal spatially non-uniform interface traps giving rise to spatial variation in Fermi-level pinning [25, 26]. In GaN Schottky diodes, inhomogeneities are associated with the presence of threading dislocations [27]. In the case of SiC, the inhomogeneities are associated with few extrinsic localized defects [28, 29]. Metal grain boundary and morphology induced inhomogeneities have been reported in [30, 31]. Dierent sources have been cited for various metal/semiconductor systems, and the source and nature of inhomogeneity is not always apparent from any individual measurement. Comprehensive physical characterization using ballistic electron emission microscopy (BEEM), scanning tunneling microscopy, scanning capacitance microscopy, and atomic force microscopy to map the location variation of barrier height has been reported [28, 32, 33, 34, 35, 36]. These studies reveal a broad distribution

17 of barrier heights and propose that the low barrier patches lie at the tail end of the distribution. Low barrier patches around localized defects in GaN have also been detected using these characterization methods. These measurements are usually coupled with the observed current-voltage characteristics to obtain a complete physical and electrical picture of the diodes. For I-V analysis, over the past three decades, dierent theories have been developed and these are examined in the following sections.

1.4
1.4.1

Framework for barrier height inhomogeneities

Zero-order model

Earlier analytical approaches analyze the observed double diode behavior as a noninteracting parallel diode model. In the non-interacting parallel diode model, the metal/semiconductor interface is assumed to be comprised of distinct low barrier and high barrier regions. The net current in the non-interacting model is given by the sum of all contributions from the individual diodes. The non-interacting parallel diode model is a good approximation when the spatial variation of the barrier height is larger than the depletion region. The model tends to err signicantly when the lateral variations in contact barrier are at a length scale comparable to the depletion region width. In general, the interaction between high and low barrier regions needs to be considered and an outline of the method developed by

18 Tung is examined next.

1.4.2

First-order interacting model

As stated earlier, the conduction properties of a real MS interface tend to deviate from ideality on a regular basis. The observed non-ideal behavior can be broadly categorized into double diode behavior and a slight curvature in the semi-log I-V plot. Based on the discussion on the underlying mechanism of SBH formation in polycrystalline metal contacts, it can be conjectured that the SBH can vary according to the spatial variation of the interface dipole. The interface dipole magnitude depends on the metal, semiconductor and the ISR properties, and based on the BP approach, the magnitude would depend on the surface charge and the equilibrium bond length between the metal and surface semiconductor atoms. The dipole magnitude would further depend on the presence of extrinsic defects and other contaminants. It is evident that the spatial variation of the interface dipole (and hence, the SBH) can be quite complicated depending on the atomic and electronic structure of the interface. However, for the sake of simplicity, two special cases that are of great interest will be considered here. The rst case is the presence of highly localized SBH patches within an otherwise homogeneous barrier. Localized Fermi-level pinning due to defects of extrinsic origin can give rise to such a scenario. Depending on the size and nature of these patches, double diode behavior can be observed in the I-V characteristics. On

19 the other hand, a more subtle variation of the SBH can be envisioned that, on average, can be modeled as a Gaussian distribution of barrier height. In this case, the I-V characteristics would be smeared out resulting in ideality factors being greater than 1. Even for these simplied cases, the interface dipole is spatially extended and the interaction between high and low barrier regions is not analytically tractable and numerical solutions need to be sought. However, in the case of a rapidly uctuating SBH, the interface dipole can be approximated as a point dipole to facilitate nding a closed-form expression for the I-V characteristics of an inhomogeneous SBD. Utilizing the point dipole approximation, Tung derived analytic expressions for the eects of barrier height inhomogeneity on the current-voltage-temperature characteristics. Conduction through low barrier regions (also termed as patches) can be dictated by the high barrier regions depending on the size of the low barrier patches and also the dierence between the low and high barrier height regions ( = BH BL ). The surrounding high barrier region can give rise to a saddle point potential within the low barrier region, and this saddle point potential governs carrier emission for the low barrier regions. The saddle point potential is also bias and temperature dependent and results in a wide variety of possible I-V characteristics. Figure 1.3 shows a technology computer aided design (TCAD) simulation of the inuence of a surrounding high barrier region on the potential prole within the low barrier region. The high barrier region can modulate the

20

Figure 1.3. Pinch-o eect of the high barrier region on the embedded low barrier region

eective low barrier diode area and the eective barrier height seen by the carriers emitted within the low barrier region. Diodes exhibiting double diode behavior are characterized by anomalous high current at low forward bias values and are modeled as low barrier patches mixed within a uniform high barrier region (BH ). The low barrier regions are characterized by the local barrier height (BL ) and the size of the patch (R0 ). The double-diode behavior is modeled using a dilute density of low barrier patches (C1 ) that have very similar and R0 values. Tung proposed a reduced patch parame-

21

Figure 1.4. Typical current-voltage response of an ideal and inhomogeneous diode

ter, (= 3

2 R0 4

1 3

), to couple the eects of and R0 on the I-V characteristics

using a single parameter [17]. Tungs parameters capture the inhomogeneity phenomenon, and unlike the conventional Schottky diode parameters, these parameters are bias and temperature independent (termed as true system parameters). is used to qualify (and quantify) the eect of inhomogeneity on the I-V characteristics. For example, if two patches of dierent interfacial barrier height dierence (dierent ) and dierent patch sizes have the same , these patches are identical in terms of their eect on I-V characteristics (for patch sizes less than the depletion region width). The double-diode characteristics can be determined by patch density (C1 ), and the homogeneous high barrier height (BH ). The contribution from the low barrier patches characterized by a single value towards the total current can be

22 expressed as

IL =

4C1 91

exp (1 ) IL0 ,

(1.8)

where

IL0 = A T 2 exp(B ) (exp((Va IL Rsp )) 1) .

(1.9)

In eq. 1.8, 1 = (Vbb /)1/3 , with =

s /qNd

is dened as the doping parameter.

captures the BHI sensitivity of the substrate depending on the doping density. In the case of higher doping density (small ), the low barrier regions are harder to pinch o and can dominate the total current. The total current is a sum of the low barrier current contribution (IL ) and the homogeneous high barrier contribution (obtained using eq. 1.3). Apart from the double diode behavior, barrier inhomogeneities can have other less pronounced eects. In diode systems that exhibit large ideality factors (n > 1), the I-V characteristics typically exhibit a curvature on a semi-log scale. This curvature gives rise to a bias dependence of the ideality factor and barrier height. In other words, the extracted ideality factor and barrier heights depend on the bias range selected for curve-tting. In the inhomogeneous barrier model framework, such deviations are explained in terms of small uctuations around the homogeneous barrier height. The low barrier current contribution, in this case, is given

23 by

IL =

8C1 2 91

exp

2 2 1 2 2

IL0 .

(1.10)

In eq. 1.10, is the spread of the patch parameter distribution. At a real MS interface, the low barrier patch scenario could be much more complex. A more generalized formulation would provide additional exibility of using one equation to model any kind of I-V characteristics. The total current contribution from the low barrier patch distribution is given by

IL =

4C1 2 91

+ 1 2 exp 1 + 0.51 2

IL0 .

(1.11)

Physically, the generalized model can be interpreted as the presence of distinct low barrier patches with a certain size distribution. The generalized distribution is characterized by the distribution mean (0 ), spread () and peak value (Cp ) and can be reduced to either of the above models and the homogeneous case under appropriate conditions such as:
0 > 0 and = 0 would yield the double diode behavior 0 = 0 and > 0 would model diodes exhibiting high ideality factor 0 = 0 and = 0 reduces to the homogeneous Schottky barrier model

Measured I-V characteristics are typically tted with the appropriate analytic

24

log()

log(C1)

Figure 1.5. Energy topography in C1 and space for inhomogeneous diodes

expressions provided by Tung, and the tting exercise is used to estimate the patch parameters. The tting process minimizes the error between simulated and experimental I-V characteristics. The error function, typically termed the energy function, is dened as

1 E= N

ln
i=1

Iexp Ipre

(1.12)

E is a function of the Schottky diode parameters (C1 , , BH ). The energy topography as a function of C1 and is shown in Figure 1.5. The energy terrain in the case of an inhomogeneous diode is quite rough and exhibits a plethora of local minima. The presence of local minima is both a result of increased number of parameters and also their contrasting eects on the I-V

25 characteristics. The parameter search space is quite large compared to the ideal diode case. Hence, the presence of local minima and considerably large search space warrants a dierent approach to curve tting. Deterministic methods such as the multi-dimensional Newton-Raphson method require a good initial guess and also are susceptible to getting stuck at local minima. A heuristic approach such as the simulated annealing algorithm can sample large search domains uniformly and can avoid getting stuck at local minima [37]. The energy terrain shown in Figure 1.5 has the key features of local minima and an extended global minima contour. The extended global minima suggests that multiple solution points would satisfactorily t the I-V curves. The simulated annealing algorithm is quite adept at moving out of local minima but is weak in approaching global minima. The presence of an extended global minima contour further complicates the task of nding optimal solutions. In the literature, several groups t the I-V characteristics to obtain certain C1 and values. However, the energy terrain clearly indicates that multiple points would satisfy the equations. The presence of an extended global minima line indicates that a unique patch parameter set cannot be obtained from pure I-V -T tting. The preceding example shows that the eects of barrier height inhomogeneities on the extracted Schottky diode parameters needs to be considered carefully. Dierent transport mechanisms have dierent signature I-V -T characteristics,

26 and it is often hard to de-couple the eects of individual mechanisms completely. Analysis of the I-V -T characteristics aims to lter these interlaced eects, in an eort to nd the true Schottky barrier height. These analytical approaches further aid in the understanding of the basic SBH formation mechanism. Engineering contacts to semiconductors with the desired properties can then rely on solid principles based on an understanding of the formation mechanism. The work presented here can be considered a two-part thesis: the rst part concerns with Schottky diode parameter extraction in wide bandgap (WBG) semiconductors. The growth and processing of WBG semiconductors are still far from mature, and, hence, Schottky contacts to these semiconductors are more likely to be aected by BHI. Experimental determination of the Richardson constant for WBG semiconductors has been largely inconsistent and often deviate from the theoretically expected values. Hence, these contacts can provide the required experimental data for a BHI aware I-V -T analysis. The second part of the thesis focuses on the analysis of I-V characteristics of Schottky contacts at nano dimensions. Schottky contacts to nano structured semiconductors (such as nanowires) provide access to the Fermi-level pinning phenomenon at the nano scale. The study of these two parts is further motivated next, in terms of fundamental importance and technological relevance.

27

1.5

Wide bandgap (WBG) semiconductors

As the power electronics industry seeks higher power and faster switches, it is widely accepted that silicon technology is fast approaching its theoretical limits [38, 39]. Research into WBG semiconductors is based on the exceptionally attractive set of properties of this class of semiconductors. Properties such as high thermal conductivity, high breakdown eld strength, low thermal generation leakage, and direct nature of the bandgap lead to excellent gure-of-merit in many electronic devices [40, 41, 42, 43]. Apart from power electronics applications, WBG semiconductors are of key importance to optoelectronic applications such as light emitting diodes (LEDs) and lasers. WBG semiconductors occur almost exclusively as compound semiconductors of binary, ternary and quaternary systems (except for diamond). Given the breadth of possible applications and issues concerning the varied aspects related to WBG semiconductors, we consider the three most important candidates: SiC (IV-IV), GaN (III-N) and ZnO (II-VI). The experimental data presented in this thesis is on Schottky contacts to these semiconductors as well. Hence, the subsequent overview is also pertinent to the on-going discussions concerning parameter extraction in BHI aected Schottky contacts.

28

Table 1.1. Summary of basic properties and comparison between 4H-SiC, GaN and ZnO

Property

4H-SiC

ZnO

GaN

Band gap(eV) 3.2 [44] 3.3 [45] 3.4 [46] Breakdown eld (MV/cm) 2.5 [47] 11 [48] 2.2 [49] Thermal conductivity (W/cm.K) 3.3 [50] 1.3 [48] 2.1 [46] Ionicity 0.65 1.9 1.23

1.5.1

Substrate growth processes

The availability of low cost, high quality single crystal wafers of WBG semiconductors has not been achieved yet. Growth processes similar to the mature liquid phase Czokralski method for silicon are not directly available for most WBG semiconductors. Silicon carbide (SiC), for example, does not melt but directly sublimes at around 2100 [51]. Bulk single crystal SiC wafers have been grown using the modied Lelys approach. Also, silicon carbide exists in several stable polytypes, hence, polytype mixing is a big problem in silicon carbide. Epitaxial growth of one polytype would contain inclusions of other polytypes [52, 53, 54], and since different polytypes of silicon carbide have widely varying electronic properties, such inclusions would lead to inconsistent behavior. Apart from polytype mixing, point and extended defects such as comet tails and micropipes can also contribute to inferior substrate quality. Even though signicant advancements have been achieved in the single crystal quality, the dislocation defect density still remains pretty high [55, 56, 57]. III-N semiconductors, on the other hand, are grown using dierent epitaxial,

29 physical and chemical deposition processes. For GaN, the epitaxial layer is usually grown on a hetero substrate with a buer layer to reduce dislocations [58]. In some cases, laterally-extending overgrown structures have been shown to have fewer dislocations [59]. A variety of substrates such as sapphire, SiC, silicon and copper have been used to grow gallium nitride (GaN) epitaxial layers [60, 61, 62]. High dislocation densities are characteristic of GaN and AlGaN lms, and these dislocations have been cited as the source for excess reverse bias leakage in Schottky diodes to these semiconductors [60, 63, 64]. ZnO is another WBG candidate that has received renewed interest for applications in optoelectronics and space electronics. Besides being a wide band gap semiconductor, ZnO has the additional advantage of the availability of high quality single crystal substrates [65, 45]. High purity ZnO has been reported to be fabricated using dierent methods such as hydrothermal [66], melt-grown [67], vapor-phase [68], epitaxial [69] and pulsed laser deposition [70] methods. However, device performance in ZnO has been shown to be greatly aected by intrinsically occurring point defects related to oxygen vacancies [71].

1.5.2

Doping, etching and annealing processes

n-type doping of WBG semiconductors is facilitated readily due to the presence of intrinsic, shallow defects, but p-type doping of WBG semiconductors has been more challenging. Although low resistivity p-type epilayers on GaN have been achieved,

30 the activation eciency is still low and requires a careful annealing process [72, 73]. High temperature annealing is typically required to activate dopants in WBG semiconductors. High temperature annealing of SiC has been shown to cause marked increase in surface roughness through a process known as step bunching (in SiC) [74]. Dopant diusion is also prohibitively slow and requires very high temperatures for reasonable diusion proles [75, 73, 76]. Dopant incorporation can be achieved using ion implantation but at the cost of introducing dislocation loops and defects [77, 73, 78]. Although in the case of III-N semiconductors, the dopants are typically introduced in situ during epitaxial growth. The high bond strength of SiC and GaN makes it dicult to nd optimal wet etching recipes, and so dry etching methods need to be relied on. Dry etching methods such as reactive ion etching (RIE) coupled with ion implantation creates crystal damage that is, in general, dicult to anneal out in these semiconductors. Amorphization of the crystal structure due to implantation damage has been found to be dicult to anneal out, as the re-crystallized structure is not of high quality. Also, in SiC, the recrystallizing domains can be of dierent polytypes giving rise to complex defect structures [79, 80]. On the other hand, ZnO has been shown to be amenable to wet etching processes, and this further contributes to low surface defect densities achievable on ZnO [81].

31

1.6

Contacts to WBG semiconductors

Interest in Schottky contacts to WBG semiconductors is rooted in the expectation that the wider bandgap would allow fabrication of Schottky contacts with large barrier heights. In contrast to Si Schottky contacts, Schottky contacts to WBG semiconductors such as SiC and GaN have shown stronger response of the measured SBH on the metal workfunction, indicating weaker Fermi-level pinning [82, 83, 84, 85, 86]. Kurtin et al. suggested the interface behavior parameter dependence on semiconductor ionicity [87]. For covalently bonded semiconductors, the pinning parameter, S, is expected to be low and hence for elemental semiconductors, the Fermi level pinning is expected to be strong. On the other hand, for ionic semiconductors, large values of S have been observed. For compound semiconductors with a large electronegativity dierence between the cation and the anion (large ionicity), the pinning is expected to be weak. For SiC, the electronegativity dierence is about 0.65 and a pinning parameter value of about 0.7 has been reported [82, 88]. Spatially and energetically localized defects have been shown to inuence the FL pinning scenario in SiC [26]. The eect of pinning through surface states is lower in SiC because the pinning surface states are not located within the band gap. This has been attributed to the relatively large ionicity of SiC (compared to Si). The eect of ionicity has been proposed by Kurtin et al., where the penetration depth of MIGS is inhibited due to the polar nature of the bonds. In this case,

32 the screening eect of MIGS is substantially reduced leading to FL unpinning. Another suggested explanation for the relatively small FL pinning eect is the surface state bunching in ionic semiconductors, which results in surface states aggregating towards the band edges rather than being distributed across the bandgap [85]. Apart from the intrinsic surface states and MIGS, defect-induced gap states can still pin the Fermi level. The growth and processing technology of SiC is still far from mature, and the abundance of several stable polytypes gives rise to a signicantly high defect density in the substrate. 3C and 8C stacking faults within the 4H-SiC matrix have been shown to form localized defects within the bandgap, and these defects can partially pin the Fermi level [89]. However, these pinning defects tend to be localized and so the Fermi level pinning is also localized. Weak Fermi-level pinning has been observed in GaN, and this has been attributed to the large ionicity of GaN [85, 86, 90, 91]. In the case of GaN, FL pinning due to interface states localized around surface pits due to the presence of threading dislocations has been suggested. For GaN, a pinning parameter of about 0.4 has been reported suggesting weak FL pinning scenario in the case of GaN [90]. In ZnO, FL pinning associated with point defects such as oxygen vacancies has been proposed [92]. Despite weaker Fermi-level pinning in most of the WBG semiconductors, it is widely recognized that Schottky contacts to WBG semiconductors are aected by barrier height inhomogeneities. Defects at the surface that are inherent to the

33 growth processes or form due to subsequent processing steps can greatly impact the Schottky barrier properties. Schottky contacts to the WBG semiconductors are aected by the presence of BHI, which can distort the observed I-V characteristics. The source of BHI can be extrinsic in nature (defects such as micropipes) or can be intrinsic to the MS interface (MIGS), but the overall eect of these mechanisms results in spatial variation of the surface dipole layer. Depending on the nature of the surface dipole layer, a wide variety of I-V -T characteristics can be observed. Localized defects such as micropipes can give rise to double diode behavior and a more gradual variation in surface dipole can give rise to n greater than 1. Traditionally, analysis of I-V -T characteristics attempts to extract the true Schottky barrier parameters such as the homogeneous barrier height and Richardson constant. The I-V -T characteristics can be tted using Tungs model to extract the patch parameters. Methods that attempt to incorporate the eects of BHI on the observed I-V characteristics utilize the extracted patch parameters as a basis for subsequent analysis. For example, the extracted patch parameters can be used to modify the original Richardson plot. The Richardson plot is constructed from the I-V -T characteristics and is used for the experimental determination of the Richardson constant.

34

1.7

Thesis organization: Part I

Part I of this thesis discusses carrier injection and transport properties of Schottky contacts to WBG semiconductors. Chapter 2 deals with the eects of minority carrier injection on the measured I-V and capacitance-voltage (C-V ) characteristics. Schottky diodes are ideally majority carrier devices; however, a small fraction of minority carriers can be injected across the interface. Minority carrier injection is of special signicance in diodes with large barrier heights such as those to WBG semiconductors. Chapter 3 focuses on understanding the eects of BHI on the extracted Schottky contact parameters through the use of a simulated diode system. The system is based on the analytic expressions provided by Tung. Based on the understanding obtained from the simulated system, a new method that provides an eective way to extract Schottky diode parameters is presented. The application of the proposed approach to the experimentally measured I-V -T characteristics of n-ZnO and nGaN Schottky diodes is also discussed. The remainder of the thesis deals with Schottky contacts at nano-dimensions. The motivation to study Schottky contacts at nano-dimensions and the technological relevance is addressed next.

35

1.8
1.8.1

Contacts at nano dimensions

Scaling of Schottky contacts

The inception of the integrated circuit (IC) (in 1958) and subsequent eorts devoted to transistor scaling has revolutionized the semiconductor industry. Complementary metal-oxide-semiconductor (CMOS) has emerged as the industry choice IC, and transistor scaling primarily concerns with the scaling of the metal-oxidesemiconductor eld-eect-transistor (MOSFET). Technological innovations required to continuously shrink the MOSFET have also been valuable for other elds such as power electronics, microelectro and mechanical systems (MEMS) and nanotechonology. With device critical dimensions (CD) down to a few tens of nanometer, it is widely believed that transistor scaling is approaching hard physical limitations. Although the focus remains intensely on the ability to shrink the transistor size, it is being widely recognized that contacts to these devices require attention as well [93, 94]. Tailoring the contact properties such as contact resistance is important to reduce parasitic series resistance-induced device performance degradation. At the nanoscale, the contact properties may be greatly dierent from the bulk case, and it is highly desirable to tailor the contact properties to meet device design constraints. An understanding of the size eects on the contact properties and an appreciation of the limitations can help engineer optimal contacts. The nanoelectronics era has also witnessed the transformation of the Schot-

36 tky structure from a simple planar and bulk contact to a more complex set of structures. Self-assembled metal nano dots and nano clusters on semiconductor substrates [95, 96], aligned nanotubes and nanowires [97, 98], axially-aligned contacts to nanotubes and nanowires [99], and conductive AFM or STM probing of semiconductor substrates are some examples where Schottky contacts at the nanoscale come into play. Apart from the technological importance, understanding the contact properties of nano-size semiconductors is important from a fundamental scientic perspective. Contacts to nano dimensional structures provide a means to understand the basic formation mechanism of Schottky barriers. At the nanoscale, the interaction between the metal and semiconductor can be markedly dierent from the bulk case. The dierences between the two cases can be organized into two categories. The rst category accounts for dierences based on the interface and surface eects, and the second category captures contact size and geometry related eects.

1.8.2

Interface and surface eects

In the simple SB formation model, the Schottky barrier is inuenced by the metal and semiconductor workfunctions and the magnitude and sign of the interface dipole. The interface dipole is dictated by the detailed electronic structure of the interface that forms as a result of the metal/semiconductor interaction. The interaction between metal and semiconductor results in the formation of MIGS, and

37 the presence of defects can further contribute to additional gap states. In contacts at nano-dimensions, the interaction between metal and semiconductor changes due to the reduced length scale. The reduced dimensionality of nanostructures can aect the distribution of MIGS due to a change in screening length and, in eect, alter the interface dipole magnitude [100]. A systematic and thorough investigation of the FL pinning strength at the nanoscale is still lacking; however, a few reports have suggested that the FL pinning is expected to be weaker at the nanoscale [101, 102]. Compared to the bulk contacts, the surface plays a much more signicant role in nano-dimensional contacts due to an increased surface area/volume ratio. For the sake of comparison, consider a bulk Schottky contact of 1 m 1m area to a cube of silicon and a 1 m long nanowire of 50 nm radius. In the case of the bulk contact, for about 10,000 atoms of bulk atoms, there is one surface atom. On the other hand, in the case of the nanowire, there is one surface atom for just 10 bulk atoms. The energetically active surface atoms can acquire charge through interaction with ambient molecules (such as H2 O), and this surface charge can alter the nanowire conduction properties. Due to increased surface/volume ratio, the surface charge can be comparable to the intentional doping level of the nanowire.

38
0.6 0.5 0.4 E c (eV) 0.3 0.2 0.1 0 0.1 0 Y x 10
5

M/S interface

Depletion region edge

2 4 3

0 x 10
5

Figure 1.6. Barrier prole for the case of a nanoscale contact to a bulk semiconductor. Figure also shows the isopotential contours indicating the depletion region edge prole.

1.8.3

Size and geometry eects

In the conventional bulk, planar Schottky contact, the metal and semiconductor contact size and geometry do not aect the barrier prole. The electrostatics at the metal/semiconductor interface changes as one enters the nanoscale regime. The dierence from the bulk, planar Schottky contact is reected in the Poissons equation. The Poissons equation is given by

2 2 2 + 2 + 2 = , 2x y z s

(1.13)

where is the electrostatic potential, is the space charge density and

is

the semiconductor permittivity. The Poisson equation (eq. 1.13) along with the appropriate boundary conditions dictates the potential barrier shape. In a bulk, planar Schottky contact, the electric eld components along the MS

39

0.8

0.6 E (eV)

Depletion region width

0.4

0.2 2 0 0 1 x 10
5

0 4 3 4 x 10
6

Figure 1.7. Barrier prole for a nanocontact to a nanowire with positive charge placed along the nanowire length. Isopotential contours depicting the depletion region edge have also been shown.

interface (Ex and Ey ) are negligible compared to the electric eld in the direction perpendicular to the MS interface. In this case, the 3D Poisson equation can be reduced to a 1D case, and the depletion region surface is a plane parallel to the MS interface. However, for nano Schottky contacts, the lateral eld components cannot be ignored, and in this case, the more generalized 3D Poissons equation needs to be considered. Figure 1.6 shows the barrier prole for the case of a nanocontact to a bulk semiconductor. Unlike in the bulk contact, the depletion region edge is not parallel to the MS interface and, further, is thinner along the contact edges. Figure 1.7 shows the barrier prole for the case of a nanocontact to a nanowire under the inuence of positive charge placed along the nanowire length. In this case, the depletion region edge can have both axial and radial variation. The

40 depletion region prole can further be inuenced by the presence of surface charge along the nanowire length. Radial variation of the depletion region width can be observed with the barrier width being thinner at the nanowire periphery. From a contact size and geometry perspective, these examples illustrate that the Schottky contact at the nanoscale can be widely dierent from the bulk case. The barrier shape dictates the conduction properties of the nanowire and the Schottky contact I-V characteristics cannot be explained using simple thermionic emission theory. Enhanced tunneling current contribution is possible in nano Schottky contacts due to barrier thinning. Special attention needs to be devoted to account for these eects, and wherever applicable additional transport mechanisms such as eld-emission need to be considered.

1.9

Thesis organization: Part II

The focus of the second part of this thesis is to analyze the I-V characteristics of axially-aligned Schottky nano contacts to nanowires, in an eort to extract the true Schottky barrier height from the I-V characteristics. The I-V characteristics of the metal/nanowire system deviate from the thermionic emission theory due to contact geometry and surface charge eects discussed earlier. TCAD based simulations are used to understand the geometry and surface condition eects on the conduction properties of the metal/NW contact. Based on the TCAD simulations, a new approach is proposed to extract the Schottky barrier height.

41 Extracting the true Schottky barrier height is essential to investigating the barrier formation mechanisms at the nanoscale. Chapter 4 details the simulation methodology and the results obtained from application of this methodology to dierent simulation cases, and experimental I-V characteristics are presented. As mentioned earlier, the nanowire surface can aect the conduction properties of the nanowire. Finally, chapter 5 presents the adaptation of the charge pumping method to probe the interface quality of nanowire based eld-eect-transistors. This method can be used to assess the dielectric/nanowire interface quality and can provide valuable inputs to the simulation methodology of parameters such as interface trap density. Chapter 6 concludes the thesis and outlines future directions to further extend the work developed in this study.

Chapter

Minority carrier injection in Schottky contacts to WBG semiconductors

2.1

Introduction

Schottky barrier diode is called a majority carrier device since the total current owing through the Schottky diode is mainly due to the ow of majority carriers. In general, the total current owing through a Schottky barrier diode is a sum of the majority carrier and minority carrier contributions. The minority carrier contribution is usually much smaller than the majority carrier current and does not aect the observed I-V characteristics. The presence of minority carrier injection current in Schottky diodes was rst proposed by Scharfetter [103]. Scharfetter proposed the minority carrier injection eciency () parameter as a measure of the inuence of minority carrier injection on the I-V characteristics. The minority

43 carrier injection eciency is the ratio of the minority carrier current density to the total current density and can be written as

Jp Jp /Jn , Jn + Jp

(2.1)

where Jp is the minority carrier current density and Jn is the majority carrier current density. increases with increasing forward current density suggesting that at large forward bias, minority carrier injection can be quite large. Yu and Snow showed that minority carrier injection is larger in systems with larger barrier height and low substrate doping density [104]. The eciency of a Schottky contact to inject minority carrier depends on the Schottky barrier height, semiconductor doping density, and minority carrier recombination velocity at the ohmic contact end. Minority carrier injection is also aected by the carrier recombination velocity at the ohmic contact. The recombination velocity at the ohmic contact inuences the spatial prole of the minority carriers thereby aecting the minority carrier diusion current. An ideal hi-lo junction (n+ /n) ohmic contact reects minority carriers and in this case, the recombination velocity is zero. In this case, minority carrier injection is inhibited. If the ohmic contact acts as a minority carrier sink, the recombination velocity approaches innity and in this case, minority carrier injection is promoted. In this chapter, we investigate the impact of minority carrier injection on the

44 observed I-V and C-V characteristics of Re/4H-SiC Schottky diodes. Both the I-V and C-V characteristics show deviations from the expected behavior and minority carrier injection oers a good explanation for the observed deviation. In the literature, similar deviations observed on Al/4H-SiC Schottky diodes [105] and Ag/p-Si Schottky diodes [106] and have been analyzed incorrectly using the space charge limited current formulation.

2.2
2.2.1

Experimental procedure
Diode fabrication

The process ow for the fabrication of Schottky diodes is relatively simple and requires few processing steps. Figure 2.1 shows a brief description of the various stages in the Schottky diode fabrication process. The surface of the semiconductor plays a critical role in determining the diode properties; hence, special attention is devoted to surface preparation and cleaning. A degreasing procedure is often employed to clean any organic residue on the surface. A typical degreasing procedure involves a short rinse using acetone, isopropyl alcohol (IPA) and a short de-ionized (DI) water rinse. Occasionally, a short ultrasonic pulse is used to dislodge any particulate contaminants. Contamination from metallic ions can be reduced by using special cleaning recipes such as the Standard Clean 1 (SC1) RCA cleaning procedure [107]. SC1 is widely employed in the CMOS process ow for cleaning Si

45

Figure 2.1. Summary of Schottky diode fabrication process ow

wafers [108]. Prior to metal deposition, the wafer is usually subjected to a short HF dip or a buered oxide etch to remove any native oxide. The presence of native oxide can prevent obtaining a uniform intimate contact between the metal and the semiconductor. The desired metal can, then, be deposited using any of the physical deposition processes such as sputtering, thermal or e-beam evaporation. The ohmic contact is formed rst by either blanket deposition of the desired metal stack over a large area followed by a rapid thermal annealing step. In the case of heteroepitaxially grown substrates, such as GaN, the ohmic contact is patterned on the top side of the wafer using photolithography. Schottky contacts can be either dened using a shadow mask or can be patterned using photolithogrpahy. A shadow mask consists of a thin metal hard mask with holes patterned that dene the desired contact area. The shadow mask is jux-

46 taposed alongside the wafer and constrained together during the Schottky metal deposition process. For contacts at sub-micron dimensions, however, patterning using photolithography is much more suitable. In this process, a photoresist is spun on to the wafer surface followed by a soft bake. The contact pattern is dened using lithography followed by resist development using the appropriate developer. Following lithography, resist development, and metal deposition, metal contacts can be dened using the lift-o process. In this study, a 5 m thick n-type 4H-SiC epi layer grown on a 375 m thick wafer with a resistivity of 30 mcm was used. The epi-layer doping concentration was 1016 cm3 . Following a degreasing rinse, the wafer was subjected to an SC1 clean [107] and a brief HF dip. The back side contact was formed by evaporating nickel followed by a vacuum anneal at 900 . Schottky contacts of Re, Ti and Ti (10%)/W (90 %) were sputter deposited to a thickness of 250 nm to form the Schottky contact (contact area of 102 cm2 ). Electrical characterization of these diodes are detailed in this chapter with a focus on the impact of minority carrier injection on the observed characteristics.

47

Figure 2.2. Schematic of a general I-V -T /C-V -T measurement

2.3
2.3.1

Electrical characterization
I-V and C-V

Figure 2.2 shows the general schematic of the experimental setup used for electrical characterization of Schottky diodes. For I-V measurements, a source measurement unit (SMU) supplies the appropriate voltage bias conditions to the device-undertest (DUT) through co-axial BNC cables, and the corresponding current is measured using a separate SMU and recorded into a data acquisition system (DAS). Device temperature is typically monitored and controlled using a temperature controller. Capacitance-voltage (CV) measurements are also performed using a similar set-up and instead of a current-voltage source measurement unit, an LCR meter is used. For this study, current-voltage-temperature (I-V -T ) characteristics of Re, Ti and Ti/W/4H-SiC were obtained using a Biorad DL8010 system over the temperature range 100300 K. Capacitance-voltage data were obtained using a KEITHLEY 590 source measurement setup.

48

2.3.2

Transient measurements

Deep level transient spectroscopy (DLTS) is a very powerful defect characterization tool that allows the determination of sub-surface trap concentration along with capture cross-section and energetic location with respect to the conduction or valence band. The set-up required for DLTS is much more involved than required for a simple C-V measurement. The required components for DLTS and the information ow is shown in Fig. 2.3. In a typical DLTS measurement, a train of voltage pulses is triggered by the pulse generator and is input into the capacitance meter. The capacitance meter, in turn, applies these train of pulses to the DUT and measures the DUT response. A typical input voltage pulse train and the corresponding DUT capacitance response is shown in Fig. 2.4. The DUT response is fed into the analog-to-digitial (ADC) converter after it is sent through a pre-amplier. The digitized transient response is stored in the data acquisition system and is analyzed using a fast Fourier transform. This method is known as the Fourier transform deep level transient spectroscopy (FT-DLTS) and is widely used for defect characterization. The theoretical basis for DLTS and the operation principles have been detailed in the literature [109]. A brief description of the method is outlined to facilitate discussion of the results obtained from DLTS studies of Re/4H-SiC Schottky diodes. The DUT is rst cooled to a low temperature ( 100 K) and at a xed temperature, the DUT is held at a constant reverse bias. A voltage pulse is then applied

49

Figure 2.3. Block diagram schematic of a typical DLTS experiment

that pushes the device towards forward bias (depending on the voltage pulse amplitude), and a transient is observed in the depletion region capacitance. Under the application of a voltage pulse, the depletion region capacitance increases due to trapped charge and also smaller depletion region width. The initial peak in the capacitance is proportional to the trap density. The space charge capacitance responds quickly to any change in the applied bias; the trapped charge, however, cannot respond in a similar fashion. Emission of the trapped charge depends on the trap location with respect to the Fermi level and temperature. The time constant for carrier emission from a discrete trap located at Et below the conduction band is given by

Ec Et 1 = t V Nc exp kT

(2.2)

where t is the capture cross-section, V is the mean thermal velocity of the carriers, and Nc is the eective density of states in the conduction band. Analysis of

50

Figure 2.4. Input voltage pulse train and corresponding capacitance transient output from the DUT

the observed capacitance transient can yield the emission time constant, and by gradually changing the DUT temperature, one can obtain the time constant as a function of the device temperature. An Arrhenius plot constructed from the emission time constant and inverse temperature is used to obtain the energetic location of the trap [109]. In the current study, FT-DLTS measurements were performed using the BioRad DL8010 system. The sample was cooled to 100K and was held under a reverse bias of 5 V. A voltage pulse of 3 V amplitude and 1 ms duration was applied and the capacitance transient was measured. The temperature was slowly ramped to the room temperature at a rate of about 1.5 K/s.

51

2.4

Results and Discussion

Figure 2.5 shows the typical current density-voltage (J-V ) characteristics observed for Re/4H-SiC Schottky barrier diodes (SBDs). At lower voltages, a linear region is observed on the semi-log plot indicating that thermionic emission is the dominant conduction mechanism. At these low forward bias values (0.10.3 V), the current characteristics can be analyzed using the ideal thermionic emission theory given by

J = A T 2 exp(B ) exp

{1 exp (V )} .

(2.3)

In Equation (2.3), A is the Richardsons constant, T is the temperature, and = q/kT is the inverse thermal voltage (k is the Boltzmanns constant and q is the electronic charge). V is the voltage drop across the Schottky diode, which is related to the applied voltage (Va ) by V = Va IRs . Rs is the series resistance and I is the total current. B and are the conventional Schottky diode parameters (eective Schottky barrier height and ideality factor, respectively). The linear t of the semi-log J-V plots (shown in Fig. 2.5) in the low-voltage (0.10.3 V for Re and 0.50.65 for Ti) region yields contact barrier heights of 0.98 0.01 eV for the Re/4H SiC SBDs and 1.23 0.01 eV for the Ti/4H-SiC SBDs. The diodes also show ideality factor values close to 1 of = 1.05 0.03 for Re/4H-SiC SBDs and = 1.26 0.04 for Ti/4H-SiC SBDs. SiC Schottky

52

Figure 2.5. Typical J-V characteristics of the Re and Ti/4H-SiC Schottky diodes. The J y-axis in this case is ln A T 2 and is denoted as ln(J ). The inset shows the parameter as a function of normalized current for titanium and rhenium diodes (as described in Section 2.4).

diodes are typically aected by lateral variations in barrier height and often exhibit deviations from the expected thermionic emission theory. However, near unity ideality factors in the Re/4H-SiC Schottky diodes point towards a homogeneous nature of the metal/semiconductor interface. Interestingly, Re is known to form a thermodynamically stable contact with SiC, and the absence of an initially nonuniform reaction may be favorable for achieving a low ideality factor [110]. The I-V relation, in the case of Re/4H-SiC Schottky diodes, is a power law at higher voltages (Va > 0.4 V ) and is indicative of space charge limited current. The power law relation cannot be explained on the basis of an inhomogeneous Schottky barrier model. Space charge limited current [111, 112] is typically observed in low

53 mobility materials such as organic semiconductors or amorphous semiconductors (such as a-Si) [113, 114]. The presence of carrier trapping centers can cause charge build-up in the system, thereby aecting the I-V characteristics. As mentioned earlier, SCLC has been observed previously in SiC Schottky diodes as well [105]. Extracted barrier height and ideality factors are utilized to extrapolate the ideal J-V characteristics at higher voltages using

ln

J A T 2

IRs Va B .
Jp

(2.4)

The extrapolated values (JP ) are then used to obtain the series resistance using

ln

J A T 2

Jp =

IRs .

(2.5)

The dierence between the actual and extrapolated values, referred to as in Eq. (2.5), is ideally linearly related to the total current and the slope can be used to extract the series resistance. The inset of Fig. 2.5 shows typical vs I plots for the Re/4H-SiC SBDs and similarly prepared Ti/4H-SiC SBDs. For clarity of comparison, the current values have been normalized with respect to the current at Va = 1.5 V . The Ti/4H-SiC SBDs show a linear behavior, as expected from a diode with a simple series resistance, as predicted by Eq. 2.5. However, Re/4H-SiC SBDs exhibit a signicant non-linear versus I relationship indicating deviation from a simple series resistance. This suggests that the conduction mechanism at

54 higher voltages in Re/4H-SiC SBDs departs very signicantly from that in the Ti/4H-SiC SBDs and, hence, from Eq. 2.3. We have recently analyzed in detail the J-V behavior of the type observed in Ti/4H-SiC SBDs [37] and will focus this article on the type of J-V characteristics observed in Re/4H-SiC SBDs. At higher voltage values, the J-V characteristics can be approximated well by the power law J V m with m 4.5 at room temperature. This dependence is usually attributed to an exponential distribution of traps and is given by

J =q

1l

Nc

2l + 1 l+1

l+1

l s 0 l + 1 Nt

V d2

V , d

(2.6)

where

l=

Tt . T

(2.7)

In Eq. (2.6), Nt is the total density of traps, Tt is often called the characteristic temperature and d is the sample thickness. Experimental data on Al/4H n-SiC SBDs taken from ref. [105] also shows a similar power law dependence of current on voltage. In ref. [105], the authors simply plug the value of obtained from the literature to t the data using Eq. 2.6. However, from the available data, one could easily extract the expected mobility values under the exponential trap distribution assumption. We have analyzed IV -T data on the Re/4H-SiC diodes, as well as data reported in ref. [105], under the

55

Figure 2.6. Current as a function of potential drop across SiC bulk showing typical space charge limited current behavior.

exponential trap distribution assumption. This analysis yields very low mobility values (104 cm2 V/s), which do not correlate well with the commonly expected value of mobility in SiC [115]. Also, an exponential trap distribution in 4H-SiC seems very unlikely due to the ordered nature of the material. Based on the arguments presented in this section, we abandon the assumption that the power law is due to an exponential distribution of traps and look for an alternative explanation. Alternatively, the potential drop across the semiconductor bulk can be approximated using

Vb = Va

I ln 1 + Isat

(2.8)

56

Figure 2.7. DLTS signal from the Re/4H-SiC Schottky diode. Inset shows the Arrhenius plot for the Z1 trap.

where

Isat = AA T 2 exp (B ) .

(2.9)

In an ideal diode, the bulk potential drop (Vb ) should be linearly related to the current owing through the diode. Figure 2.6 shows the observed relationship between current and Vb in Re/4H-SiC Schottky diodes. The observed relationship is also strongly indicative of space charge limited current. In the lower voltage regime, the relationship between I and Vb is linear, indicating ohmic behavior, followed by a SCLC behavior at higher voltages. In the higher voltage regime, the current varies with Vb as I = BVbn , where B is a proportionality constant (n 2). Figure 2.7 shows the FT-DLTS spectrum observed for a Re/4H-SiC diode. In Fig. 2.7, b1 is the rst sine coecient in the Fourier transform of the capacitance

57 transient. The inset shows the Arrhenius plot for a trap located at an energy depth of Et = 0.6 eV below the conduction band edge. The trap concentration is determined from the signal intensity and is estimated to be 1012 cm3 . The electron trap has a capture cross-section of = 3.8 1013 cm2 and is extracted from the intercept of the Arrhenius plot (shown in Fig. 2.7). These values are very close to those reported for an intrinsic defect in SiC known as the Z1 defect center [116]. The trap density obtained by the DLTS measurements is orders of magnitude smaller than the carrier density (1016 cm3 ). Also, excess injected charge of a magnitude comparable to the equilibrium free carrier density cannot be achieved at such voltage levels. In organic semiconductors and insulators, either or both of the above conditions are met and one can observe trap-limited I-V characteristics. In 4H-SiC, neither of these conditions are satised, and hence it is unlikely that SCLC behavior is due to majority carrier traps. Double carrier injection in solids can also give rise to SCLC-like behavior. The preceding analysis points to the conclusion that space charge limited current due to minority carrier injection is the most likely cause for the observed I-V characteristics. Forward bias C-V measurements have been used to further assess the role of minority carrier injection in the conduction properties of Re/4H-SiC SBDs. Figure 2.8 shows the observed C-V characteristics of Re/4H-SiC and Ti/4H-SiC SBDs in forward bias. The reverse bias characteristics are typically used to obtain

58

Figure 2.8. Forward bias capacitance-voltage curve of Re and Ti/4H-SiC Schottky diodes.

the doping prole of the underlying substrate. The peak in the forward bias region of the C-V characteristics is due to interface traps and series resistance as analyzed in ref. [117]. Ti/4H-SiC SBDs follow the expected C-V characteristics; however, Re/4H-SiC SBDs show excess capacitance in forward bias. Werner et al. have shown, in the case of Si Schottky diodes, that such excess capacitance signature can be attributed to minority carrier injection, and the excess capacitance is not related to interface traps [118]. Minority carrier injection under forward bias conditions would occur from the Schottky metal into the substrate. At low forward bias voltage values, the current is primarily limited by thermionic emission, and most of the applied voltage drops across the depletion region. In this case, there is negligible electron and hole Fermilevel splitting. With increasing forward bias, the Fermi-level splitting increases

59 and results in higher minority carrier injection. Eventually, most of the voltage drop is seen as the dierence between the electron and hole quasi Fermi-levels and corresponds to the bulk voltage drop. Since the majority carrier current is primarily governed by the drop across the diode (V ), and with increasing minority carrier injection there is very little variation in V , the majority carrier current contribution does not increase with increasing forward bias. As excess minority carriers are injected, the current is limited mainly by the injection and transport of holes across the semiconductor bulk. Werner et al. have suggested that under ideal conditions, an ohmic contact to a hi-lo junction acts as a good reecting boundary for minority carriers and inhibits minority carrier injection at the Schottky contact [118]. In the case of a poor ohmic contact, the injected minority carriers are not reected eectively at the hi-lo junction and can recombine at the ohmic contact. Although Re forms a good homogeneous contact, an imperfect ohmic contact in our Schottky diodes may have made possible the minority carrier injection at the Schottky contact. Minority carrier injection would be detrimental to device operation, not only in terms of the limitation due to space charge, but also because of minority carrier storage and slower reverse recovery. However, I-V characteristics show other deviations such as n > 1, high reverse leakage current and double diode behavior. These deviations are commonly observed in Schottky diodes and have been explained well by the inhomogeneous

60 Schottky barrier model. The eects of BHI on the I-V characteristics on the extracted Schottky diode parameters are examined in the next chapter. Starting with a survey of the current approaches to account for eects of BHI on the extracted conventional Schottky diode parameters, a new method that extends the applicability of existing methods is proposed.

Chapter

Eects of barrier height inhomogeneities on Richardson constant determination

3.1

Introduction

In order to use the current-voltage (I-V ) response to accurately obtain the Schottky barrier height of a metal/semiconductor (MS) junction, it is necessary to know the Richardson constant (A ), and this is one of the most compelling reasons for an accurate determination of the Richardson constant [119]. The Richardson constant is extracted from the so-called Richardson plot using measured I-V -T data. In practice, the extracted Richardson constant may be far from the theoretically expected value, and in many cases, by orders of magnitude. Several researchers

62 have investigated the cause for the discrepancy and proposed dierent explanations [119, 16, 120, 121, 122]. Earlier approaches (circa mid 80s and early 90s) focused on the temperature and interface electric eld dependence of the barrier height (as proposed by Wagner [123]). Recent approaches focus on incorporating the eects of barrier height inhomogeneities (BHI) on the measured I-V -T curves, and a modied version of the Richardson plot is often used (for example, [121, 124, 35, 125, 126, 127]). Eects of BHI on the extracted barrier height are widely recognized. Analytical approximations that capture these eects are available to interpret experimental I-V -T data. No such provision exists for the extracted A until this study. To begin with, we demonstrate the limitations of previous approaches in greater detail and also provide further experimental support for our proposed approach. First, we review previous methods that are typically used to account for the deviations of the Richardson plot from the ideal case. We specically focus on the methods that address barrier height inhomogeneities. Next, we apply these methods to a simulated dataset in order to gain insights into the applicability and limitations of these widely-used approaches. Based on the BHI framework provided by Tung, we explicitly derive the dependence of the Richardson constant on the BHI parameters. The new approach lters the eects of BHI on the extracted Richardson constant without the need for parameterized tting or modifying the original Richardson plot. The proposed approach is applied to determine the

63 Richardson constant of n-type ZnO and GaN.

3.2

Review of existing methods

In the ideal Schottky diode case, under forward bias, the carrier conduction process is limited by emission of carriers from the semiconductor over a spatially homogeneous barrier at the MS interface into the metal. In this case, the carrier conduction and hence, the current is given by

I = Isat exp

(Va IRs ) [1 exp (Va )] , n

(3.1)

where

Isat = AA T 2 exp (Be ) .

(3.2)

In Eq. 3.1 and 3.2, I is the total current, A is the Richardson constant, A is the the diode area, is the inverse thermal voltage (q/kT ), Va is the applied voltage, Rs is the series resistance, T is the absolute temperature, n is the ideality factor and Be is the apparent or eective Schottky barrier height. The Richardson constant is extracted from the current-voltage-temperature (I-V -T ) characteristics using the Richardson plot. The saturation current, Isat , is

64 obtained from the I-V data at dierent temperatures using

ln

I 1 exp (Va )

Va + ln (Isat ) . n

(3.3)

This equation is applicable at low currents under forward bias, where the eects of series resistance can be neglected. From the obtained Isat values, the Richardson plot is constructed by plotting ln (Isat /AT 2 ) vs. 1/T . The slope and intercept of the Richardson plot yield the eective barrier height and Richardson constant respectively, as indicated by

ln

Isat AT 2

qBe 1 + ln(A ). k T

(3.4)

The bias and temperature dependence of the Schottky diode parameters (n and Be ) give rise to a slight curvature in the ln(I) V plot. As a result of the curvature, the saturation current (Isat ) values used in the Richardson plot are heavily inuenced by the bias range selected for curve-tting. Numerous deviations from the ideal thermionic emission theory have been proposed and examined in real Schottky diodes. Some of the key eects that signicantly aect the measured Richardson constant are outlined next.

65

3.2.1

Temperature dependence of B

In one of the earliest treatments of non-ideality in the extraction of A , the discrepancy between the measured and theoretical A values was explained using a linear temperature dependence of the homogeneous barrier height (B0 ). The temperature dependence of the homogeneous barrier height is given by

B0 (T ) = B0 (0) + T.

(3.5)

In equation 3.5, is the temperature coecient of the barrier height. Using this method, the corrected Richardson constant value A is related to the uncorrected c value (A ) [119, 128] by uc

A = A exp (q/k) . c uc

(3.6)

The temperature coecient is obtained from capacitance-voltage-temperature (CV -T ) measurements. For silicon, the temperature coecient of the barrier height has been correlated with the temperature coecient of the bandgap, and it has been suggested that the temperature dependence is associated with the Fermilevel pinning position [122, 125, 129]. The Richardson constant is expected to be independent of the barrier metal and is a property of the semiconductor alone [119]. However, even the corrected Richardson constant values have been found to depend on the choice of metal [128]. The temperature dependence of the barrier

66 height would be less signicant for systems exhibiting weak Fermi-level pinning, since in this case the temperature coecient of B would be much smaller. Also, for diodes exhibiting ideality factors far greater than 1, other dominant factors can distort the Richardson plot.

3.2.2

Flat band barrier height analysis

Wagner et al. observed a linear correlation between the ideality factor and barrier height and attributed this dependence to interface electric eld dependence of the eective barrier height [123]. A at band barrier height (f ) concept is introduced B and is considered a real MS interfacial property since it is measured at zero electric eld. The at band barrier height can be expressed in terms of the ideality factor and apparent barrier height as given by

f = nBe (n 1)Vn . B

(3.7)

In Eq. 3.7, Vn is the bulk potential and equals (1/)ln(Nc /Nd ), where Nc is the eective density of states in the conduction band and Nd is the doping density. In the case of non-ideal Schottky diodes, a curvature is usually observed in the original Richardson plot. Unewisse et al. suggested a modied version of the Richardson

67 plot using a at band saturation current [120], as dened by

f Isat = AA T 2 exp

qf B nkT

(3.8)

In this case, the abscissa of the Richardson plot is modied to 1/nT instead of 1/T according to

ln

f Isat AT 2

qf B k

1 + ln(A ). nT

(3.9)

Apart from the linear correlation between n and B , an anomalous increase in ideality factor with decreasing temperature was observed by Padovani and Sumner [11]. This behavior is commonly known as the T0 anomaly, and the interface electric eld model does not oer an explanation for the T0 anomaly. The inhomogeneous Schottky barrier models, as explored by several authors in late 1980s and early 1990s, was able to account for many of the observed anomalies and deviations. In recent years, the inhomogeneous Schottky barrier concept has been applied to explain a wide range of observed I-V characteristics. A brief overview of the inhomogeneous Schottky barrier models is presented next, in the context of their application towards modifying the Richardson plot. For the case of barrier inhomogeneities that vary on the length scale of the depletion region width, two theories are widely employed. Werner and Gttler propose an interacting Gaussian disu tribution of barrier heights to account for the presence of spatial inhomogeneities

68 [16]. The second model proposed by Tung relies on a patchwork of low barrier regions embedded within a homogeneous high barrier region [17].

3.2.3

Werner and G ttlers model u

Using a Gaussian distribution of barrier heights characterized by a voltage and temperature dependent spread parameter ( ), the inhomogeneous barrier model is able to account for a variety of observed deviations. The model is able to address the problem of T0 anomaly observed in several MS systems. Also, the model is able to account for deviations observed in extracted ideality factors and eective barrier heights. A central feature of the model is the emergence of the ideality factor as a result of the voltage deformation of the potential prole uctuation, or in other words, the voltage dependence of the barrier distribution parameter, . Using the Gaussian distribution of barrier heights, the model is able to account for the curvature in the Richardson plot. A modied Richardson plot has been suggested based on Werner and Gttlers model and is given by u

ln

Isat T2

2 q 2 2k 2 T 2

= ln(AA )

qB0 . kT

(3.10)

A key feature of Werner and Gttlers model is the bias independence of the u ideality factor. Hence, the model applicability is limited to experimental data that conforms to this principle, although experimental data in the literature are regularly tted with the Gaussian distribution model without this constraint met.

69 Tungs model, on the other hand, accounts for barrier inhomogeneities in a slightly dierent way. Tungs model accounts for bias and temperature dependence of the Schottky diode parameters using bias and temperature independent patch parameters and is discussed next.

3.2.4

Tungs model

As stated earlier, the I-V characteristics of a real MS interface often deviate from the ideal case. The observed non-ideal behavior can be broadly categorized into double diode behavior and a slight curvature in the semi-log I-V plot. Diodes exhibiting double diode behavior are characterized by anomalous high current at low forward bias values and are modeled as low barrier patches mixed within a uniform high barrier region (BH ). The low barrier regions are characterized by the local barrier height (BL ) and the size of the patch (R0 ). Depending on the interfacial barrier height dierence between low and high barrier regions ( = BH BL ) and the patch size, the high barrier region can aect the potential within the low barrier region. Under such conditions, the low barrier region is said to be pinched o by the high barrier region. The pinch-o phenomenon gives rise to a saddle point potential within the low barrier region, and the saddle point potential governs the carrier transport across the low barrier region. The saddle point potential is both bias and temperature dependent and can account for the observed voltage dependent Schottky diode parameters for the low barrier region.

70 Tung proposed a reduced patch parameter, , to couple the eect of and R0 (as dened by Eq. 3.11) [17]. According to Tung, the double diode behavior can be modeled using a dilute density (C1 ) of patches characterized by very similar values, where
1 3

=3

2 R0 4

(3.11)

Many Schottky diodes do not exhibit double diode behavior, but they do still show a slight curvature in the semi-log I-V plot. Tung suggests a semi-Gaussian distribution of the reduced patch parameter () to account for the slight curvature in the semi-log I-V plot. The distribution is characterized by a mean value, 0 = 0, spread , and total density of patches C1 . It is well established that the curved nature of the Richardson plot can be a result of BHI. The eects of BHI on Richardson constant determination using Werners model [16, 130, 131] and Tungs model [35, 22] have been attempted in the literature. Based on Tungs model, some authors have attempted to account for the eects of BHI by using an eective area rather than the overall contact area [124]. In an inhomogeneous Schottky diode, at low temperatures, the current preferentially ows through the low barrier regions. In this regime, the total area contributing to the current conduction is a small fraction of the geometric area of the Schottky contact. I-V -T data are tted using the analytic expressions provided by Tung

71 to obtain the low barrier patch density and parameters. At a given bias and temperature, the eective area of the low barrier patches can be estimated using

f=

8C1 2 , 91

(3.12)

where

1 =

Vbb

1/3

(3.13)

In Eq. (3.13), Vbb is the band bending at the measured bias, and is the doping density dependent parameter and equals
s /qNd . s

is the dielectric constant of

the semiconductor. The Richardson plot is then modied, using this eective area term, to

ln

Isat fT2

= ln(AA )

qB0 . kT

(3.14)

However, it should be noted that the eective area of the low barrier patches is both bias and temperature dependent. A key aspect of these analytical approaches is the hypothesis that the current contribution mainly comes from the low barrier regions. This assumption need not hold true across the measurement temperature range and particularly at higher temperatures. The eective area contribution is estimated using the patch spread

72 parameter () and the patch density (C1 ) obtained through the I-V -T tting exercise. However, the BHI parameters (C1 and ) cannot be uniquely determined from the I-V -T characteristics since multiple sets of BHI parameter values can t the I-V -T data. Hence, a consistent method for calculating the eective area is not possible and is riddled with a great degree of uncertainty. Another approach that tries to incorporate BHI eects on Richardson constant relies on invoking the T0 approximation [125, 130, 35] originally proposed by Padovani and Sumner [11]. Experimental data on several Schottky diode systems exhibit the T0 anomaly over a limited temperature range, and in this range the ideality factor can be expressed as

n=1+

T0 . T

(3.15)

The T0 parameter has been attributed to presence of BHI and within the BHI framework provided by Tung, T0 can be written as

T0 =

2 31

q . k

(3.16)

The modied Richardson plot is constructed by plotting ln suggested by

Isat AT 2

vs. 1/nT as

ln

Isat AT 2

qBe + ln(f A ). nkT

(3.17)

73

Figure 3.1. I-V -T characteristics simulated using Tungs equations. A homogeneous barrier height of 1.2 eV, C1 of 107 cm2 and of 104 cm2/3 eV1/3 have been used in this case.

However, the obtained Richardson constant is still an eective value that is scaled by the fractional area covered by the low barrier regions (f ). The eective barrier height obtained from the BHI modied Richardson plot is given by

B = B0

n1 ln

Nc Nd

(3.18)

74

3.3

Extended inhomogeneity analysis

From the above discussion, it is evident that there are quite a few methods that attempt to account for the deviation of the extracted Richardson constant from the expected value. In this section, we investigate the applicability and limitations of previous methods using a controlled I-V -T dataset obtained from analytical expressions by Tung for the case of a semi-Gaussian distribution of the patch parameter . A wide range of device characteristics can be simulated by varying the homogeneous barrier height (B0 ) and BHI parameters (C1 and ). Forward bias I-V characteristics are obtained across a wide range of temperature values, and the simulated data are treated in a similar fashion as one would treat experimental I-V -T data. Figure 3.1 shows the typical simulated I-V -T characteristics obtained using analytical expressions provided by Tung. A patch density C1 of 107 cm2 , of 104 cm2/3 eV1/3 , and a B0 of 1.2 eV have been used in this case.

3.3.1

n-B and T0 analysis

Schmitsdorf et al. showed that the observed linear correlation between n and B could be explained in terms of Tungs BHI model [132]. The linear correlation between n and B is reported in several MS systems and provides a simple way to account for the eects of BHI on the extracted Schottky barrier height without the need for complicated parameterized tting of the I-V -T characteristics. However, the linear correlation observed between n and B is valid only for a

75

(cm2/3 eV1/3 )

Figure 3.2. n-Be plot for devices simulated with dierent values and a patch density of C1 = 107 cm2 . A homogeneous barrier height of 1.2 eV was used in the simulation.

narrow range of ideality factors as pointed out by Schmitsdorf et al. [132]. Figure 3.2 shows an n-B relation for a family of simulated devices, and each device is characterized by a dierent value. For low ideality factors (n < 1.2), the ideality factor and eective barrier height are linearly correlated. The linear correlation can be extrapolated to n = nif , where nif is the image force controlled ideality factor, yielding the zero-bias barrier height B0 . Adding the zero-bias barrier height and the barrier height lowering due to the image force (B ), one can obtain the homogeneous barrier height. The image force controlled ideality factor can be estimated using
1 4

1 q 3 Nd nif 1 + 3 4 8 2 3 Vbb s

(3.19)

76

Figure 3.3. Temperature dependence of the extracted ideality factor for two dierent values. A patch density of 1 107 cm2 and a homogeneous barrier height of 1.2 eV is assumed.

and the barrier lowering due to image force is given by

1 4

q 3 Nd Vbb 8 2 3 s

(3.20)

For moderately doped semiconductors, extrapolating to n = 1 yields a close estimate of the homogeneous barrier height, since in this case, nif is very close to 1. It should be noted that a linear correlation is observed at high ideality factor values as well, but the straight line in this region does not extrapolate to the input barrier height and can give erroneous extrapolated barrier height values. Figure 3.3 shows the ideality factor as a function of the inverse temperature for two dierent values of . At lower temperatures (high n), the temperature dependence of n can be approximated using the T0 approximation (as given by

77

Figure 3.4. Extracted ideality factor, T0 approximation and HBD approximation for a simulated device

Eq. 3.15), and in this regime, the total current is dominated by the contribution from low barrier (LB) regions. At higher temperatures (low n), the temperature dependence of the ideality factor deviates signicantly from the T0 approximation. Although BHI has been suggested as the source for the T0 parameter by both Tung [17] and Werner et al. [16], the abrupt change of slope in the n vs. 1/T curve has not been investigated yet. At lower ideality factor values, the currentvoltage characteristics have been found to be dominated by the homogeneous high barrier region. This regime is dened as the high barrier (HB) dominated regime. Experimental data on several Schottky diode systems exhibit the T0 anomaly; however, an important point to be noted is that the T0 anomaly eect is observed over a limited temperature range [16, 11]. Starting from the analytic expressions for I-V -T characteristics for an inhomo-

78 geneous diode, one can show that the voltage and temperature dependence of the ideality factor in the HB dominated (HBD) regime is given by

n=1+

8C1 4 exp 2 271

2 2 1 2 2

(3.21)

The barrier height in terms of ideality factor is given by

Be = B0 3(n 1)Vbb .

(3.22)

A clear linear relation between n and Be is observed, and for n = 1, Be becomes equal to B0 . The relevant derivations of these expressions are provided in the Appendix. Figure 3.4 shows the extracted ideality factor as a function of the inverse temperature (1/T ). At lower temperatures (higher ideality factor), the T0 equation gives a good t to the ideality factor curve. The T0 regime is the LB dominated regime. At higher temperatures, the ideality factor values deviate signicantly from the T0 line, and the HBD approximation (equation 3.21) yields a much better t. In the HB dominated regime, Eq. 3.21 captures the bias and temperature dependence of n, and analytical approaches that invoke the T0 approximation in this regime would yield erroneous results.

79

Figure 3.5. Eect of on the Richardson and modied Richardson plot. Larger values correspond to greater deviation from ideality and therefore larger ideality factor values.

3.3.2

Richardson plot

The eect of increasing departure from ideality (n = 1) on the Richardson plot is shown in Figure 3.5. For the case of n = 1 or low values, the 1/T and 1/nT plots coincide, and the obtained values of A and B values correlate well with the input values. For moderate high ideality factor values, the extracted A and B values from the original or modied Richardson plot can be quite dierent from the input or actual values. With increasing BHI parameter values (C1 and ), n tends to increase, resulting in a curvature or distortion of the Richardson plot. Curvature of the original Richardson plot has been reported widely and, in this case, the modied version of the Richardson plot is often employed [121, 125, 126, 127]. However, as suggested by Fig. 3.5, the modied Richardson plot is not always

80 successful in rectifying the curvature observed in the original Richardson plot.

3.3.3

Application of existing methods

From the preceding discussion, it is evident that the presence of BHI aects the Richardson plot, and therefore, the extracted Richardson constant. A systematic investigation of the eect of BHI parameter values (C1 and ) on the extracted Richardson constant is, however, still missing. In order to understand the applicability of the conventionally reported methods, we apply previous methods for analyzing I-V -T characteristics to a set of simulated devices obtained by varying the BHI parameters (C1 and ). Several methods have been proposed in the literature, but we have chosen to focus on three approaches: the original plot (M1 ), modied plot (M2 ) [120] and eective area method (M3 ) [124]. The original plot method is the simple original Richardson plot that does not account for any of the deviations, whereas in the modied version of the Richardson plot, the abscissa and ordinate are changed to 1/nT and ln
f Isat AT 2

respectively ( according to Eq. 3.9).

The eective area method is a more recent approach (proposed by Roccaforte et al. [124]) that attempts to account for the eects of BHI on the Richardson plot by calculating the eective area for conduction using Eq. 3.12. In this case, the total current is assumed to be dominated entirely by the low barrier patches and the geometric area term (A) is scaled by an eective area term (f ). Figure 3.6 shows the extracted Richardson constant as compared to the input

81

Figure 3.6. Eect of on the extracted Richardson constant using the original Richardson plot (M1 ), modied Richardson plot (M2 ) and eective area method (M3 ). A Richardson constant of 26 A cm2 K2 , homogeneous barrier height of 1.2 eV and a patch density of 1 107 cm2 were used in the simulations. In the case of extraordinarily high Richardson constant values, it has been found that the Richardson plot is longer linear and the method applicability is, therefore, questionable.

Richardson constant value as a function of using the three dierent approaches. A patch density of 1 107 cm2 , homogeneous barrier height of 1.2 eV, and donor density of 1016 cm3 was used in this case. Forward bias I-V curves in the temperature range of 300400 K were used to obtain the original and modied Richardson plots. Fig. 3.6 also shows the extracted ideality factor at room temperature. At low values (corresponding to low n), the original Richardson plot yields Richardson constant values close to the input Richardson constant. However, with increasing ideality factor values (larger n), the Richardson constant extracted using the original Richardson plot can quickly deviate from the true value. In other words, the

82
12
9

2.0

log(A* /A*) e

6 3

M3

1.8 1.6 1.4 1.2 1.0 8.0

0
-3 -6 -9

M1

-12 5.0

5.5

6.0

6.5 7.0 -2 log(C1/cm )

7.5

Figure 3.7. Eect of C1 on the Richardson constant extracted Richardson constant using the original Richardson plot (M1 ), modied Richardson plot (M2 ) and eective area method (M3 ). A Richardson constant of 26 A cm2 K2 , homogeneous barrier height of 1.2 eV and = 1 104 cm2/3 eV1/3 were used in the simulations. In the case of extraordinarily high Richardson constant values, it has been found that the Richardson plot is longer linear and the method applicability is, therefore, questionable.

extracted Richardson constant value is an eective value that depends on the extent of deviation the MS interface exhibits from ideality. The modied Richardson plot (M2 ) also suers from similar discrepancies and can yield reasonable Richardson constant values for low n, but with increasing n, the extracted Richardson constant can deviate signicantly from the input value. The Richardson constant extracted using the eective area method can vary over orders of magnitude from the input Richardson constant value. The eective area method can yield a Richardson constant value close to the input value for large ideality factor values since the method is applicable when the contribution from low barrier regions dominates the total current. However, as shown in Fig. 3.6, even an accurate knowledge of C1 and does not ensure an accurate determination of the actual Richardson constant since the eective area is both bias and temperature dependent. Figure 3.7 shows the

83 eect of patch density (C1 ) on the Richardson constant extracted using the three dierent approaches (original, modied and eective area methods). The eect of varying C1 is similar to the eect of varying , and with increasing C1 values the ideality factor increases and results in a larger departure of the extracted A value from the actual value. The preceding analysis shows that these earlier methods fail to provide an accurate method to account for the eects of BHI and tend to either underestimate or overestimate the value of the actual Richardson constant. To summarize, the T0 approximation cannot be applied for low ideality factor cases or more specically in the HB dominated regime. n-Be plots show the presence of distinct linear regimes that can be attributed to the HB (low n) and LB (high n) dominated regimes. Extrapolation of the n-B plot in the HB dominated regime gives the homogeneous high barrier height, but in the case of the LB dominated regime, the extrapolation yields an eective barrier height higher than the homogeneous barrier height. Although the T0 anomaly equations are a good approximation of the voltage and temperature dependence of the ideality factor in the LB dominated regime, the approximation is not valid in the HB dominated regime. Depending on the extent of inhomogeneity, the Richardson constant extracted using previous approaches can deviate signicantly from the actual value. Hence, there is a need for an accurate method that can lter the eects of BHI on the extracted Richardson constant.

84

3.4

Proposed approach

In the HB dominated regime, the eects of BHI on the Richardson plot are reduced. Despite the reduced impact of BHI in the HB dominated regime, the Richardson constant extracted using the original Richardson plot can vary over orders of magnitude. Realizing the limitations of previous approaches, we have proposed a new and dierent approach based on Tungs BHI model [133]. The current owing through an inhomogeneous Schottky diode characterized by the BHI parameters C1 and is given by

8C1 2 I = AA T 2 exp (B ) 1 + exp 1 exp(V ) 91

2 2 1 2 2

exp(V ), (3.23)

where 1 equals (Vbb /) 3 . In Equation (3.23), Vbb is the band bending at the measurement bias and =
s /(qNd )

is a doping density dependent parameter[17]

determines the overall patch strength, and at higher doping levels (low ), conduction through low barrier regions is enhanced. Taking the natural log of both sides of Eq. 3.23 and using the approximation ln(1 + x) x in the HB dominated regime, we can re-write Eq. (3.23) as

ln

I 1 exp(V )

= V + ln(AA T 2 ) +

8C1 2 exp 91
ln(Isat )

2 2 1 2 2

B .

(3.24)

85 Setting the ln(Isat ) term from Eq. 3.24 equal to that in Eq. 3.4, we obtain

Be + ln(A ) = B + ln(A ) + e

8C1 2 91

exp

2 2 1 2 2

(3.25)

Recognizing that the eective barrier height is the slope of the Richardson plot and can be obtained from the saturation current expression (given in Eq. 3.24),

Be =

ln

Isat AA T 2

= B

81 C1 4 9

exp

2 2 1 2 2

(3.26)

Using Equations 3.25 and 3.26, we can now express the eective Richardson constant (A ) as e

ln(A ) = ln(A ) + e

1 2 1 2

(Be B ).

(3.27)

Equation 3.27 shows that the extracted Richardson constant (A ) can be related e to the eective barrier height (Be ), homogeneous Richardson constant (A ) and homogeneous barrier height (B ). A linear relationship between ln(A ) and Be e exists, and as Be approaches B , A approaches A . e Equation 3.25 suggests that the extracted barrier height and Richardson constant are correlated, and as B approaches the homogeneous barrier height, the eective Richardson constant approaches the unaected, homogeneous value (A ). In other words, in the HB dominated regime, with diminishing BHI eect, both the

86

Figure 3.8. Linear correlation between ln(A ) and Be extracted from the original e Richardson plot for several simulated devices. An input barrier height of 1.2 eV and Richardson constant of 26 A cm2 K2 have been assumed in this case.

eective barrier height and Richardson constant values approach their true values in a correlated fashion. Figure 3.8 shows a typical log(A )-Be constructed using the extracted Richarde son constant and eective barrier height values from several simulated devices. A homogeneous barrier height of 1.2 eV and A of 26 A cm2 K2 were assumed in this case. C1 and values were chosen randomly within the range 1 5 107 cm2 and 0.9 1.1 104 cm2/3 eV1/3 , respectively, to generate the data points on the plot. As mentioned earlier, in the HB regime, the n-Be plot can be extrapolated to the homogeneous barrier height. The HB regime is indicated by the absence of bowing in the Richardson plot. Using the extracted ideality factor in the HB

87 dominated regime, and the eective barrier height from the Richardson plot, an n-Be plot can be constructed. The ln(A )-Be plot can be constructed using e the ln(A ) and Be values obtained from a set of devices. The homogeneous e Richardson constant can then be extracted by extrapolating the ln(A )-Be plot e to Be = B0 . The zero-bias barrier height can be obtained from the n-Be plot by extrapolation to n = nif . Alternatively, the n-Be plot can be constructed by using n values from the HB dominated regime and eective barrier height extracted from the I-V characteristics. However, to use the I-V characteristics to extract the eective barrier height, one would need to assume the Richardson constant. Since the n-Be plot is coupled with the ln(A )-Be plot to extract the true Richardson constant, ase suming a Richardson constant value for the n-Be is not justied. In order to overcome this limitation, an iterative approach can be employed. To begin, an initial guess for A is chosen to allow construction of the n-Be plot. The homogeneous barrier height can then be extracted from the n-Be plot and coupled with the ln(A )-Be plot, so that a new estimate of the A value can be obtained. e The new A value can then be used to modify the n-Be plot, and the process is repeated until the desired convergence criteria is reached. Application of the proposed methodology to emerging semiconductors such as the WBG class is particularly useful since experimental verication of the Richardson constant is largely hindered due to the lack of availability of good quality Schot-

88 tky diodes. As suggested by the above discussion, even modest ideality factors can result in a great scatter in the extracted Richardson constant. Consequently, the Richardson constant for WBG semiconductors such as ZnO, GaN is not very well established. In the following sections, we discuss the application of this method to the determination of Richardson constant of n-ZnO and n-GaN.

3.5

Application to IrOx/n-ZnO I-V -T characteristics

Previously published temperature dependent studies on ZnO Schottky diodes report high ideality factor values (n > 1.3), and as a result, the extracted A values (about 0.2 A cm2 K2 ) are far lower [134, 135] than the theoretical value. Recent studies indicate that nearly-ideal Schottky contacts to ZnO can be obtained through modied deposition techniques [136]. Nevertheless, we nd that the extracted A values can still exhibit signicant diode-to-diode variation. In this work, we investigate the I-V -T characteristics of multiple low ideality factor SBDs fabricated using 300 m diameter iridium oxide (IrOx ) Schottky contacts on the m-plane (1 100) face of a melt grown bulk ZnO wafer from Cermet, Inc. (USA). A net donor concentration of 1 1017 cm3 was determined from capacitance-voltage measurements. The fabrication procedure for these IrOx diodes follows the methodology described in detail elsewhere [136]. Diode fabri-

89

Figure 3.9. Typical Richardson plot extracted from I-V -T data (shown in the inset) of a Schottky contact to n-ZnO. From the I-V data at dierent temperatures, n and Isat can be extracted using Eq. 3.1.

cation was carried out by Dr. Martin Allen at the University of Cantebury, New Zealand. The wafer was mounted on a hot stage, and the temperature was controlled and monitored using a Temptronics temperature controller, chromel-alumel thermocouple and a Keithley 2000 temperature measurement system. Electrical characterization was performed using a Keithley 4200 semiconductor characterization system. A typical Richardson plot of ln(Isat /AT 2 ) versus 1/T (shown in Fig. 3.9) can be constructed from the I-V -T characteristics (Fig. 3.9 inset) of the diodes tested in this study using Equations 3.1 and 3.4. Table 3.1 shows the eective Richardson constant (A ), eective barrier height (Be ) and ideality factor e extracted for several devices. The most important observation from Table 3.1 is that the extracted values of A vary over a wide range. We also note that the e

90 extracted values of A are signicantly dierent from the theoretically predicted e value [135] for n-type ZnO of 32 A cm2 K2 .
Device No. 1 2 3 4 A (A cm e 2.0 1.7 6.1 0.8
2

K2 )

Be (eV) 0.82 0.82 0.86 0.78

n (295 K) 1.12 1.12 1.09 1.17

Table 3.1. Extracted eective Richardson constant and barrier height values for dierent devices obtained using the original Richardson plot

Figure 3.10 shows the linear correlation between ln(A ) and Be . The homoe geneous A value is obtained by extrapolation to Be = B . The homogeneous barrier height B can be determined from a plot of the eective barrier height versus the ideality factor for multiple SBDs. B is obtained by extrapolating the Be -n plot to n = nif , where nif is the image force controlled ideality factor, [137] which has a value of 1.028 for these SBDs. Figure 3.11 shows the Be -n plot for our SBDs from which a homogeneous barrier height of 0.91 0.01 eV is extracted. Using this value, Fig. 3.10 yields a homogeneous Richardson constant for n-ZnO of 27 7 A cm2 K2 , in very close agreement with the theoretically expected value of 32 A cm2 K2 . From Eq. 3.27, it can be seen that when the eective barrier height is lower than the homogeneous barrier height, the extracted Richardson constant tends to be lower than the expected Richardson constant. Although the HB regime is most amenable for the Richardson plot, the extracted Richardson constant value can still be lower than the expected value even when data are collected

91

Figure 3.10. Linear correlation between ln(A ) and Be obtained from the Richarde son plots for several devices.

in this regime. As the eective barrier height approaches the homogeneous barrier height, the eects of BHI become negligible and the extracted A approaches the homogeneous value. The present approach overcomes some of the diculties with other commonly employed approaches, which rely on modifying the original Richardson plot in dierent ways [124, 16, 120, 138, 122]. Methods focusing on incorporating the eects of BHI tend to extract Tungs patch parameter () from the I-V -T characteristics. Unfortunately, a unique patch parameter value is not possible from an I-V -T tting exercise due to the presence of multiple solutions. Hence, these approaches do not oer an accurate method to account for BHI on the obtained Richardson constant value. Instead, we have utilized a linear correlation between the eective Richardson constant and barrier height values based on Tungs BHI model. The method has been used to extract the Richardson con-

92

Figure 3.11. Be -n plot used to determine the homogeneous barrier height of the IrOx /n-ZnO Schottky diode.

stant of n-type ZnO using I-V -T characteristics measured on IrOx /n-ZnO Schottky diodes. Using a homogeneous barrier height value of B = 0.910.01 eV (obtained from the Be -n plot), the linear correlation between ln(A ) B yields a homogeneous Richardson constant value of 27 7 A cm2 K2 . The obtained Richardson constant value is in very close agreement with the theoretically expected value of 32 A cm2 K2 and is, by far, the closest to the theoretical Richardson constant. The error bars are due to slight variations in the ln(A )-Be and n-Be plots that e occur as a result of the selected bias range used for parameter extraction and also diode-to-diode variations. Establishing the Richardson constant of n-ZnO using the proposed approach is one of the main contributions of this thesis. To further corraborate the approach, the application of the proposed method to determine

93 the Richardson constant of n-GaN from the I-V -T characteristics of Au/Ni/n-GaN Schottky diodes is described next.

3.6
3.6.1

Application to Au/Ni/n-GaN I-V -T data

Fabrication procedure

A GaN epi-layer doped with Si grown on a sapphire substrate was used for Schottky diode fabrication. Prior to the ohmic contact and Schottky metal deposition, the sample surface was cleaned using 10% HCl for 45 s. The ohmic contact was formed by depositing Ti/Al/Ni/Au layers of 30/120/50/20 nm thickness using ebeam evaporation followed by rapid thermal annealing at 800 for 60 s. Circular contacts (area = 103 cm2 ) of Ni/Au (50/150 nm) were deposited using e-beam evaporation, and the contacts were dened using lift-o. A net donor concentration of 1 1017 cm3 was determined from capacitance-voltage measurements of the Schottky contacts.

3.6.2

Device characterization

For the I-V -T measurements, the sample was mounted on a hot stage, and the temperature was controlled and monitored using a Temptronics temperature controller, chromel-alumel thermocouple and a Keithley 2000 temperature measurement system. Electrical characterization was performed using a Keithley 4200 Semiconduc-

94
V (V) a 0.5 0.6

0.3 -3.5 -4.5

0.4

0.7

0.8

Increasing T

log (I/Amps)

-5.5 -6.5 -7.5 -8.5 -9.5

T (K) 320 340 360 380 400 420 440

n 1.45 1.33 1.21 1.15 1.10 1.07 1.05

Figure 3.12. Typical I-V -T characteristics measured for Au/Ni/n-GaN Schottky diodes

tor Characterization system. I-V -T characteristics of the Au/Ni/n-GaN Schottky diodes were measured from 320440 K, and a typical plot on a semi-log scale is shown in Figure 3.12. The diodes exhibit an ideality factor of about 1.45 at T = 320 K, and the ideality factor decreases to about 1.05 at T = 440 K. The high ideality factor values obtained at lower temperatures can be attributed to the presence of barrier height inhomogeneities. Contribution due to eld emission can be neglected due the low doping density levels in these diodes. With increasing temperature the low barrier region contribution becomes less signicant, and the current conduction becomes spatially homogeneous (ideality factor close to one). Figure 3.13 shows a typical Richardson plot obtained from the I-V -T data of the n-GaN Schottky diodes. As evident in Figure 3.13, the eect of BHI is manifested as a curvature in the original Richardson plot.

95

Figure 3.13. Typical Richardson plot obtained for the Au/Ni/n-GaN Schottky diode

Applying Equations 3.3 and 3.4 to the I-V -T data measured in the high temperature regime, we obtain the barrier height and Richardson constant for dierent devices. Due to the presence of BHI, these values would be expected to dier from the homogeneous values and are deemed as eective ones. Table 3.2 shows the extracted barrier height and Richardson constant values for dierent devices. The extracted Richardson constant values show a scatter over several orders of magnitude and are, also, orders of magnitude lower than the theoretical value of 26.4 A cm2 K2 . Depending on the extent of BHI, the extracted Richardson constant is found to vary greatly from device to device. Figure 3.14 shows the correlation observed between the extracted barrier height and Richardson constant values on a semi-log scale. As suggested by our preceding discussion, as the barrier height increases towards the homogeneous barrier height, the extracted Richardson constant value increases from a low value towards the

96

Device No. 1 2 3 4

A (A cm e 1.3 3.2 7.1 3.1

K2 )

Be (eV) 0.88 0.89 0.77 0.82

n (380 K) 1.22 1.18 1.28 1.25

102 102 104 103

Table 3.2. Extracted Richardson constant values for dierent GaN Schottky diodes obtained using the original Richardson plot

Figure 3.14. Linear correlations between n-Be values and Be -ln(A ) values e

expected Richardson constant. Extrapolating the observed linear correlation to the point where the barrier height equals the zero-bias barrier height, we can obtain a good estimate of the actual Richardson constant value. The n-Be plot is shown in Figure 3.14 and can be used to obtain the zero-bias barrier height. A zero-bias barrier height of 1.13 0.01 eV is obtained by extrapolating the n-Be plot to the image force controlled ideality factor, nif = 1.01 (using Eq. 3.19). A homogeneous Richardson constant value of 26 6 A cm2 K2 can be

97 obtained using Figure 3.14 and B0 . The homogeneous Richardson constant is in excellent agreement with the theoretically expected value of 26.4 A cm2 K2 [139]. It is important to note that a wide range of A values have been reported in the literature [140, 141, 142, 143, 144]. The discrepancy between experimentally observed A and theoretically expected value is typically attributed to inferior diode quality. However, even for diodes exhibiting low ideality factor values, the extracted Richardson constant can vary over orders of magnitude. The proposed approach overcomes this diculty by ltering the eects of BHI on the extracted Richardson constant value.

3.7

Summary of results

Previous approaches to extract the Richardson constant, and the assorted modications to the original Richardson plot to account for dierent non-ideality contributions, are described. Unfortunately, the currently employed methods can provide inaccurate results and fail to eectively lter the BHI eects. In this chapter, we have elaborated upon these shortcomings, and have also provided a new approach we recently proposed. In this chapter, this method is applied to IrOx /n-ZnO and Au/Ni/n-GaN Schottky diodes as an example. The new method is based on Tungs BHI model and takes advantage of a linear correlation between the extracted Richardson constant and the eective barrier height. Based on the preceding analysis and discussion, we can provide a few sim-

98 ple guidelines that are useful to account for the eects of BHI on the extracted Richardson constant. One of the key points to be noted is that even in the case of moderate ideality factors ( 1.1), the extracted Richardson constant can be widely dierent than the expected or actual value. It has been dicult to extract an accurate Richardson constant using previous approaches due to large variations from device to device. When the Richardson plot exhibits bowing, higher measurement temperatures should be used, instead of using the modied Richardson plot. As suggested earlier, the modied Richardson plot does not necessarily provide an accurate method to extract the Richardson constant. In the case of MS diodes with low homogeneous barrier heights, adequately high temperatures might not be accessible since I-V -T measurements are further complicated due to series resistance eects or due to interfacial reactions at high temperatures. After choosing the appropriate temperature window, the original Richardson plot can be used to extract the eective Richardson constant and eective barrier height for each of a set of devices. These values can then be used to construct the ln(A ) vs.Be e plot. In order to obtain the homogeneous Richardson constant, one would need the zero-bias barrier height, and this can be obtained from the n-Be plot. The n values in the HBD regime along with the eective barrier height can be used to construct the n-Be plot. Using the proposed linear correlation and the widely-used n-Be plot, we have analyzed I-V -T data from the simulated semi-Gaussian BHI model, IrOx /n-ZnO

99 and Au/Ni/n-GaN Schottky diodes. Excellent correlation between the expected and extracted values has been shown for these cases. The proposed method oers a simple way to extract Richardson constant, and, in essence, is similar to the n-Be analysis. The proposed method is particularly valuable for semiconductor systems that are still shrouded in uncertainty due in part to immature crystal growth and processing methodology. For moderately doped semiconductors, Schottky diode parameters extracted from the I-V characteristics are heavily inuenced by the presence of BHI. The work presented in this article has dealt with re-visiting the applicability of the commonly employed approaches to the extraction of Richardson constant. The need for a methodology that relies on application of BHI principles and, thereby, accounts for the eects of BHI on the extracted Richardson constant has been realized. An explicit relation between the extracted Richardson constant and the BHI parameters serves as the basis for the proposed approach. This approach has been shown to provide an accurate way to extract the Richardson constant from the I-V -T characteristics of an inhomogeneous Schottky barrier diode.

Chapter

Extracting the Schottky barrier height from axial contacts to semiconductor nanowires

4.1

Introduction

Nanoscale contacts are important for novel devices based on semiconductor nanowires such as eld eect transistors and chemical and biological sensors [145, 146]. For a variety of reasons, the behavior of these contacts can depart signicantly from that of their microscale counterparts. For example, in the case of nanoscale contacts to a bulk semiconductor, barrier width thinning is predicted by solving the Poisson equation in this geometry, and an increase in tunneling current is experimentally observed [147, 148]. Apart from geometric eects, Fermi-level pinning at the inter-

101 face between the metal and semiconductor might be reduced for nanoscale contacts compared to bulk Schottky contacts [149, 102]. Experimental data on the current-voltage (I-V ) characteristics of Schottky contacts to dierent semiconductor nanowires (such as Si, ZnO and GaN) show deviation from the conventional thermionic emission theory [150, 98, 151]. Large ideality factors have been observed in Schottky contacts to n-GaN nanowires [151], whereas room-temperature ideality factors of about 1.2 for Ni contacts to n-type Si nanowires [150], or 1.1 for Pt contacts to n-ZnO [98] nanowires and axial -Ni2 Si/Si nanowires [150], have been reported. A tunneling current contribution has been suggested to be the source for the observed deviation from thermionic emission theory. In addition, the Schottky barrier depletion width can be inuenced by surface charge present along the adjacent surface of the nanowire [152]. For these reasons, the Schottky barrier height extracted from the current-voltage (I-V ) characteristics might be signicantly dierent from the actual barrier height. So far, a systematic investigation of the eect of the nanowire surface on the metal/nanowire Schottky diode I-V characteristics and the means to extract the true Schottky barrier height from the I-V characteristics has not been reported. The goal of this work is to analyze simulated I-V characteristics of an axial Schottky barrier diode to a semiconductor nanowire with a surround gate in order to devise a method to accurately extract the Schottky barrier height from experimental I-V data. A surround gate structure provides symmetric control over the nanowire surface and facilitates a

102

Figure 4.1. (a) Schematic of a surround-gate nickel silicide/n-Si NW Schottky diode structure. The specic metals shown were used in the nanofabricated device described later in the paper, while the simulations are more general for metallic and Si segments. (b) Cross-sectional schematic showing gate and silicide overlap.

systematic study of the eect of surface charge on the I-V characteristics. The surround-gate structure is also of importance because of its use in nanowire FETs (NWFETs) and is expected to help further device scaling [153, 154]. A key nding of the study is that I-V characteristics as a function of the surround gate bias are required to extract the true barrier height of the metal/semiconductor Schottky barrier diode. The range of required gate biases depends on the nanowire doping density, trap density at the oxide/nanowire interface, and measurement temperature. Under the inuence of gate bias, the relative contributions of tunneling and thermionic emission can be modulated, and spatially non-uniform tunneling current density is found to be the key factor distorting the simulated I-V characteristics. Application of the proposed methodology to experimental data collected from a surround-gate -Ni2 Si/n-Si nanowire device is nally presented.

103

Figure 4.2. Typical I-V characteristics simulated using SDEVICE for the structure shown in Figure 4.1.

4.2

Simulated device structure and parameters

Figure 4.1(a) shows a schematic of the surround gate nanowire Schottky diode structure that we have used in our study. The device structure consists of an 0.8 m long lightly doped n-type nanowire followed by a 0.2 m long n+ segment. Doping of the lightly doped segment can be varied and is treated as a simulation parameter in our study. An oxide shell of 10 nm thickness surrounds the 25 nm radius nanowire, and an aluminum gate wraps around to form a cylindrical metaloxide-semiconductor structure. Traps distributed uniformly across the forbidden gap are assumed to be present at the Si/SiO2 interface along the nanowire length. Interface trap density is treated as a simulation parameter to assess its eect on conduction through the nanowire Schottky diode. The nanowire rests on a SiNx isolation layer deposited on an n-type Si wafer. A Schottky contact is dened

104 on the lightly doped side, and the barrier height in this simulation depends on the work function of the metal. However, the simulation results are valid even if Fermi-level pinning is present, in which case, we are simply running a simulation for a particular Schottky barrier height. The barrier height aects the currentvoltage-temperature (I-V -T ) characteristics and also the relative contributions of thermionic emission and thermionic eld emission. An ohmic contact is dened on the heavily doped segment. In the actual surround gate (SG)-NW Schottky diode described later in this paper, the Schottky contact is a metal silicide formed by rapid thermal annealing of the deposited contact metal. The silicidation process results in a cross-sectionally uniform and an atomically abrupt metal silicide/nanowire contact that can be reproducibly fabricated [155]. However, the contact silicidation process does not guarantee a self-aligned silicide-gate structure and almost always results in some amount of gate overlap onto the dielectric-coated silicide segment. Figure 4.1(b) shows a cross-sectional schematic of the possible overlap between the gate and the silicide segment. The impact of the resultant gate overlap on the conduction through the silicide/NW Schottky barrier is also studied using device simulations. The device structure is simulated using Sentaurus Structure Editor, and the device characteristics are simulated using the 3D Sentaurus Device (SDEVICE) simulator. Poissons equation in 3D and the current continuity equations with trap statistics, along with the appropriate boundary conditions, are solved using

105 the device simulator to obtain the I-V -T characteristics. The simulation setup is used to explore the eect of nanowire doping, interface trap density, gate bias, Schottky barrier height and temperature on the conduction properties of the surround-gate nanowire Schottky diode.

4.3

Gate bias eects

Forward bias I-V characteristics as a function of the surround gate bias were obtained for a matrix of the listed input parameters. Figure 4.2 shows the typical I-V characteristics (T = 300 K) obtained for a gate sweep from -1 V to +1 V. An input barrier height of 580 meV and NW doping density of 1016 cm3 were used in this case. Negative gate voltage corresponds to a surface inversion condition for the portion of the NW unaected by the Schottky barrier. With increasing gate voltage, the nanowire surface switches to surface depletion followed by accumulation. Under ideal thermionic emission theory for bulk contacts, the current-voltage relationship is given by

ln

I 1 exp(Va )

Va Be + ln(AA T 2 ). n

(4.1)

In Eq. 4.1, I is the total current owing through the diode under application of a forward bias of Va , (q/kT ) is the inverse thermal voltage, A is the crosssectional area of the diode, A is the Richardsons constant and T is the absolute

106

Figure 4.3. Depletion region edge prole under (a) surface depletion and (b) surface accumulation conditions.

temperature. The constants q and k are the electronic charge and Boltzmann constant, respectively. The diode behavior is characterized by the conventional Schottky diode parameters; n is the ideality factor and Be is the eective barrier height. In the case of an ideal Schottky contact, n approaches unity and the eective barrier height approaches the homogeneous barrier height B . A family of I-V curves (a typical case shown in Fig. 4.2) is generated by stepping through appropriate gate-to-source voltages Vgs and sweeping the Schottky contact from 0 to + 1V. In each case, the I-V data are then treated as would normally be done for a planar Schottky barrier diode. As the gate voltage is increased, the

107

Figure 4.4. Typical n-Be plot constructed using values extracted from I-V characteristics at dierent gate biases.

portion of the NW unaected by the Schottky barrier shifts from surface depletion to surface accumulation. In the surface depletion regime, the eective diode area is reduced and results in an increase in apparent barrier height. As the gate voltage is swept into the surface accumulation regime, the apparent barrier height decreases. The decrease in the apparent barrier height is attributed to a tunneling contribution and is examined in detail later. The relative extent of electrostatic control over the semiconductor NW exerted by the Schottky contact and the surround gate is a result of the interplay between several parameters: NW doping density, applied bias, interface trap density, temperature and Schottky barrier height. Close to the metal/nanowire interface, the nanowire xed and free charge densities are strongly inuenced but not exclusively controlled by the Schottky contact. Away from the metal/nanowire interface, the surround gate provides symmetric control over the

108 nanowire surface and can be used to accumulate, deplete or invert the surface of the nanowire. For gate voltages less than the at band voltage (VFB ), the nanowire surface is depleted, and for Vgs > VF B , the nanowire surface is accumulated. Electron concentration contours are shown in Figure 4.3 for surface depletion and surface accumulation conditions. Each case results in a curvature to the axial Schottky barrier depletion region edge. Under surface accumulation conditions, the barrier width thins along the nanowire periphery. Also, with increasing gate bias, the depletion region edge moves closer to the MS interface. Apart from thermionic emission over the barrier, gate bias dependent barrier thinning can enhance tunneling contributions across the periphery of the contact. Consequently, the current-voltage (I-V ) characteristics in the surface accumulation conditions depart from the ideal thermionic emission theory giving rise to n > 1. It should be noted that even under zero gate-bias conditions, the depletion region edge can vary radially, and the sign and degree of this variation depends on the nature and density of interface traps on the nanowire surface along its length. The surround-gate architecture provides maximum control over the nanowire surface and allows us to override the eect of interface traps on the nanowire conduction properties.

109

Figure 4.5. Linear correlation between n and Be for two dierent input barrier height cases. Gate bias values ranging between 0.21 V were used in both cases.

4.4

n-B analysis

Simulated I-V data obtained from SDEVICE are treated in this work in a similar fashion to the I-V characteristics of a bulk contact. An important distinction, however, is that the extracted ideality factor and eective barrier height are a function of the surround gate bias. An n-Be plot can be constructed using the gate bias dependent ideality factor and eective barrier height values. A typical n-Be plot is shown in Fig. 4.4 and exhibits certain unique features as discussed below. For Vgs > VFB , the nanowire surface is accumulated and carrier conduction is due to a combination of thermionic emission and tunneling processes. The tunneling current contribution increases with increasing gate bias and results in an increase in ideality factor and a corresponding decrease in the eective barrier height. At gate bias values that result in moderate accumulation at the nanowire surface, a linear correlation between n and Be is observed, and this linear region can be

110

Figure 4.6. Eect of nanowire doping density on the n-Be plot. An input Schottky barrier height of 580 meV, oxide/nanowire interface trap density of 1 1012 cm2 eV1 and T = 300 K have been assumed.

extrapolated to the actual barrier height. Under deep accumulation conditions, the tunneling current contribution becomes dominant and results in larger ideality factor values. For these slightly larger n values, a departure from the n-Be linear correlation is observed. For Vgs < VFB , the eective area for conduction is reduced due to depletion induced by the surround gate. As the nanowire is pushed deeper into depletion, the eective area for conduction further decreases and results in an increase in both the ideality factor and eective barrier height values. Figure 4.5 shows the n-Be plot for the cases of two dierent input barrier heights (580 and 730 meV). The nanowire is assumed to be doped n-type with a donor density of 1016 cm3 and is simulated at 300 K. Ideality factor and Be

111

Figure 4.7. Extracted ideality factor as a function of Vgs for dierent nanowire doping densities.

values obtained at dierent gate bias conditions are used to generate Fig. 4.5, and the linear region can be extrapolated to n = 1 to obtain the input barrier height in both cases. The minor eect of image force lowering is discussed later in the paper. The linear correlation has been observed under dierent conditions of interface trap density, NW doping density, input barrier height, gate overlap and temperature. Depending on the MS interface barrier height, nanowire doping density, gate overlap and temperature, the tunneling current contribution to the total current diers. In order to verify the applicability of the n-B plot to determine the true barrier height, I-V -T characteristics were obtained for dierent test cases by varying these simulation parameters and are examined next.

112

Figure 4.8. Eect of temperature on the n-Be plot for the case of a nanowire doped to 1016 cm3 with an interface trap density of 1012 cm2 eV1 . In this case, an input Schottky height of 580 meV has been used.

4.4.1

Eect of NW doping density

Figure 4.6 shows the n-Be correlation obtained for three dierent NW doping densities (1016 , 1017 and 5 1017 cm3 ). In this case, we have assumed the Si/SiO2 interface to be devoid of interface traps and the temperature is set to 300 K. Larger tunneling current contributions are expected at higher doping densities, so an increase in ideality factor is observed for higher doping density. Figure 4.7 shows the dependence of the extracted ideality factor on the applied gate bias. At a given gate bias in surface accumulation condition, the ideality factor increases with increasing nanowire doping density (Fig. 4.7), but the doping density does not have a noticeable eect on the n-Be plot, as seen in Figure 4.6. The n-Vgs plot is useful

113 for estimating the gate voltage regime for surface accumulation conditions. As the gate voltage is swept from surface depletion to surface accumulation conditions, the ideality factor decreases initially and increases thereafter. As a consequence,
min min the n-Vgs plot exhibits a minimum at a certain gate voltage (Vgs ). For Vgs > Vgs ,

the surface moves deeper into surface accumulation and an increase in the ideality
min factor with gate voltage is observed. For Vgs < Vgs , the ideality factor decreases

with increasing gate voltage as the surface moves from a depleted condition to at band condition.

4.4.2

Eect of temperature

Figure 4.8 shows the n-Be correlation at two dierent temperatures (300 and 250 K). A Schottky barrier height of 580 meV, nanowire doping density of 1016 cm3 , and an interface trap density of 1012 cm2 eV1 were used in this case. With decreasing temperature, the contribution due to thermionic emission is reduced, and we observe larger deviations from ideal behavior. Hence, for a given gate bias in the surface accumulation condition, the ideality factor increases with decreasing temperature. Figure 4.9 shows the n-Vgs variation for the two dierent temperatures, with higher ideality factor values for T = 250 K. Extrapolating the linear correlation from an n-Be plot at either of the temperatures yields a barrier height of 580 3 meV.

114

Figure 4.9. n-Vgs variation for dierent temperatures.

4.4.3

Eect of interface traps

Unlike the case we have examined so far, real silicon/oxide interfaces often contain traps. In a bulk Schottky contact, traps are present at the MS interface, and these defect states can pin the Fermi level, thereby dictating the obtained barrier height. A local variation of the interface trap density and their energies have been postulated to give rise to lateral variations in the barrier height [25]. In the case of a Schottky contact to a nanowire, the reduced size of the contact makes less likely such lateral variations of barrier height. However, traps present at the adjacent oxide/nanowire interface can inuence conduction at the metal/NW contact. In these simulations, interface traps distributed uniformly across the energy band gap and with electron and hole capture cross-section values of 1014 cm2 are assumed to be present along the Si/SiO2 interface. The I-V characteristics as a function of

115

Figure 4.10. Trapped interface charge (for dierent interface trap densities) as a function of the applied gate bias.

gate bias have been simulated for dierent interface trap densities. The primary eect of interface traps is to increase the at band voltage and postpone the surface accumulation condition. The presence of xed oxide charge shifts the at band voltage, but interface traps smear the eect of gate voltage. Under the application of a gate bias, a part of the gate voltage is used in free carrier accumulation, and the rest results in an increase in trapped interface charge. However, the increase in interface trapped charge with gate voltage is not linear and implies a gate bias dependent interface trap capacitance. Figure 4.10 shows the trapped interface charge as a function of the applied gate voltage. The onset of strong surface accu-

116

Figure 4.11. Eect of interface trap density on the n-Vgs plot.

mulation occurs when the gate voltage dependence of the interface trapped charge saturates. Any change in the gate voltage is therefore utilized in accumulation of free carriers at the surface and also in modulating the trapped charge at the oxide/nanowire interface. At higher interface trap densities, signicantly higher gate voltages are required to saturate the trapped interface charge. Figure 4.11 shows the variation of n with Vgs for dierent interface trap densities. With increasing trap density, the MS depletion region edge is pinned more eectively by the oxide/nanowire interface traps. Hence, for a given gate bias, the MS depletion region is found farther into the nanowire away from the MS interface, resulting in a lower tunneling current contribution at a given gate bias. As a result, for a given gate bias, the extracted ideality factor is lower for higher interface trap densities. Figure 4.12 compares the n-Be plot for dierent interface trap densities. The n-Be plots display a curvature at low n values that becomes more prominent

117

Figure 4.12. n-Be plot for dierent interface trap densities: (a) no interface traps with 0 < Vgs < 0.5 was used for the linear correlation, (b) 5 1011 cm2 eV1 traps with 0.2 < Vgs < 0.7 was used for the linear correlation, and (c) 1 1012 cm2 eV1 traps with 0.4 < Vgs < 1 was used for the linear correlation. An input Schottky barrier height of 580 meV, nanowire doping density of 1016 cm3 , and T = 300 K have been assumed.

with increasing trap density. The curvature results from using n-Be values from the surface depletion conditions. For these values, the applied Vgs is lower than
min the corresponding Vgs , and in this regime, both the ideality factor and barrier

height decrease with increasing gate bias. At a high enough gate bias, the surface is under accumulation irrespective of the surface trap density, and in this regime, the n-Be plot is linear and can be used to extrapolate to the input barrier height. Compared to a planar Si/SiO2 interface, the nanowire Si/SiO2 interface might have a higher interface trap density. In the case of a nanowire, the oxide growth occurs

118 along dierent crystal orientations (and at dierent rates). Interface trap densities on the order of 2 1012 cm2 eV1 have been estimated based on subthreshold slope calculations for Si NWFETs [156]. However, the interface trap density could be reduced through post-oxidation annealing treatment [157, 158, 159].

4.4.4

Eect of gate overlap

Depending on the gate-silicide overlap, the capacitive coupling eect of the gate on the MS depletion region can dier and is examined here. Figure 4.13 shows the n-Vgs plot for dierent cases of gate overlap. The self-aligned case is when there is no gate overlap on the silicide segment. Under surface accumulation conditions, for a given gate bias, the ideality factor increases with increasing overlap. For larger gate overlap, the peripheral barrier thinning eect is enhanced, resulting in a larger tunneling contribution for a given gate bias. Figure 4.14 shows the correlation between n and Be for dierent overlap conditions. In all cases, a barrier height of 580 7 meV is obtained by extrapolating to n = 1 and matches the input barrier height used for the simulations.

4.4.5

Image force lowering eect

In the case of a homogeneous Schottky contact to a bulk semiconductor, the eective barrier height equals the zero-bias barrier height (B0 ) and can be related to

119

Figure 4.13. Eect of gate overlap over the n-Vgs plot.

Figure 4.14. Eect of gate overlap over the n-Be variation. An input Schottky barrier height of 580 meV, nanowire doping density of 1016 cm3 , and interface trap density of 1012 cm2 eV1 have been assumed.

120 the homogeneous barrier height (B ) by

B0 = B B ,

(4.2)

where B is the barrier lowering contribution due to the image force eect. The extent of barrier lowering due to the image force depends on the substrate doping density (Nd ) and is given by [137]
1 4

B =

q 3 Nd Vbb 8 2 2 s 3 0

(4.3)

In Eq. 4.3, Vbb is the band bending,

is the permittivity of free space, and

and

are the static and optical dielectric constants. The image force barrier lowering

eect also results in a slight increase in the ideality factor to nif and is given by [137]
1 4

1 nif = 1 + 4

q 3 Nd 8 2
3 3 2 s 0 Vbb

(4.4)

It should be noted that the eective barrier height and the image force controlled ideality factor show weak dependence on the applied bias. For moderately doped silicon, B is typically about 1030 meV, and nif ranges from 1.011.03. Apart from the gate induced tunneling current contribution, the eective barrier height is also aected to a small extent due to the image force eect. The image

121

Figure 4.15. Eect of image force lowering on the n-Be plot for the two dierent doping densities. An interface trap density of 1012 cm2 eV1 , input Schottky barrier height of 580 meV, and T = 300 K have been assumed.

force barrier lowering contribution would be of relatively greater signicance for nanowires with a higher doping density. Fig. 4.15 shows the eect of barrier lowering on the n-Be plot generated from room temperature I-V characteristics for the case of two dierent NW doping densities (1016 and 1017 cm3 ). The input barrier height is 580 meV and a gate overlap of 200 nm is used in both cases. The n-Be plot should be extrapolated to n = nif to obtain the zero-bias barrier height. The homogeneous barrier height can be obtained from the zerobias barrier height using Eq. 4.2 and the estimated Be value. Using the n-Be plots shown in Fig. 4.15, a zero-bias barrier height of 560 and 550 meV can be obtained for 1016 and 1017 cm3 NW doping densities, respectively. The zero-bias barrier heights are slightly lower than the homogeneous barrier height, and with increasing NW doping density, the zero-bias barrier height value is further lowered.

122 B values of 20 meV and 30 meV are estimated using Eq. 4.3. Using the zero-bias barrier height and the corresponding B values, a homogeneous barrier height of 580 meV can be obtained irrespective of the NW doping density. In the case of low to moderate doping levels, the value of nif is close to 1 (1.01) and extrapolating to n = 1 yields a good estimate of the homogeneous barrier height, as is done in the earlier sections of this paper. In the preceding sections, dierent scenarios have been presented, and these cases illustrate the general applicability of the n-Be method to obtain the true barrier height of a MS nanowire contact. A linear correlation between the extracted n and Be is observed in inhomogeneous bulk Schottky diodes [132]. Although a linear correlation between n and Be is observed in the nanowire case as well, the origin of the correlation is entirely dierent. In the nanowire case, gate bias dependent tunneling current gives rise to deviation from ideality and is the reason for the correlation between n and Be .

4.5
4.5.1

Application to experimental data

Fabrication procedure

Silicon NWs were grown by the vapor-liquid-solid (VLS) method from a gold catalyst to a length of 16 m with lightly and heavily doped n-type segments [160]. The lightly doped n-type segment was grown rst to a length of 10 m with a

123 PH3 /SiH4 ratio of 1 104 , and then the heavily doped n-type segment was grown to a length of 6 m with a PH3 /SiH4 ratio of 2 103 . The SiNWs were soaked in Transene Au etchant to remove the Au tips from the nanowire and then thermally oxidized to form a 15 nm thick oxide shell surrounding the Si NW. Sacricial Ag electrodes were patterned on a Si wafer coated with 100 nm of SiNx using photolithography, and a local Al back gate was patterned between the two Ag electrodes. SiNWs with a 15 nm thick oxide shell were then electrouidically aligned to the Ag electrodes [161]. A window was next patterned over one of the Ag contacts (over one end of the nanowire) using photoresist, and the Ag electrode was etched away. Before depositing the Ni contact, a solution of 15% 10:1 BOE and 85% deionized water was used to remove the oxide shell surrounding the SiNW in the contact region. 80 nm of Ni was e-beam evaporated for the Schottky contact. A second window was opened to the second Ag electrode on the other end of the nanowire, and the Ag was again etched away along with the oxide shell surrounding the SiNW in this second contact region. 50 nm of Ti with a 50 nm cap of Al were then e-beam evaporated and used as the Ohmic contact to the SiNW. The Al top gate was then patterned on top of the local Al back gate to form a complete wrap-around gate surrounding the oxidized SiNW. Lastly, the devices were annealed at 550 for 240 s to form an axial nickel silicide segment that extended into the wrap-around gate such that the silicide/Si interface was surrounded by both the oxide shell of the SiNW and the Al wrap-around gate.

124 Note that the Ohmic contact does not react laterally down the nanowire under these conditions.

4.5.2

Electrical characterization

I-V characteristics were measured on a -Ni2 Si/n-Si NW Schottky diode at room temperature in a N2 environment using an Agilent 4156B Precision Semiconductor Parameter Analyzer. Figure 4.16 shows the n-Be plot obtained using the measured I-V characteristics at dierent gate bias values (0.5 < Vgs < 1.5 V). With increasing gate bias, the ideality factor increases and apparent barrier height decreases. In the case of the Sentaurus simulations, extrapolation of the linear n-Be plot to n = 1 yields the actual barrier height, neglecting image force lowering. Using the same principle, in the case of the experimental -Ni2 Si/n-Si NW Schottky diode, a barrier height of 557 meV is obtained by extrapolation to n = 1, where image force lowering is expected to be small for the lightly doped nanowires. A future publication will address the eect of nanowire diameter on the Schottky barrier heights extracted by this method.

4.6

Conclusions

I-V characteristics of surround-gate Schottky diodes to semiconductor NWs have been simulated using SDEVICE. I-V characteristics of nanowire Schottky diodes are highly sensitive to the adjacent semiconductor surface, and a surround gate

125

Figure 4.16. Linear correlation between n and Be obtained from experimental I-V characteristics.

provides symmetric control of the surface condition. Under surface accumulation conditions, a spatially non-uniform tunneling contribution can be signicant. The tunneling current contribution is gate bias dependent, and with increasing gate bias, the apparent barrier height decreases. As the gate bias is increased from surface depletion towards the at band condition, both the ideality factor and barrier height decrease together. This trend is in contrast with the surface accumulation conditions, wherein increasing the gate bias increases the ideality factor and decreases the eective barrier height. In this article, we have proposed a simple method for Schottky barrier height extraction from the I-V measurements of surround-gate Schottky contact to semiconductor nanowires. Spatially varying barrier width in these contacts has been shown to be the source for departure from thermionic emission, due to enhanced tunneling along the nanowire periphery. For a given metal/NW contact, the tun-

126 neling contribution can be modulated by varying the gate bias. Within limits, under surface accumulation conditions, a linear correlation between n and B has been observed, and extrapolating the linear correlation to n = 1 yields the input barrier height for Schottky barriers to lightly doped semiconductor nanowires. The
min n-Vgs plot exhibits a minimum at Vgs that signals the onset of surface accumula-

tion conditions. The linear correlation is shown to be valid considering the eects of NW doping, interface trap density, interface barrier height, temperature and gate overlap. In the case of nanowires with higher doping density, the image force lowering eect becomes important. Extrapolation of an n-Be plot to n = nif yields the zerobias barrier height (B0 ). The homogeneous barrier height can then be obtained using B0 and the estimated B value. The extrapolated barrier heights under dierent test conditions have been found to be in good correlation with the input barrier height. A linear correlation between n and B is also observed for the case of experimental data from Ni silicide/n-Si nanowire Schottky diodes, and extrapolation to n = 1 yields a barrier height of 557 meV. In the next chapter, we review the application of a modied-version of the charge pumping method to qualify the oxide/nanowire interface. The methodology presented therein can be used to characterize the oxide/nanowire interface. The proposed method can serve as basis for comprehensive experimental investigations on the eects of interface condition on the nanowire conduction properties.

Chapter

Low frequency three terminal charge pumping applied to silicon nanowire eld-eect-transistors

5.1

Introduction

Charge pumping (CP) is an important technique commonly used to assess gate oxide integrity and the overall reliability of metal-oxide-semiconductor eld-eect transistors (MOSFETs) [162]. In its basic form, CP allows for a quantitative measure of the oxide-semiconductor interface trap density. Variants of the method have been developed over the past few decades to obtain the spatial and energy distribution of traps, electron and hole capture parameters, and localized damage prole due to electrical stress [163, 164, 165]. Often coupled with transfer charac-

128 teristics, CP can be used to uncover dominant damage mechanisms under dierent accelerated test conditions, such as hot-carrier and Fowler-Nordheim stresses [166]. In a bulk MOSFET the conventional CP (CCP) method employs four device contacts (gate, drain, source, and substrate/body), and the CCP output is a substrate current generated under the action of a large signal gate pulse. However, with the continuous miniaturization and diversication of devices, the eld-eect transistor (FET) structure has evolved from planar bulk MOSFET to a variety of structures, such as the thin-lm transistor, silicon-on-insulator (SOI) FET, and the trench-gated U-shaped vertical MOSFET (UMOSFET). In these structures, substrate/body contact is generally unavailable; hence, applying CCP to characterize these devices is not possible. However, we have recently modied the CCP technique and developed a three-terminal CP (3T-CP) version, which can be applied to three-terminal FETs [167]. Short channel eects continue to pose signicant challenges to CMOS operation, and these eects are further aggravated with scaling [168]. As device dimensions shrink, encroaching source and drain electric eld eects on the channel weaken gate control. In an eort to reinforce gate control over the channel, the planar CMOS multiple gate, FinFET, gate and eventually surround gate architecture are being considered [169]. A surround gate FET allows for maximum electrostatic control by the gate over the surface and is expected to provide good short channel eect tolerance. The surround gate-nanowire FET (SG-NWFET) is an important

129 candidate for non-planar CMOS and is being studied as a viable device design to combat short channel eects. In addition, FETs based on silicon nanowires grown using the vapor-liquid-solid (VLS) technique have been demonstrated for applications such as high performance vertical transistors [170] and chemical and biological sensors [146]. The oxide/nanowire interface plays an important role in determing the performance of these devices and its detailed study is, hence, critical. Charge pumping is indispensable to such a study, and its application to NWFETs can render available valuable information on defect densties and longterm reliability. However, the SG-NWFET also lacks a substrate/body contact and is, therefore, a three-terminal FET that is not amenable to CCP. We herein apply 3T-CP to silicon SG-NWFETs to measure trap density in the vicinity of the Si/SiO2 interface. We show that a strong CP output is obtained and can be used to probe interface and near-interface trap densities. This report describes the rst application of the CP technique to nanowire transistor structures.

5.2

Experimental procedure

Figure 5.1(a) shows a cross-sectional schematic of the active device region. Axially doped (n+ -p -n+ ) Si NWs are grown using the VLS growth technique as discussed in ref. [157]. The SiNW diameter is 34 nm as determined by eld emission scanning electron microscopy (FESEM). The NW structure is thermally oxidized using

130

Figure 5.1. a) Cross sectional schematic of the active device segment b) Schematic of the 3T-CP setup.

dry O2 at 700 for 4 h to form a uniform 16 nm thick oxide shell. Subsequently, the n+ ends of the NW are aligned onto Ti/Au contacts using electric-eld-assisted assembly. A Ti/Au(20/60 nm) global-back-gate is sputter depsoited onto the backside of the n++ substrate. The source and drain contacts are dened over the n+ nanowire segment using e-beam lithography. Ti/Au (80/40 nm) was deposited using e-beam evaporation to form the top-gate to complete the non-self-aligned surround-gate structure. The entire active structure rests on a SiNx isolation layer on a heavily doped silicon substrate. Detailed description of the device fabrication procedure is given elsewhere [157]. For transfer characteristics measurements, current owing from the drain to source (Ids ) is measured while the gate and drain contacts are biased relative to the source contact. Keithley 238 source and measure units (SMU) are used to apply the appropriate bias and measure the resultant current. Voltage pulses required for charge pumping are generated using an Agilent 33250A signal generator. Fig. 5.1(b) shows the biasing and measurement conguration used for the 3TCP measurements. Details of the 3T-CP method are given in ref. [167]. Briey,

131 however, 3T-CP utilizes a square voltage pulse (Vp ) of a given frequency, f , superimposed on a base gate voltage ramped between two values of a gate-to-source voltage Vgs . The charge pumping current, ICP , is the drain current measured as a function of Vgs . For our SG-NWFETs we used Vp = 2 V, f between 0.5 and 400 kHz, and Vgs between -1 and 0.25 V.

5.3

Results and discussions

The transfer characteristics of the SG-NWFET were measured at a drain-to-source voltage (Vds ) of 100 mV by sweeping the gate-to-source voltage (Vgs ) from -3 to +3 V. Figure 5.2 shows the measured transfer characteristics on a semi-log scale. The devices exhibit good on-to-o state current ratio (Ion /Io ) values exceeding 104 at a Vds of 100 mV. A threshold voltage value of 248 mV is extracted by extrapolating the linear portion of the transfer characteristics, and a linear transconductance (gm ) of 50.1 nS is obtained at the turn-on voltage. The inverse subthreshold slope (S) is 292 mV/decade and is signicantly higher than the ideal value of 60 mV/decade. The high value of S is indicative of a high interface trap density at the Si/SiO2 interface, and it is important to note that no eorts were made to optimize the processing of the SiO2 /Si interface in this device. A large interface trap density at the oxide/silicon interface can give rise to a strong CP signal, and this device is therefore a good candidate for the rst application of our 3T-CP method. Post-oxidation

132

Figure 5.2. Transfer characteristics measured by sweeping Vgs from -3 to +3V while holding Vds at 100 mV.

annealing treatments have been shown to greatly improve the interface quality and are planned for future devices [157, 171]. Subthreshold swing can be used to extract the average interface trap density [172] using

S = 2.3

kT q

1+

Cit Cox

(5.1)

In Eq. (5.1), Cit is the interface trap capacitance and Cox is the oxide capacitance. Using Eq. (5.1), an interface trap density value (Dit ) of 6 1012 cm2 eV1 is estimated from the subthreshold swing value. The interface trap density obtained

133 from the subthreshold slope measurements is used as a reference to compare the trap density value that will be obtained using 3T-CP method as described next. In the 3T-CP method as the base gate voltage is swept, the NW surface is pulsed between inversion and accumulation. During inversion, interface traps are populated by electrons coming from the drain and source ends of the device. During accumulation the trapped electrons recombine with incoming holes and the interface traps are, hence, emptied of electrons and are now ready to ll with electrons owing from the drain/source in the next inversion cycle. The charge pumping current, ICP , is measured at the drain end and is related to the interface trap density [167]. Fig. 5.3 gives ICP for dierent pulse frequencies. A clear dependence of ICP on f is shown in the gure, and this is expected to be the case for the low frequency charge pumping response. However, at higher frequencies (f > 50
max kHz), the maximum charge pumping current, ICP , is found to saturate and does max not exhibit a strong frequency dependence. ICP saturation with frequency is not

observed in our previous applications of 3T-CP to MOSFETs [167], although it apparently is the case for SG-NWFETs. Apart from being a three terminal device, the SG-NWFET has very limited supply of holes because of the minuscule neutral bulk volume. In each charge pumping cycle, a large fraction of the majority carrier holes would be lost due to recombination with the trapped electrons at the SiO2 /Si interface. At lower frequencies, these holes can be replenished by thermal generation in the depletion

134

Figure 5.3. 3T-CP signal in a SG-NWFET measured at dierent pulse frequencies.

region. The thermal generation rate is determined by the temperature dependent time constant for the process. At frequencies far greater than the thermal generation rate, the majority carrier concentration available for recombination is limited by the thermal generation process. Hence, at higher frequencies, the charge pumping current does not increase linearly with frequency and exhibits a saturation behavior. The above mechanism is suggested as a possible explanation for the
max observed saturation of ICP with f at high frequency levels. max The frequency dependence of ICP is generally taken to be of the form [162].

135

max Figure 5.4. ICP as a function of applied frequency and Qmax variation with ln(f ) CP measured in our SG-NWFET.

max Icp = qAg Dit s f

(5.2)

In Equation (5.2), Ag is the gate area, q is the electronic charge, Dit is the average interface trap density, and s is the surface potential change when the MOSFET switches from inversion to accumulation. One could use Eq. (5.2) in a
max linear plot of ICP versus f and extract Dit from the slope of the tted straight

line. Our attempt to do so is shown in Fig. 5.4, and a Dit = 7 1013 cm2 eV1 is obtained in our SG-NWFETs. Dit obtained for the SG-NWFET from 3T-CP is an order of magnitude higher than that estimated from the subthreshold swing. The relatively high Dit obtained

136 from 3T-CP may be attributed to the low frequency of measurement, which enables timely population/depopulation of oxide traps in the neighborhood of the SiO2 /Si interface. At low frequencies, near-interface slow oxide traps can also contribute to the total charge pumping current. In the past low frequency CCP has been employed to probe slow oxide traps close to the interface in short channel MOSFETs [173]. In low frequency charge pumping the relationship between
max ICP and frequency is no longer linear as suggested by Eq. (5.2). The depth into

the oxide measured from the interface over which oxide traps contribute to ICP is dependent on the frequency: this depth is larger the lower the measurement
max frequency. The total charge pumped Qmax = ICP /f at low frequency is related CP

to the frequency as given by

dQcp = qAg Nit (xm )e s . d log f

(5.3)

In Eq. (5.3), Nit is the trap concentration per unit volume of the SiO2 /Si interface and near interface SiO2 bulk at a maximum tunneling distance (xm ). e is the inverse attenuation factor for electrons in SiO2 and can be estimated using

e =

8m e e

(5.4)

In Eq. (5.4),

is the reduced Plancks constant, m is the eective tunneling mass, e

and e is the injection barrier for electrons from silicon into SiO2 and equals 3.1

137 eV. The maximum tunneling distance at any given frequency can be estimated using

xm

1 ln 2k0

1 n v n . 2f

(5.5)

In Equation (5.5), k0 is the decay constant and for a barrier of 3.1 eV the value of 1/2k0 is approximately 0.7 [174], n is the electron capture cross section, v is A the average thermal velocity and n is the carrier concentration [174, 175]. Using a free carrier concentration value of 1 1016 cm3 and assuming a uniform capture cross-section value of 1 1014 cm2 , the maximum tunneling distance for a pulse frequency of 1kHz is estimated to be about 0.76 nm. The total charge pumped in our SG-NWFETs as a function of the pulse frequency, f , on a semi-log scale is shown in Fig. 5.4. Applying Equations (5.3) and (5.4) to the Qmax versus ln f plot of Fig. 5.4, one gets Nit 6.9 1019 cm3 eV1 . CP Using the estimated tunneling distance of 0.76 nm, an average interface trap density of Dit 1.2 1013 cm2 eV1 is obtained. This value of Dit correlates very well with that obtained from the subthreshold swing measurements. The high Dit obtained in the SG-NWFETs may arise in part from the cylindrical oxide growth inherent to the geometry of the device [156]. As mentioned earlier, the high interface trap density in these devices may also be reduced using optimized post-oxidation annealing treatments [157, 171]. No such treatments were used for our devices since high interface trap density is desirable to detect the CP signal.

138

5.4

Conclusion

We have applied a modied three-terminal CP technique that we recently developed [167] to the study of the SiO2 /Si interface and neighboring oxide traps in a SG-NWFET structure. Frequency saturation of the CP signal is observed to occur in the SG-NWFET at higher measurement frequencies. At low measurement frequencies, however, near-interface slow oxide traps are observed to contribute to the measured 3T-CP signal. Analysis of our 3T-CP measurements have revealed a trap density of 1.2 1013 cm2 eV1 in the SG-NWFET, which is in agreement with trap density estimates made from subthreshold swing measurements [157]. This is the rst time that CP has been applied to NWFETs, and this study demonstrates the applicability of the technique to three terminal SG-NWFETs.

Chapter

Conclusions and Future Work

6.1

Contacts to WBG Semiconductors

The rst part of this thesis focuses on electrical characterization of Schottky contacts to WBG semiconductors. These semiconductors tend to contain more defects than silicon or even some of the mature III-V systems. Schottky contacts to WBG semiconductors, therefore, are far from ideal and show deviant behavior in their electrical characteristics. Also, the wide bandgap nature of these materials results in larger barrier heights compared to Si. Due to the larger barrier heights obtainable, minority carrier injection is more of a concern in these diodes. Space charge limited current-like behavior has been observed in Re/4H-SiC Schottky diodes. Using a combination of I-V , C-V and DLTS methods, the observed SCLC characteristics have been attributed to minority carrier injection as opposed to trap limited SCLC (reported in the literature).

140 Apart from minority carrier injection, the I-V characteristics can be heavily inuenced by the presence of barrier height inhomogeneities. An important goal of electrical characterization is the determination of the homogeneous barrier height. The homogeneous Schottky barrier height is a fundamental parameter that characterizes the metal/semiconductor system. An increasing amount of literature relies on analytical approaches based on the inhomogeneous Schottky barrier model to account for the observed deviations. In order to account for the eects of BHI on the extracted eective Schottky barrier height, an n-B plot is typically employed. The n-B plot provides a simple way to lter the eects of BHI. In order to use the I-V characteristics to determine the Schottky barrier height, knowledge of the Richardson constant is essential. However, an accurate approach to extract the Richardson constant in the presence of BHIs is still lacking. A key goal of this thesis has been to account for limitations of existing approaches to extract the Richardson constant. In light of these limitations, the need for a new method has been recognized. Based on the BHI framework provided by Tung, a linear correlation between the extracted barrier height and ln(A ) has been proposed. This linear correlation coupled with the widely used n-B plot has been used to extract the actual Richardson constant. The linear correlation is one of the key contributions of the current work. This method has been applied to the determination of the Richardson constant of emerging WBG semiconductors such as ZnO and GaN. The application of the method

141 to ZnO is of particular importance since the Richardson constant is not well established. An A value of 27 A cm2 K2 has been estimated using the proposed approach. This value is by far the closest reported to the theoretical value of ZnO of 32 A cm2 K2 . This method has also been applied to the determination of Richardson constant of GaN, and close agreement with the theoretically expected value has also been obtained.

6.2

Contacts to Nanowires

The second part of the thesis is focused on the Schottky contacts to nanowires. Electrical characteristics of a Schottky contact to a nanowire dier markedly from those of a bulk Schottky contact. The I-V characteristics of a Schottky contact to a nanowire are inuenced heavily by the adjacent nanowire surface. Depending on the surface charge magnitude and sign, the current conduction can vary. In order to systematically investigate the eects of surface condition on the I-V characteristics of an axial metal/nanowire contact, a surround gate architecture has been used. TCAD simulations have been used to gain insights into the eect of a surroundgate bias on the metal/semiconductor nanowire I-V characteristics. Based on these simulation studies, a method has been proposed to extract the true Schottky barrier height from the I-V characteristics. Under the inuence of surface charge, the depletion region width can vary radially and axially as well. The eective area for conduction is reduced in surface

142 depletion conditions, and under surface accumulation conditions, spatially nonuniform tunneling current localized along the nanowire periphery can contribute to the total current. The ideality factor and eective barrier height have been found to be surround-gate bias dependent. A linear correlation has been found between the ideality factor and eective barrier height obtained as a function of gate bias. The linear relation has been found to be valid in the case of surface accumulation conditions, and this straight line when extrapolated to n = 1 yields the homogeneous barrier height. The gate voltage required for the onset of surface accumulation can be determined by an n-Vgs plot. Using a combination of the n-B and the n-Vgs plots, the true Schottky barrier height can be determined. RT I-V measured on -Ni2 Si/n-Si NW Schottky contacts have also been analyzed and a linear correlation between n and B has been observed. The proposed method presents a simple way to analyze and interpret experimental I-V characteristics of Schottky contacts to nanowires. Given the signicant role played by the oxide/nanowire interface on conduction in the nanowire, it is important to control the interface quality. A modied version of the conventional charge pumping method known as the 3 terminal charge pumping method has also been applied to nanowire eld eect transistors for the rst time. 3T-CP method has been used to characterize the oxide/nanowire interface, and an interface trap density of 1012 cm2 eV1 has been determined. The charge pumping method can provide inputs such as interface trap density to the

143 TCAD simulation set up. Simulation and experimental methods presented in this work can together serve as a characterization toolset that can be used to further investigate contact and dielectric interfaces in semiconductor nanowire devices.

6.3

Future Work

The main focus of this thesis has been the development of analytical approaches that would allow determination of the true Schottky contact parameters. The inhomogeneous Schottky barrier model is gaining prominence, and analytical approaches based on the BHI framework are still not thoroughly investigated. For example, a strong and meaningful correlation between extracted BHI parameters and experimental data are still missing. Given the complexity of real MS contacts, a detailed study involving TCAD simulations and analytical approaches can provide more insight into the signicance of the extracted patch parameters. Correlation with samples that have been fabricated with the intentional incorporation of barrier height inhomogeneities would be the next step. At the nanoscale, the Schottky contact has evolved from a simple planar structure to a more complex creature with the eects of size and geometry becoming signicant. The methods provided in this thesis are a rst step in exploring dierent trends and unique features exhibited at the nanoscale. Size dependence of the Schottky barrier and its eect on Fermi-level pinning are just a few directions for continuing further investigations.

Appendix

Non-technical abstract
Metal contacts to semiconductors are ubiquitous in diverse electronic applications such as power diodes, light emitting diodes (LEDs) and gas sensors. For these applications, novel semiconductors such as silicon carbide, zinc oxide and gallium nitride have excellent potential and have gained a great deal of attention. Schottky contacts to these semiconductors can provide valuable inputs that can aid in improving material quality and thereby obtaining superior performance. This is often accomplished by interpretation of electrical characteristics such as current-voltage measurements. Extraction of Schottky barrier parameters is hampered due to the presence of material defects at the metal/semiconductor interface. For a large part, the rst of this thesis relies on the pioneering work done by Dr. Raymond Tung (then at AT & T Bell Labs) known as the inhomogeneous Schottky barrier model. This model has been largely successful in explaining the dierent trends exhibited by the current-voltage characteristics of real Schottky diodes. Parameter extrac-

145 tion based on the inhomogeneous Schottky barrier model is one of the key goals of this thesis. So far, methods presented in the literature have been found to be incomplete in the incorporation of the inhomogeneous Schottky barrier concepts. In this thesis, existing approaches to analyze current-voltage measurements are extended to provide a more thorough analysis. The analysis methodology presented here provides a means to accurately extract Schottky barrier parameters. On the other hand, contacts at extremely small dimensions (nanoscale) are being studied due to their relevance in nanoelectronics. Nanocontacts are important from both technological and fundamental perspectives. The behavior of these contacts is much dierent from that of macroscale contacts and hence electrical characterization of these contacts needs to be considered dierently. In this thesis, a method to analyze the current-voltage measurements of nanocontacts has been proposed based on simulations. Contact size and geometry eects are important in these nanocontacts. A simulation based approach allows a systematic exploration of these eects on the conduction properties of nanocontacts to nanowires. Due to substantially larger surface area/volume ratio in nanocontacts, the impact of surface on the conduction properties of nanocontacts to nanowires is also quite important. In the second part of this thesis, a method to address the eects of surface and geometry on the extracted parameters from current-voltage measurements is presented. The proposed approach would serve as a useful method to investigate Schottky barrier properties at the nanoscale.

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Vita
Karthik Sarpatwari 1594 S.Riverstone Ln, Apt. 301 Boise, ID 83706 karthik.sarpatwari@gmail.com 1-814-777-1157

Education
PhD, Engineering Science and Mechanics, The Pennsylvania State University

Dissertation advisors: Profs. O. O. Awadelkarim and S. E. Mohney

M.S, Engineering Science, The Pennsylvania State University B.Tech., Metallurgical Engineering, Indian Institute of Technology Madras

Research experience
Eects of barrier height inhomogeneities on Schottky barrier parameter extraction
Numerical and analytical approaches to extract true Schottky barrier parameters Experimental determination of Richardson constant of ZnO, GaN

TCAD simulation study of axial Schottky contacts to nanowire

Method to extract true Schottky barrier parameters from current-voltage characteristics of Schottky contacts to nanowires Eects of surface charge on nanowire conduction properties studied using 3D TCAD simulations

Publications
Extracting the Richardson constant: IrOx /n-ZnO Schottky diodes, K. Sarpatwari, O. O. Awadelkarim, M. W. Allen, S. M. Durbin and S. E. Mohney, Applied Physics Letters, 242110, Vol.94, No.24, 2009 Analysis of currentvoltagetemperature characteristics in SiC Schottky diodes using threshold-accepting simulated-annealing techniques, K. Sarpatwari, L. Passmore, S. A. Suliman and O. O. Awadelkarim, Solid State Electronics, Vol.51, Issue 5, 2007