Courses In Electrical Engineering

ENSET BAMBILI FIELD PROGRAMMABLE DEVICES AND APPLICATIONS

By Jean-Paul NGOUNE DIPET I (Electrotechnics), DIPET II (Electrotechnics) DEA (Electrical Engineering) Teacher in the Electrical Department, GTHS KUMBO, Cameroon.

FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

Chapter One
FIELD PROGRAMMABLE DEVICES: Technologies and Architectures
1.0 Specific objectives: At the end of this chapter, the student will be able to: Define Field Programmable Devices (FPDs) and give theirs specificities as compared to other high density devices used for Hardware designing; Know the evolution of the FPDs from the simplest one to the most recent ones and the improvement at each level of evolution; Master terminologies related to the field of FPDs; Know the basic architecture of each type of FPD; Compare different types of FPDs in terms of their performances; Know Companies manufacturing FPDs;

1.1 Introduction: A digital system can be defined as a combination of circuits intended to receive Boolean variables at their inputs and to output Boolean signals, according to the function they are realising. Since the beginning of the years 50 and the discovery of transistors, electronics has experienced a great evolution especially in the domain of signal processing and digital system designing. This evolution led to the creation of high density programmable devices such as Field programmable devices (FPDs) and microprocessors. In this chapter, technologies and architectures of various FPDs will be presented, and their performances compared.

1.2 Overview of programmable systems: The designing of digital systems can be achieved using non programmable standard integrated circuits (TTL and CMOS medium Scale Integrated circuits realising simple combinatory and sequential functions). However, for complex digital systems, the designing is achieved using Programmable Logic Devices (PLDs)

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Which are also called FPDs) microprocessors and microcontrollers. The following chart presents different types of IC used for digital system designing.

Digital Integrated Circuits

Standard logic circuits: 74LSXX 40XX

Microprocessors, microcontrollers

Field Programmable Devices: SPLD, CPLD, FPGA

Application Specific Integrated Circuits

Figure 1.1: Integrated circuits used for Digital Hardware Designing.

Remark 1.1: Definition of terminologies related to the field of Digital Integrated Circuits.

Field Programmable Devices (FPDs): It is a general term that refers to any type of integrated circuit used for implementing digital hardware, where the ship can be configured by the end user to realise different designs. Programming of such devices often involves placing the chip into a special programming unit, but some chips can also be configured in-system (SoC and SoPC: System on Chip and System on Programmable Chip).

PLA: Programmable Logic Array. It is a relatively small FPD that contains two levels of logic, an AND-plane and an OR-plane, where both levels are programmable.

PAL: Programmable Array Logic. It is a relatively small FPD that has a programmable AND-plane followed by a fixed OR-plane (non programmable). PAL is a trademark of Advanced Micro Devices Company (AMD).

SPLD: Simple Programmable Logic Device. It refers to any simple FPD, usually either PLA or PAL.

CPLD: Complex Programmable Logic Device. It consists of an arrangement of multiple SPLD-like blocks on a simple chip. Alternative names sometimes adopted for this type of chip are Enhanced PLD (EPLD), Super PAL, and Mega PAL.
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FPGA: Field Programmable Gate Array. It is a general structure that allows very high logic capacity. Whereas CPLDs feature logic resources with a wide number of inputs (AND-planes), FPGAs offer more narrow logic resources. FPGA also offer a higher ratio of flip-flops to logic resources than do CPLDs.

HCPLDs: High-capacity PLDs. It is a single acronym that refers to both CPLDs and FPGAs. This term has been coined in trade literature for providing an easy way to refer to both types of devices.

Interconnect: It is a term that is used to name the wiring resources of an FPD.

Programmable Switch: It is a user-programmable switch that can connect a logic element to an interconnect wire, or one interconnect wire to another (diode, transistor, fuse, antifuse).

Logic block: It is a relatively small circuit block that is replicated in an array in an FPD. When a circuit is implemented in an FPD, it is first decomposed into smaller sub-circuits that can each be mapped into logic block. The term is mostly used in the context of FPGAs, but it could also refer to a block of circuitry in a CPLD.

Logic capacity: It is the amount of digital logic that can be mapped into a single FPD. This is usually measured in units of equivalent number of gates in a traditional array. In other words, the capacity of an FPD is measured by the size of gate array that it is comparable to. In simpler terms, logic capacity can be thought of as number of 2-input NAND gates

Logic Density: It is the amount of logic per unit area in an FPD.

Speed performance: It measures the maximum operable speed of a circuit when implemented in an FPD. For combinational circuits, it is set by the longest delay through any path, and for sequential circuits it is the maximum clock frequency for which the circuit functions properly.

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Noise immunity: It is the degree of protection of a circuit against (electromagnetic) noise. Integration scale: Number of component (MOS or bipolar Transistors) integrated per surface unit of a chip. There are many integration scales: SSI: Small Scale Integration MSI: Medium Scale integration LSI: Large Scale integration VLSI: Very Large Scale Integration ULSI: Ultra Large Scale Integration

1.2.1 Standard Integrated logic circuits. The designer can interconnect many types of standard ICs (TTL, CMOS) in order to realise a digital system. The advantage of this method of designing is that it is easy to achieve because logic function are already available in ICs so as to be connected in order to realise a determined logic system. The main disadvantage is that standard ICs have a fixed configuration: they are designed by the manufacturer and cannot be modified by the end user. They also have a limited speed performance. 1.2.2 Microprocessors and microcontrollers. Microprocessors and microcontrollers have brought a great revolution in the domain of digital designing, because they permit the user to realise any digital function by programming. Information in microprocessors is treated in a sequential manner; that is, one information after another, like in Finite State Machines (FSM). The main disadvantage of microprocessor systems is that many processes cannot be carried out at the same time in them and the program controlling them should be permanently stored in a separated memory.

Instructions of a program stored in a memory

CPU

Figure 1.2: Principle of microprocessor systems.

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1.2.3 Field Programmable Devices. They offer the user the possibility to design a complex digital system in a single IC by programming. Some FPDs are reprogrammable. Unlike processor systems, FPDs systems work in a concurrent manner: many processes can be carried out at the same moment in the same FPD. On the other hand, once they are programmed, they can work alone, without the intervention of any external instructions controlling them, as it was the case for processor systems.

1.2.4 Application Specific Integrated circuits (ASICs). ASICs are integrated circuits designed for a specific purpose. They are not programmable. Once they have been designed, they can only achieve the function for which they have been made. ASICs are complex ICs that can contain processors, DSP (Digital Signal Processor) and many IP blocks (Intellectual Properties blocks: these are macrocells realising specific complex functions, they are intellectual properties of Companies).

1.3 Architecture of FPDs. FPDs are circuits into which a user can realise any digital function he want by programming, provided the number of I/O available on the IC is sufficient. We distinguish three main groups of FPDs: SPLDs, CPLDs and FPGAs.

1.3.1. PLAs and PALs (SPLDs). The first device developed specifically for implementing logic circuits was the Field Programmable Logic Array (FPLA), or simply PLA. A PLA consists of two levels of logic gates: a programmable wired AND-plane followed by a programmable wired OR-plane. Logically, a PLA is a circuit that allows implementing Boolean functions in sum-of-product form. The typical implementation consists of input buffers for all inputs, the programmable AND-matrix followed by the programmable OR-matrix, and output buffers. The input buffers provide both the original and the inverted values of each PLA input. The input lines run horizontally into the AND matrix, while the so called product term lines run vertically. Therefore, the size of the AND matrix is twice the number of inputs times the number of product terms.

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When PLA were introduced in the early 1970, by Philips, their main drawbacks were that they were expensive to manufacture and offered poor performances. Both disadvantages were due to the two levels of configurable logic, because programmable logic planes were difficult to manufacture and introduced significant propagation delays. To overcome these weaknesses, Programmable Array Logic (PAL) devices were developed. PALs provide only a single level of programmability, consisting of a programmable wired AND plane that feeds fixed OR-gates. PALs usually contain flipflops connected to the OR-gate outputs so that sequential circuits can be realised. PLAs and PALs are often referred to as Simple Programmable Logic Devices (SPLDs).

Inputs

Dense array of AND gates

Product terms

Dense array of OR gates

Outputs

Figure 1.3: General structure of PLAs and PALs

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F0

F1

F2

F3

Figure 1.4: PLA structure: A PLA consists of two levels of logic gates: a programmable wired AND-plane followed by a programmable wired OR-plane.

Figure 1.5: PAL structure: PALs provide only a single level of programmability, consisting of a programmable wired AND plane that feeds fixed OR-gates. A given column of the OR array has access only to a subset of the possible product terms.

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1.3.2. CPLDs CPLDs are made up of many PALs linked together by mean of interconnects in a single chip. This architecture permits higher speeds of functioning (hundreds of MHz). The larger size of a CPLD allows implementing either more logic equations or a more complicated design.

Figure 1.6: Structure of a CPLD: Each logic block contains many PALs

Some CPLD manufacturers are: Altera, Atmel, Lattice, Xilinx, Actel.

1.3.3. FPGAs. Basic structure of an FPGA includes logic elements, programmable interconnects and memory. Arrangement of these blocks is specific to a particular manufacturer. There are two main types of FPGAs: Reprogrammable FPGAs (SRAM based). Manufacturers are Xilinx, Altera, Lattice, Atmel. One-time Programmable FPGAs (OTP). They are antifuse technology based. Manufacturers are Actel, Quicklogic.

FPDs and applications_ENSET Bambili_Jean-Paul NGOUNE.

Figure 1.7: FPGA structure

1.4. Application: Digital designing using PLAs: Let us realise the following functions using a PLA device.
F0 F1 F2 F3 A B.C AC B.C BC AB AB A

Method:

1. Determination of the number of input, outputs and product terms of the system; 2. Determination of the format of PLA to be used; 3. Establishment of truth table of the system; 4. Realization of digital circuit;

Step one: Determination of the number of inputs, outputs and product terms: We have three input variables: A, B and C. The outputs are four: F1, F2, F3

and F4. The product terms are: A, BC, AC, AB, and BC. Each product term fits in one AND gate (6 input AND gate because we have three input variables with their inverse). Each output is that of an OR gate (5 inputs OR gates because we have five product terms).

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Step 2: Minimal format of PLA to be used. From the information above, the minimal format of PLA suitable for the

realization of the system is: 3x5x4. Where 3 is the number of inputs, 5 the number of product terms and 4 the number of outputs.

Step 3: truth table.

Product terms A A 1 1 1 -

Inputs B 0 1 0 C 0 0 1 F0 1 1 0 0 0

Outputs F1 0 0 1 1 0 Output : 1 = Term connect to output; 0 = No connection to output. F2 0 1 0 1 0 F3 1 0 0 0 1

B.C A.C
AB

B.C

Input: 1 = Asserted in term; 0 = Negated in terms; - = Does not participate.

Step 4: Realisation of the digital circuit.

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F0

F1

F2

F3

Figure 1.8: All possible connections are available before programming.

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AB /BC A /C /B /C A

F0

F1

F2

F3

Figure1.9: Programmed PLA: Unwanted connections are blown.

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Alternative representation for high fan-in structures:

Figure 1.10: Conventional representation of PLA connections.

Let us implement the following digital functions in the PLA whose structure is represented above.
F0 F1 AB A.B

C . D C .D

A B

C D

AB AB CD CD

F0

F1

Figure 1.11: Representation of digital functions on simplified PLA structure

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Exercise1.1: Consider the following Boolean functions:

F1 F2 F3 F4 F5 F6

ABC A B C ABC A B C A A B B C C

Realise these functions on a suitable PLA structure.

Solution: We should first write the Boolean expressions in terms of sum of products.
F1 F2 F3 F4 F5 ABC A B C ABC A AB AB B AB A B C A.B.C C AB AB.C ABC A.B.C A.B.C A.B.C C

A B C

AB C C AB ABC

AB . AB C

A B A BC AB F5 A.B C

A.B.C

ABC

A.B.C

A.B.C

F6

A AB AB

B AB

C C AB AB .C A.B.C ABC

AB .C

A B.A BC AB F6 A.B C

A.B.C

A.B.C A.B.C

A.B.C

A.B.C

A.BC

So, we have a total of 14 product terms, 3 inputs and 6 outputs. The suitable PLA structure will have the following format: 3x14x6.

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The truth table of the system can be given as follows: Product terms A A B C
A B

Inputs B 1 0 1 0 1 0 1 0 1 0 C 1 0 1 1 0 0 0 0 1 1 F1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 F2 1 1 1 0 0 0 0 0 0 0 0 0 0 0

Outputs F3 0 0 0 1 1 1 0 0 0 0 0 0 0 0 F4 0 0 0 0 0 0 0 0 0 0 0 1 0 0 F5 0 0 0 0 0 0 1 1 1 1 0 0 0 0 F6 0 0 0 0 0 0 0 0 0 0 1 1 1 1

1 0 1 0 0 1 1 0 0 1

C
ABC

A.B.C A.B.C A.B.C A.B.C A.B.C A.BC A.B.C

The logic diagram of the system can therefore be drawn as shown in the following page.

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ABC A B C A B C ABC ABC ABC ABC ABC ABC ABC

F1

F2

F3

F4 F5

F6

Figure 1.12: Logigram of the system using PLA.

1.5 Application: Digital designing using PALs. Digital designing using PALs is similar to designing using PLA. The only difference is that PALs have a fixed output OR-gate structure. Let us realise a 3-bit binary to Gray converter using a PAL.

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Truth table

Inputs A 0 0 0 0 1 1 1 1
S2 A BC

Outputs C 0 1 0 1 0 1 0 1 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 1 1 0 0 S0 0 1 1 0 0 1 1 0

B 0 0 1 1 0 0 1 1

Expressions of the outputs:

0 1

00 0 1

01 0 1

11 0 1

10 0 1

S2 = A

S1 A BC

0 1

00 0 1

01 0 1

11 1 0

10 1 0

S1

AB

AB

S0 A BC

0 1

00 0 0

01 1 1

11 0 0

10 1 1

S0

BC

BC

We have five product terms. We are going to realise this digital function using a 3X6X3 PAL with a fixed OR output structure (each output is connected to two AND gates) as presented below.

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AB'

A'B

B'C

BC'

S2

S1

S0

Figure 1.13: Realisation of a 3-bit binary-Gray converter using a PAL.

1.6 Comparative study of FPDs. There are many types of FPDs which are characterised according to the following criteria: The number of gates integrated; The nature of AND-plane structure (fixed or programmable); The nature of OR-plane structure (fixed or programmable); Their ability to be erasable or not.

The following table summarises the comparison between some FPDs.

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Table 1.1: Comparative study of FPDs Type PROM PLA PAL GAL EPLD FPLA Number of gates integrated 2000 to 500 000 10 to 100 10 to 100 10 to 100 100 to 3000 2000 to 3000 AND-Plane Fixed OR-Plane Programmable Erasable No No No Electrically U-V rays

Programmable Programmable Programmable Programmable Programmable Fixed Fixed Fixed

Programmable Programmable Electrically

Remark: Programmable Read Only Memories (PROMs). There are many types of PROMs: PROMs: They are programmed once, and cannot be erased. EPROMs or UVPROMs: They can be erased by an exposure to ultraviolet rays. EEPROMs: They can be erased many times (anytime) and reprogrammed. Flash: They have the same property with EEPROMs, with higher density of integration.

1.7 Conclusion. Technologies and architectures of FPDs have been presented. Digital designing using PLA and PAL has been introduced and discussed with many applications. A comparative study of FPDs has been carried out. The next chapter will be consecrated on the study of Finite State Machines (FSMs).

REVIEW QUESTIONS:
1. Define the following acronyms as they apply to digital logic circuits: ASIC PAL PLA CPLD

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FPGA.

2. Why would anyone use programmable logic devices (PAL, PLA, CPLD, FPGA, etc.) in place of traditional hard-wired logic such as NAND, NOR, AND and OR gates? Are they any applications where hard-wired logic would do a better job than a programmable device? 3. Some programmable logic devices (and PROM memory devices as well) use tiny fuses which are intentionally blown in specific patterns to represent the desired program. Programming a device by blowing tiny fuses inside of it carries certain advantages and disadvantages. Describe what some of these are. 4. Use one 4x8x4 PLA to implement the following functions. F1(w,x,y,z) = wxyz + wxyz + wxy F2(w,x,y,z) = wxy + xyz

5. Realise a 4-bit DCB Gray converter using a suitable PLA device. 6. How granularity of logic block influences the performance of an FPGA

References: 1. Stephen Brown, Jonathan Rose, Architecture of FPGAs and CPLDs: A Tutorial, Department of Electrical and Computer Engineering University of Toronto, Canada. 2. Field Programmable Gate Arrays and Applications, Version 2 EE IIT, Kharagpur University, India. 3. Shantanu Dutt, Introduction to CPLDs and FPGAs, ECE Department, University of Illinois at Chicago, USA. 4. Christian Gamom, Cours de circuits logiques architecture programmable et systmes, Dpartement du gnie lectrique, ENSET Douala, Cameroun. 5. J.P Ngoune, O. Vaiza, B. Bahoya, Etude et ralisation dun portail de parking pilot automatiquement par le CPLD EPM7128S ALTERA, Mmoire de fin dtude du premier cycle, ENSET Douala, 2007, Cameroun.

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ABOUT THE AUTHOR

NGOUNE Jean-Paul was born in Forek-Dschang, Republic of Cameroon in 1984. He is a holder of a Master Degree in electrical engineering, obtained in 2010 in the Doctorate School of the University of Douala. He is also a holder of a DIPET II and a DIPET I respectively obtained in 2009 and 2007 in the Advance Teaching School for Technical Education (ENSET de Douala). He is currently a permanent teacher of Electrical Engineering at the Government Technical High School of Kumbo, North-West region, Cameroon. His domain of research concerns the improvement of energy

conversion techniques for an efficient generation of electrical energy from renewable sources (especially wind and solar energy, small and medium scale hydropower) and digital designing using FPDs. The author is looking for a Ph.D program in his domain of research (he has not yet found it). Any suggestion for this issue will be warmly welcome.

NGOUNE Jean-Paul, P.O. Box: 102 NSO, Kumbo, Cameroon. Phone: (+237) 7506 2458. Email : jngoune@yahoo.fr Web site: www.scribd.com/jngoune

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