Current Sinks and Sources (CS)

[vezi CIA I, pp38-46, 67-75, 78-81]

A current sink/source is a two terminal component whose current is independent

of the voltage across its terminals.
The current flows from the positive node to the negative node.
A current sink typically has the negative node at VSS = VS. The source has the
positive node at VDD = VS+

Current sources and sinks are basic building blocks in IC design. Ideally, the output
impedance of a current sources/sink should be infinite in order to be able to generate or
draw a constant current over a wide range of voltages. However, finite values of Ro,
and a limited output swing required to keep devices in saturation will limit the
performance of CSs.
+
+ VS + I
V V I I ≠ f (V) ⇒ RL VL variable
- -
I
-
VS
Source Sink Ideal; R O → ∞ ; VL min = 0

Real

I IL I L =f(VL )
VL
RO RL VLmin ≠ 0
Ro ≠ ∞

The MOS implementation of a current sink. Basic output stage.

iout iout
IO
VG
vout 2LI D
Vmin=VDSsat = = v GS -VTh
KW
vGS
-
VS vout = vDS
vDSsat

KW 2
i out ≅ ( vGS -VTh ) (1 + λvout )
2L

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 KW 2
i out ≅ ( vGS -VTh ) Iout is set mainly by vGS, when vGS = ct , ⇒iout = ct
2L
From the above formula it follows that vmin across the current source can be made small
by using large W/L ratios and biasing the transistor at low current ID
1
rout =
λI D
Typically rout is of the order of hundreds of kΩs. In many applications such an output
resistance is too small.
Conditions for keeping the devices in saturation.
nMOS
vD
vG
vDS > vGS – VTh => vD > vG – VTh (1)
vS

pMOS

vS
vG vDS > vGS – |VThp|=> vD < vG + |VThp| (2)
vD

Example:
VO max
|VThp|

|VThp| VGp
V1
V1
VD - Dn max

vo
V2
V2 VGn
VThn
VThn

VO min

The advantage of the current sink and source realized by a single transistor is their
simplicity. For certain applications the performance may need to be improved. One
improvement is to increase the small – signal output resistance resulting in a more
constant current over the range of vout values. The second improvement is to reduce the
value of vomin thus resulting in a larger range of vout over which the CS works properly.

20
MOS CSs are widely used in analog circuits both as active load elements for amplifier
stages and as biasing devices.
VOmin can be small by using large W/L ratios, biasing Ts at low current or using other
architecture (vomin ~vDSsat ~ iD / (W/L)).
Output resistance can be increased by cascoding current sources or by introducing a
negative feedback.

Current Mirrors (CM)

A CM is a current controlled CS → CCCS. CMs are based on matched devices. The
matching principle is much like looking into a mirror, therefore the circuits are called
CMs.
Simple MOS current mirror.
+
VS
ID1=IREF KW1
R
I D1 = (vGS -VTh ) 2 (1+λv DS1 ) (3)
2L1
ID2=Iout
W1 KW2
1 2 W2 I D2 = (vGS -VTh ) 2 (1+λv DS2 ) (4)
L1 L2 2L 2
-
VS

Since vGS1 = vGS2 , ideally the same current, or a multiple of the current in T1 flows
through T2. We assume T2 is in saturation. T1 is saturated because

vD1 = vG1 ⇒ vD1 > vG1- VTh.

The ratio of the drain currents is given by

I D1 w L 1+λvGS1
! = 1 1⋅ (5)
I D2 w 2 L 2 1+λv DS2

The reference current ID1 is determined by solving the system of equations.

Kw1
! I D1 = (VS+ -vGS -VS- ) R = (vGS -VTh ) 2 (6)
2L1

21
The minimum voltage across the current sink is set by requirement that M2 remains in
saturation, that is
! vout min = VDS sat = vGS – VTh (6’)

Current I2 should be independent of vDS2 :

I D2 w L
! = 2 2 (7)
I D1 w1 L1

The variables w2, L2, w1, L1 and vGS (rel. 6 and 7) are available to the designer to set
currents. Where designing CMOSCMs, the values for vGS and L1 = L2 = L are selected
before solving for W to get the desired current.
For analog design it is extremely important to keep the output resistance

1 1
ro = ; λ≅ (8)
λI D2 LVE

as high as possible.
By increasing the channel length of the devices, setting L to two to five times the
minimum drawn gate length, the effects of channel length modulation (parameter λ) is
reduced : ro increases and influence of vDS2 decreases, because λ decreases (rel 8 and 5)
• If vGS is set close to VTh very large devices result (vDS sat is very small)
• If vGS >> VTh transistors enter in the linear region too early (vDS sat is very large)
An acceptable difference vGS - VTh is several hundreds of milivolts.
vGS ≅ 1.2V ; vGS ≅ 0.8V
These rules of chosing vGS and L1 = L2 = L are starting points in the design. They allow
the designer to concentrate on two variable (W2 and W1) in the basic CM rather than five
(see rel. 6 and 7).

22
 Improving the output resistance of a current source
The small signal output resistance of a current source can be increased by negative
feedback. Usually a source resistance is introduced. The principle is shown in the

iL
following figure.

1
VG = ctv
GS
VG is constant. We expect iL = ct. If iL increases iLRS also increases
RS
and reduces vGS that controls iL. This one goes toward the initial
iLRS
value.

We can calculate the output resistance by modelling the above circuit at low frequency
and passivisating the input signal. An output measure voltage source is introduced
vx
Ro =
ix

iX
v X + vgs vX iX R S
ro vX i X = g m v gs + i X = - g m R Si X + -
ro ro ro
gmvg ⇒
g v gs RS
iX = - g m R S >>
vgs RS ro
RS
i X ro (1+g m R S ) = v X
⇒
R o = ro (1+g m R S )
gmRS – the magnitude of the feedback loop gain.
The above principle is also implemented by using in the place of a passive resistance an
active one.
Active resistances
• Transistors in saturation play the role of large small signal active resistances wenn
connecting it as a current source or of small resistances or vGS voltage reference
when operating in “gate-drain” connections.

23
 iD small go Current source connection
saturation saturation region:
 ro

large go
VDS > vGS – VTh
voltage controlled R vGS = ct 1
g o = λI D ; ro =
VDS g d id λI D
vGS = ct ⇒ Transistor acts as a resistor:
ro v
vgs = 0 (no variations) i d = ds ; R ech = ro
vgs = 0 gmvgs = 0 ro
vds
s

The “gate – source” connection

g d id vGS = vDS > vDS -VTh ⇒saturation region
R1 ro v ds
i d = g m v ds +
gmvgs ro
vGS
s i d ≅ g m v ds
1
⇒ Rech = is a small resistance
gm
Increasing the output resistance of a current source.

Ro
 a) The cascode connection boosts the output resistance

IREF IL
IL = ? ; Ro = ? ; vomin = ?
3 4 a) IL = ?
V1
the basic CM is T1 – T2 . These transistors have the same areas and
vGS, so that
V2
1 2 ID1 = ID2 -> IL = IREF
vGS

b) Ro = ?
IREF – ct ; V2 = ct ; T2 acts as an active resistance connected in the source of T4.
Ro ≅ ro 4 (1 + g m 4 ro 2 ) ~ g m ro2
This Ro is much larger than the output resistance ro of a basic current mirror.

24
c) vomin =?
vo = vD4
vD4min = v1min – VTh = 2 vGS – VTh = 2 vDSsat + VTh
The minimum voltage across the cascode is significant larger than the minimum voltage
across the basic CM (vDSsat).

Ro
 b) The Wilson mirror
The negative feedback increases Rout and stabilizes IL

VS+ I REF = ?

IREF IL IL = ?
4 Ro = ?
VB a 3
vout min = ?
b
1 2 Kpw4
I REF = (VS+ -VB - VThp ) 2
2L 4
W1 W2
I L = I REF if =
L1 L 2
iX Ro = ?

vX
Low frequency small signal model
ro4 ro3
M4 is a current source because vGS4 = ct
vab gm3vab
a M2 is connected as a 1/gm resistance
b
ro1 W1 W2 W3
vgs1
IREF = IL and = =
1/gm2 L1 L 2 L3
gm1vgs1
2KW
⇒ gm = I D is the same for T1, T2, T3
L

v x -v gs1
i x = g m3 vab +
ro3
ix
vgs1 =
g m2
vab = v a -v b = -g m1vgs1ro1||ro2 -vgs1

25
 ix v i
i x =-g m (g m vgs1ro1||ro2 )- g m v gs1 + x - x
gm
 ro3 g m ro3
ix

1 v
i x (2+g m ro1||ro2 + )= x
g m ro3 ro3
vx 1 g r
Ro = ro3 (2+g m ro1||ro2 + ) ≅ ro3 (2+ m o )@ g m ro2 2
ix g m ro3 2
Comparison of Rout of CMs
basic cell cascode CM wilson CM
ro ~gmro2 ~gm ro2/2

The minimum voltage required to keep the output current constant is

V3
3 v out min =V3 -VTh3 =
2vGS vGS = vGS2 +vGS3 -VTh3 =
1 2
2I L 2I L
=2 +VTh3 + +VTh2 -VTh3 =
basic CM β3 β2

KnW 2I L
β= =2 +VTh3 = 2v DSsat +VTh
L β
VTh2 ≅ VTh3 =VTh
β 2 =β 3

The minimum voltage across the CM is much larger than for the basic CM (vDSsat).

Ro
 c) Other configuration of CM - other type of Wilson CM.

IREF Iout
vout
Iout if W1/L1 = W2/L2
3 4
V4 Rout ≅ g m ro2 / 2
vGS vGS vo min = V4 − VTh 4 = 2vGS − VTh = 2v DSsat − VTh

1 2

The basic CM has both vDS1 and vDS2 equal to vGS so the mirror factor

26
 Iout W2 L 2 1+λv DS2 W2 L 2
k= = = ≠ f(v DS )
I ref W1 L1 1+λv DS1 W1 L1
is independent of output voltage, so the stability of IL is very good.

Ro
 d) Regulated cascodes
The cascoding effect of the output transistor in a cascode CM can be increased adding an
additional gain stage.

IL IL
R O ≅ ag m rO2 R O ≅ g m rO2
V2
+ 2 KW
a 2
- IL = (V1 -VGS ) 2
2L

1 1
V1

regulated cascode simple cascode

The output impedance is increasing to a higher degree than the Wilson CM.
vDS1 is kept constant and if a >>1, vDS1 = V2
KW
⇒ IL = (V1 -VGS ) 2 ≠ f(v out )
2L
• Calculate Ro
+
ix

a (v +-v -) vgs vx
ro2
-
gm2 vgs

ix
v--v+
ro1

v x + (v + -v - )
i x = g m2 v gs +
ro2
v+ - v-
ix = -
ro1
v gs = a (v + -v - )+v + -v - =(a+1)(v + -v - )

27
 vx r
i x = -g m2 (a+1)ro1i x + -i x o1
ro2 ro2
 r 
v x = i x ro2 1+ o1 + g m2 ro1 (a+1) 
 ro2 
v
R o = x ≅ ro2 ⋅ g m2 ro1 (a+1) = (a+1)g m ro2
ix
e) The amplifier can be a single input single output device:

IL
Iout
4
V 2 -a 2

3 vi
1 1
V1 V1

M34 – an inverting amplifier

ro4 I4 vo
= − g m ro 3 || ro 4 = − a
vi
vi

vi 3

The small signal model of the regulated cascade with an inverting amplifier:

g d iX

ro2 vX

-avi
gm vgs
s
iX
ro1
vds1= vi

28
 v x - vi
i x = g m vgs +
ro2
vi = i x ro1
v gs = - avi -vi = − ( a +1) v ι ≅ -avi ; if a  1
 
v v  r  v
i x = - ag m vi + x - i = -  g m aro1 + o1  i x + x
ro2 ro2  ro2  ro2
 
 neglectible 
ro2i X = - g m aro1ro2i X + v X
vX
Ro = = r02 (1+g m ro1a) ≅ g m ro2 a
iX

for a  gmro/2 Typical values : gm= 20µA/V ; Ro  g m2 ro3 /2 ro=10MΩ ⇒ Ro ≅ 400 GΩ

Biasing the cascode for lower minimum voltage across CS

vo a) Calculate vo min across the following CM:

I6 Ro ≅ ro4gm4ro2
IREF IL IL = IREF (CM 1-2)
1W vomin = ?
4 L
3 6 W/6
4 vomin = V4 – VTh4
W
V4
L
W 5 vo
1 2
L W W
L L

KW KW
I REF = (vGS3 -VTh3 ) 2 = (v GS1 -VTh1 ) 2
2 ⋅ 4L 2L

⇒ v DSsat3 = 4v DSsat1 v DSsat = vGS -VTh

⇒ v DSsat3 = 2v DSsat1 = v DSsat ( If w 3 L3 =1 4 W L )

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 V4 = v GS1 + v GS3 -v GS6 = v DSsat1 + VTh1 + v DSsat3 +VTh3 v DSsat1 +VTh6
≅ v DSsat + 2v DSsat -v DSsat + VTh

If the body effects are neglected (VTh1 ≅ VTh3 ≅ VTh6)

⇒ voutmin = 2vDSsat +VTh-VTh

voutmin = 2vDSsat
2I L 2LI L
A voltage of 2v DSsat = 2 =2 is across both M2 and M3 giving lowest value of
β LW
Vmin and still keeping both Ts in saturation. Using this approach and increasing the W/L
ratios will result in minimum values of Vmin .

vo b) Calculate vomin across the following CM

Iout = ?
Ro = ? IR IR
Vomin = ? Iout = IR
Voutmin = V4 – VTh
V4 = VGS5
4
5 3 W/L

1 2 W/L

basic CM

KW KW
IR = (v GS5 -VTh ) 2 = (v GS1 -VTh ) 2
4 ⋅ 2L 2L
⇒ v GS5 - VTh = 2(v GS1 - VTh )
⇒ v GS5 = 2v GS1 -VTh
v out min = 2v GS -2VTh = 2v DSsat

30