Data Transfer Croup: The data transfer instructions move data between registers or between memory and registers.

MOV MVI LDA STA LHLD SHLD Move Move Immediate Load Accumulator Directly from Memory Store Accumulator Directly in Memory Load H & L Registers Directly from Memory Store H & L Registers Directly in Memory

An 'X' in the name of a data transfer instruction implies that it deals with a register pair (16-bits); LXI LDAX STAX XCHG XTHL Load Register Pair with Immediate data Load Accumulator from Address in Register Pair Store Accumulator in Address in Register Pair Exchange H & L with D & E Exchange Top of Stack with H & L

Arithmetic Group: The arithmetic instructions add, subtract, increment, or decrement data in registers or memory. ADD Add to Accumulator ADI Add Immediate Data to Accumulator ADC Add to Accumulator Using Carry Flag ACI Add Immediate data to Accumulator Using Carry SUB Subtract from Accumulator SUI Subtract Immediate Data from Accumulator SBB Subtract from Accumulator Using Borrow (Carry) Flag Subtract Immediate from Accumulator Using Borrow (Carry) Flag INR Increment Specified Byte by One DCR Decrement Specified Byte by One INX Increment Register Pair by One DCX Decrement Register Pair by One DAD Double Register Add; Add Content of Register Pair to H & L Register Pair Logical Group: This group performs logical (Boolean) operations on data in registers and memory and on condition flags. The logical AND, OR, and Exclusive OR instructions enable you to set specific bits in the accumulator ON or OFF. ANA ANI ORA OR XRA XRI Logical AND with Accumulator Logical AND with Accumulator Using Immediate Data Logical OR with Accumulator Logical OR with Accumulator Using Immediate Data Exclusive Logical OR with Accumulator Exclusive OR Using Immediate Data

The Compare instructions compare the content of an 8-bit value with the contents of the accumulator;

CMP CPI

Compare Compare Using Immediate Data

The rotate instructions shift the contents of the accumulator one bit position to the left or right: RLC RRC RAL RAR Rotate Accumulator Left Rotate Accumulator Right Rotate Left Through Carry Rotate Right Through Carry

Complement and carry flag instructions: CMA CMC STC Complement Accumulator Complement Carry Flag Set Carry Flag

Branch Group: The branching instructions alter normal sequential program flow, either unconditionally or conditionally. The unconditional branching instructions are as follows: JMP CALL RET Jump Call Return

Conditional branching instructions examine the status of one of four condition flags to determine whether the specified branch is to be executed. The conditions that may be specified are as follows: NZ Z NC C PO PE P M Not Zero (Z = Zero (Z = 1) No Carry (C = Carry (C = 1) Parity Odd (P Parity Even (P Plus (S = 0) Minus (S = 1) 0) 0) = 0) = 1)

Thus, the conditional branching instructions are specified as follows: Jumps C INC JZ JNZ JP JM JPE JP0 Calls CC CNC CZ CNZ CP CM CPE CPO Returns RC RNC RZ RNZ RP RM RPE RPO

(Carry) (No Carry) (Zero) (Not Zero) (Plus) (Minus) (Parity Even) (Parity Odd)

Two other instructions can affect a branch by replacing the contents or the program counter: PCHL Move H & L to Program Counter

RST

Special Restart Instruction Used with Interrupts

Stack I/O, and Machine Control Instructions: The following instructions affect the Stack and/or Stack Pointer: PUSH Push Two bytes of Data onto the Stack POP Pop Two Bytes of Data off the Stack XTHL Exchange Top of Stack with H & L SPHL Move content of H & L to Stack Pointer The I/0 instructions are as follows: IN OUT Initiate Input Operation Initiate Output Operation

The Machine Control instructions are as follows: EI Enable Interrupt System DI Disable Interrupt System HLT Halt NOP No Operation

Processor 8085 Registers Table 2 shows the 8085 microprocessor internal registers that the programmer has access to. Registers are temporary memories that can be accessed with some of the instructions. each are 8 bits long and two are combined to form 16 bit binary numbers like registers B and C. Stack pointer register SP as low order byte in SPL and most significant byte in SPH. Value in SP points to current top of stack memory. Table2: Microprocesor 8085 Registers 7 0 7 0 B C D E H L SPH SPL PCH (program counter) PCL 15 A increment/decrement register 0

Assembly Language Format The 8085 instruction consists of a label label2, followed by the mnemonics, then the distination operand and the source operand if present on a single line like this: label2: MOV A,(HL) ; Code explanantions and comments. where label label2 to is made equivalent to the location of the first byte of the instruction by the assembler. The word "MOV" is the mnemonics, character "A" is the distination instruction operand in this case. The (HL) is the source instruction operand in this case and means that the contents of registers H,L points to a memory location. The characters to the right of character ";" to end of line "\n" are code explanations and are not compiled by the assembler. Mnemonics Reprentation Conventions r, r1, r2 One of the registers A, B, C, D, E ,H, L (, ) round brackets means register(s) in these contains a pointer value to a main memory location, DDD three bits in opcode representing destination register in table 4, SSS three bits in opcode representing source register in table 4, M a 16 bit pointer value to a main memory location, d8 data as a 1 byte operand immediately following the opcode, d16 data as a 2 byte operand immediately following the opcode, low order data byte first; low order byte d16l of d16, most signifcant byte d16h of d16; word d16 is two bytes. rp Two bits in opcode representing the use a register pair in table 5; register pair instruction operand: BC, DE, HL or SP. PC 16 bit progam counter register, with PCL low order byte of PC and PCH the most significant byte of PC. SP 16 bit stack pointer register which points to start location of stack in main memeory, SPL is low order byte of SP, SPH is most signifcant byte of SP. port an eight bit number as port number that follows the opcode byte in main memory and is from address pins A0 through A7 used by "IN", or "OUT" instruction. . Tables 4 and 5 shows bits that needs be included in some opcodes depending on the register(s) used in

instruction. For example if register B is used in instruction "MOV B,(HL)", its opcode will be: 01DDD110=01000110. Table 4: Register Bits DDD or SSS bits: 111 000 001 010 011 100 101

register names: A B C D E H L

Table 5: Register Pairs For Opcode rp bits: register pairs (rh, rl): 00 B, C 01 D, E 10 H, L 11 S, P.

Intruction Set Encyclopedea Intruction set encyclopedea for each intruction below has instruction syntax (mnemonics) format, basic operation, code explanations and comments, operation function, machine code or opcode of corresponding instruction in binary format with optional immediate operands, addressign types, flags affected, other information and then perhaps an example instruction. The 8085 microprocessor has ff16 assembly instructions that have opcodes that are eight bits long. Some opcodes have an immediate byte or two immediately following it in main memory. Indirect addressing means that a value in one of the register pairs (b-c, d-e, h-l or sp) contains a value that points to a main memory location of a byte. Direct addressing means the immediate operands (2 bytes) following the opcode points to a location in main memory of a byte.

Data Transfer Mnemonics MOV r1,r2 (move value between registers). The content of source register r2 is moved or copied to destination register r1: r1 r2. Opcode: 11DDDSSS2 . Addressing type(s): register r; flags affected: none. Example: MOV A,B.

MOV r,M (move byte from main memory to a register). The byte contents of main memory location whose address is in index registers H and L is moved to

register r: M= (HL). r (HL). 01DDD110. Addressing: register r, indirect M; flags affected: none. Example: MOV B,(HL).

MOV M,r (move byte from a register to a memory location) The contents of register r is moved or copied to the memory location whose address in in registers H, and L; register L contains to the lower byte of location M and H the most significant byte of M: (HL) r. 01110SSS. Example: MOV (HL),C.

MVI r,d8 (move immediate byte to register e) The content d8 of immediate operand byte of the instruction into register r: r d8. Opcode and operand: 00DDD1102, d816 . Example: MVI D,02h.

MVI M,d8 (move immediate byte to a memory location) The content d8 of immediate byte operand of the instruction is moved or copied the main memory whose address is in registers H and L. (HL) d8. 00110110, d8 Example: MOV (HL),03h.

LXI rp,d16 (load register pair rp with immediate word d16) Most significant byte d16h of data of d16 is moved to most significant register rh of register pair rp and low order byte d16l of d16 is moved to low order register rl of register pair rp: rh d16h, rl d16l. 00rp0001, d16l, d16h Example:LXI HL,025dh.

LDA A,(d16) (load accummulator A direct) The content of the memory location pointed to by immediate operand value d16 is moved to register A. A (d16). 00111010, d16l, d16h. Example: LDA A,(0255h)

STA (d16) (Store from accummulator direct) The content of accumulator A is stored in main memory location whose address is d16 (immediate word). Low order byte is d16l. 00110010, d16l, d16h.

STA (041ch)

LHL (d16) (load H and L register direct) The content of two adjacent memory locations whose starting address is immediate operand d16 is loaded into register paint H and L, with lower order byte in L and most signficant bye following is stored into register H. L (d16), H (d16+1). 00101010, d16l, d16h. LHL (02a7h)

SHLD (d16) (store H and L direct) Store H and L values into memory location beginning at location d16. Lower byte in L into main memory location d16, and most significant byte in H into location d16+1 (following L). (d16) L, (d16+1) H. 00100010. d16l, d16h. SHLD (030fh).

Arithmetic Mnemonics ADC r (add register r to A with carry) The content of register r and contents of current carry bit C are added to content of accmumulator A=An with results in acccumulator A=An+1 .ResetscarryflagtoC=1=Cn+1 bit if carry bit is present. Example value An+1=100011012. An+1 An+r+Cn, Cn+1. 10001SSS. ADC B.

ADC M (Add a memory location content with carry) The byte content of the memory location whose address is contained in register pair H and L and the current carry flag C bit are added to the accumulator A value with result in accumulator A. An+1 An+(HL)+Cn, Cn+1. Opcode: 10001110. Example: ADC (HL).

ACI d8 (add immediate operand with carry) The content of the second byte (immedate operand) d8 of instruction, the current carry bit Cn and contents of accumulator A are added. Results in accumulator A=An+1. An+1 An+d8+Cn, Cn+1. 11001110, d8. Example: ACI 04h.

Processor Input, Output IN port (processor byte input) The byte data is placed on the eight bit bi-drectional data bits (bits D0 through D7) by another circuit (8155))

by the specified port is moved to register A. Pin IO/~M goes bit 1, and address pins A7 through A0 contains the port number. A (data). 11011011, port. Addressing: direct; flags: none. Rxample: IN 82.

OUT port (Byte output from processor) The contents of register A is placed on the eight bit bi-directional data bus (D0 through D7) for transmission the specified port. During data transmission (on the eight bit bi-directional data bus) pin IO/~M goes bit 1 and ~Wr pin goes to bit 0. The IO/~M pin goes bit 1, and port number byte is address value in pins A7 through A0, and then repeated at the most significant byte of address word at pins A8 through A15. (data) A. 11010011, port. Addressing type: direct; flags affected: none. address A: 8155 names: 76543210 x x x x x 0 0 0 command status register x x x x x 0 0 1 port A x x x x x 0 1 0 port B x x x x x 0 1 1 port C. The x means does not care, can be bit 1 or 0. Example: OUT 80.

HLT (halt procesor) The proceesor is stopped. Switch "reset in" pin to restart processor. 01110110.

NOP (no operation) No operation, proceed to next intruction in main memory. Program counter register PC value is incremented by 1. Registers and flags are unaffected. Opcode: 000000002 . Example: NOP.

RIM (read interrupt mask) The RIM intruction loads data into the accumulator relating to interrupts and serial data input. Opcode: 00100000.