A New BIST Architecture for Word Oriented Memory

Il-Woong Kim School of Electrical and Electronic Engineering Yonsei University, Seoul, korea woong@soc.yonsei.ac.kr Gunbae Kim School of Electrical and Electronic Engineering Yonsei University, Seoul, korea kgb9572@soc.yonsei.ac.kr Ilgweon Kang School of Electrical and Electronic Engineering Yonsei University, Seoul, korea neokings@soc.yonsei.ac.kr Sungho Kang School of Electrical and Electronic Engineering Yonsei University, Seoul, korea. shkang@yonsei.ac.kr

Abstract Systems-on-Chip(SoC)s are now moving from logic dominant to memory dominant chips in order to satisfy high functionality and short development cycle. This means that the yield of memory part is the most important factor for the entire chip yield. In this paper, two word-oriented memory test algorithms are proposed newly. The one is an efficient writing NPSF test algorithm and the other is an efficient disturb test algorithm. Finally, we describe an BIST architecture for word-oriented embedded memory that detects basic FFMs, DFs, NPSFs, and disturb faults. Keywords: Embedded Memory, NPSF Test, Disturb Test, BIST

memory. Furthermore, disturb faults are also being regarded important. This paper describes an efficient BIST architecture for the word-oriented embedded memories that detect basic FFMs, DFs, NPSFs, and disturb faults. March Calgorithm is used to detect basic FFMs and March AB1 algorithm is used to detect the single-cell 2-operation dynamic faults. In this paper, two algorithms are proposed. The one is an efficient writing NPSF algorithm and the other is an efficient disturb test algorithm. Finally, a new word-oriented memory BIST architecture which supports above test algorithms is presented.

Introduction

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2.1

Supporting Algorithms
March based algorithms

Systems-on-Chip(SoC)s are now moving from logic dominant to memory dominant chips in order to satisfy high functionality and short development cycle. According to the ITRS 2005, the memory part grows faster than the logic part in SoC (logic part 15%/year, total 26%/year.). Therefore, the embedded memory becomes the largest and essential part of SoC. This means that the yield of memory part is the most important factor for the entire chip yield. For this reason, the development for the advanced memory test strategy is being required. As direct controllability and observability of the embedded memory cores are low, most of the embedded memories are tested through dedicated self-test circuits. This self-test circuit is called as memory Built-In-SelfTest(BIST). Traditionally, memory BIST architectures are optimized to support March algorithms that detect basic functional fault model(FFM)s such as address decoder fault(ADF)s, stuck-at fault(SAF)s, transition fault(TF)s, and coupling fault(CF)s [1]. These March algorithms are generally composed of simple and symmetric memory operations, so that a memory BIST can be implemented efficiently. However, as the density of embedded memory is increased, faults of embedded memory are complicated and complex fault models such that dynamic fault(DF)s and neighborhood pattern sensitive fault(NPSF)s are now being regarded as important fault models of embedded

In memory testing, ADF, SAF, TF, and CF are typical FFMs detected through March algorithms. They are characterized by being sensitized by the execution of just a single memory operation. These faults are called as static faults. However, new faulty behaviors occur in latest technologies [2], [3]. For an example, a write operation on a memory cell, immediately followed by a read operation, may cause the cell to flip. This behavior cannot be modeled as static faults since they require more than one operation to be sensitized, and are referred to as dynamic faults. Although dynamic faults are sensitized by more complex operations than static faults, both static and dynamic faults can be detected by March based algorithms. The proposed BIST uses March C- algorithm for static faults [1] and March AB1 algorithm for dynamic faults [4]. March C- algorithm is frequently adopted in MBIST since it has reasonable test length and test coverage. The cardinality of the dynamic fault set is infinite and the number of possible operations is not limited. Therefore, single cell 2-operation DFS are only considered in this paper. March AB1 algorithm is selected since it has reasonable test length and test coverage. The March sequence and fault coverage of these algorithms are presented in Table 1.

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Table 1. Supporting March algorithms

Algorithm March CMarch Sequence { (w0); (r0,w1); (r1,w0); (r0,w1); (r1,w0); (r0);} { (w0); (w1,r1,w1,r1,r1); (w0,r0,w0,r0,r0)} Fault Coverage ADF, SAF, TF, unlinked CFid dRDF, dDRDF, dIRF

data to be written. If we write the word into the memory block using the 1st step scheme, one write operation sensitizes four tiling neighborhoods and five write operations sensitize twenty tiling neighborhoods.

March AB1

2.2

A NPSF test algorithm

Depending on the definition of the neighborhood cells, two types of neighborhoods are defined. The one is type-1 for a five-cell neighborhood and the other is type-2 for a nine-cell neighborhood [1]. The victim cell is called as the base cell(denoted as B) and all the aggressor cells form together the deleted neighborhood, which includes the N, E, W, S, NW, NE, SW, and SE cells that are adjacent to B. The base cell and the deleted neighborhood cells are called as the neighborhood cells. In this paper, only the type-1 tiling neighborhood is considered, because type-1 has a reasonable number of NPSF pattern for the high density memories.

Figure 2. Proposed pattern writing scheme In the 2nd step, the column addresses at 1st step are increased by one. The same method is repeated in 3rd, 4th, and 5th steps for the previous steps. Table 2. Sensitizing performance of proposed method
Write Step 1st Sensitized *TN Number / One Write Operation 4bit-word 4 3 2 2 3 2.8 8bit-word 6 5 5 6 4 5.2 16bit-word 10 10 10 10 10 10

Figure 1. Type-1 and Type 2 neighborhood NPSF can be classified into active NPSF, passive NPSF and static NPSF corresponding to the characteristics between base cell and deleted neighborhood cell. To detect all faults for one neighborhood, 128 patterns are required for active NPSF, 32 for passive NPSF and 32 for static NPSF, respectively [1]. Multi-background March algorithms have been developed to detect NPSFs [5], [6]. However, such algorithms require the too much long test time (i.e., almost 100n memory operations for the full fault coverage, where n is the size of the address space). And an Euler sequence generator was developed to generate NPSF patterns [7]. However, it has the long test time too and high H/W overhead itself. Thus, NPSFs have been considered as complex faults that are hard to test. Therefore, we propose a efficient writing NPSF pattern generation algorithm for type-1 tiling group and word-oriented memories. In the proposed algorithm, a limited set of patterns will be used by default. Figure 2 describes memory blocks which shows type-1 tiling neighborhoods. The colored squares indicate transited cells to sensitize NPSFs. We can write patterns into a memory block using the shown method with the five-step sequence in a 4bit-word system. Let assume that all memory cells are initialized by 0 and 1111 is the word

2nd 3rd 4th 5th Average

(* TN : Tiling Neighborhood) Table 2 presents the number of tiling neighborhoods sensitized by one write operation for the 4, 8, and 16 bitword oriented memories. Using a 5bit-Euler sequence generator [7], the average values of tiling neighborhoods sensitized by one write operation are 0.8, 1.6, and 3.2 for the 4, 8, and 16 bit-word memories, respectively. Using the proposed method, average values of tiling neighborhoods sensitized by one operation are 2.8, 5.2, and 10 for the 4, 8, and 16 bit-word memories, respectively. Therefore, the propose method can generate NPSF patterns more effectively than the previous method for the word-oriented memories. Tiling neighborhoods sensitized in 1st step can be classified into four types according to transited cells (i.e. TN1 : N is transited, TN2 : E is transited, TN3 : W is transited, and TN4 : S is transited). When all memory cells are initialized by 0, NPSF patterns generated by the five-step sequence with 1111 word are presented in Table 3. After this write sequence, all memory cells are filled with 1.

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Table 3. TN patterns (Background:0s, Word-Data:1111)

TN1 TN2 TN3 TN4 Write step B N E W S B N E W S B N E W S B N E W S Init 1st 2nd 3rd 4th 5th
0 0 1 1 1 1 0 1 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 1

If March tests have been done, we can use the initiated background in NPSF test. If so, test length can be saved by 2n. The test coverage using single background is presented in Table 5. However, If the high test coverage is needed, we can use multi-background, and complex word data. Table 5. Test coverage
Algorithm March PS[5] March 12N[6] Proposed Method Length 23n 17n 12.8n SNPSF 0.25 0.25 0.22

When all memory cells are initialized by 1, NPSF patterns generated with 0000 word are presented in Table 4. Table 4. TN patterns ((Background:1s, Word-Data:0000)
TN1 TN2 TN3 TN4 Write step B N E W S B N E W S B N E W S B N E W S Init 1st 2nd 3rd 4th 5th
1 1 0 0 0 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 1 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 0 0 1 1 1 0 0 0 1 0 0 0 0 0

2.3

A Disturb Test Algorithm

Resistive shorts between memory cells, bit-lines, and word-lines are sources of disturb faults. Such disturb faults can be detected by repeated accesses to a same memory cell. Usually, disturb tests have features of wordline based tests. And target cells and neighborhood cells have complementary values to cause faults. However, the problem of disturb test is that the huge number of accesses are needed to detect disturb faults. Generally the repeated number is more than 20,000. Therefore, an efficient test algorithm is needed. The proposed disturb test algorithm classify all memory cells with word-line blocks for efficient test (i.e. one block is composed of four consecutive word-lines) and give active signals target word lines. The target word line is selected from every word-line block, and changed into the next adjacent word-line in the next test step. We give active signals to all selected word-lines sequentially while a timer for disturb test is expired. (In DRAM, the timers limit is a little longer than the refresh time of the DRAM Spec.) The disturb fault detection is done by reading from all memory cells. This sequence is repeated until all word-lines are tested. The test sequence is conceptually presented in Figure 4.

We can combine above two sequences. With this write sequence, the proposed efficient writing NPSF test algorithm is presented in Figure 3.
// The proposed NPSF test algorithm Setup WD and BW; // Initialize all cells if (Previous BW != BW) { write BW into all cells; // Test Length : n read data from all cells; // Test Length : n } else { // NPSF test sequence for (step=1; step<5; step++) { write_step(i); // Test Length : n/5 read data from all cells; // Test Length : n } WD = ~WD; for (step=1; step<4; step++) { write_step(i); // Test Length : n/5 read data from all cells; // Test Length : n } } // Write-Step module write_step(step) { CA = step -1; for (RA=0; RA<MAX_RA; RA++) { for (; CA<MAX_CA; CA+=5) { write WD into (RA,CA); } CA = step + 2; } } // WD : Word Data // BW : Background Word // n : the size of address space // RA : Row Address // MAX_RA : Maximum Row Address // CA : Column Address // MAX_CA : Maximum Column Address

Figure 4. Proposed disturb test sequence If the number of word-lines in a word-line block is increased, word-lines are get more stress, so that more disturb faults can be detected. Figure 5 presents the proposed disturb test algorithm in detail. The most of abbreviations are reused from Figure 3.

Figure 3. Proposed NPSF test algorithm

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// The proposed disturb test algorithm Setup BW and WBS; // Initialize all cells If (Current BW != BW) { write BW into all cells; read data from all cells; } else { // Disturb test sequence for (i=0; i<WBS; i++) { // Write ~BW into cells connected target word lines for (RA=0; RA<MAX_RA; RA++) { if (RA mod WBS == i) { for (CA=0; CA<MAX_CA; CA++) { write ~WD into (RA,CA); } } } restart disturb_timer; // Give active signal target word lines while (!disturb_timer) { for (RA=0; RA<MAX_RA; RA++) { if (RA mod WBS == i) { for (CA=0; CA<MAX_CA; CA++) { give active signal into (RA,CA); } } } refresh all memory cells; // For DRAM only read data from all cells; // Check disturb faults // Reset background cells for (RA=0; RA<MAX_RA; RA++) { if (RA mod WBS == i) { for (CA=0; CA<MAX_CA; CA++) { write BW into (RA,CA); } } } } } // WBS : Word-line Block Size // BW, RA, RA_MAX, CA, and CA_MAX are described in Figure 3.

The MBIST controller controls memory operations (i.e. read, write, and activate word-line), address generation schemes, and reporting diagnosis information. Furthermore, it controls a timer for disturb test. The address generator has two address counters (i.e. the one is for row address and the other is for column address). Thus, it can support flexible addressing mode. The data generator generates various word-data sequences using address-change-signal, so that we can support complex algorithms like NPSFs and disturb faults. The comparator checks faults and reports the diagnosis information.

Conclusions

In this paper, two test algorithms for word-oriented memories are proposed. NPSFs and disturb faults can be tested efficiently using the proposed NPSF test algorithm and disturb test algorithm. Furthermore, the proposed BIST architecture can be used for high density embedded memories. The RTL design and the real H/W implementation are our remaining future works.

References
[1] A. J. van de Goor, Testing Semiconductor Memories : theory and practice, Wiley, Chichester (UK), 1991. [2] S. Hamdioui, R. Wadsworth, J. D. Reyes, and A. J. van de Goor, Importance of Dynamic Faults for new SRAM Technologies, Proceedings of the IEEE European Test Workshop, pp. 29-34, May 2003. [3] Z. Al-Ars, Ad J. van de Goor, Static and Dynamic Behavior of Memory Cell Array Opens and Shorts in Embedded DRAMs, Proceedings of the IEEE Design Automation and Test in Europe, pp. 496-503, March 2001. [4] A. Benso and A. Bosio, March AB, march AB1: new march tests for unlinked dynamic memory faults, Proceedings of the International Test Conference, pp. 834-841, Nov. 2005. [5] V. Yarmolik and Yu. Klimets, March PS(23N) test for DRAM pattern-sensitive faults, Proceedings of Asian Test Symposium, pp. 354-357, Dec. 1998. [6] K.-L. Cheng and M.-F. Tsai, Efficient Neighborhood Patterns-Sensitive Fault Test Algorithms for Semiconductor Memories., Proceedings of the IEEE VLSI Test Symposium, pp. 225-230, May 2001. [7] A. Chrisarithopoulos and T. Haniotakis, New test pattern generation units for NPSF oriented memory builtin self test, Proceedings of the IEEE International Conference of Electronics, Circuits and Systems, Volume 2, pp. 749-752, Sept. 2001

Figure 5. Proposed disturb test algorithm

Proposed BIST Architecture

Figure 6 presents the proposed MBIST architecture which supports test algorithms in section 2.

Figure 6. Proposed MBIST architecture

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