Motivation and Goals Basic MCML Topology

MOS Current Mode Logic for • Develop a small library of MCML gates and blocks
R R
– What are the transistor sizing constraints?
Low Power Mixed-Signal Digital • Explore the feasibility of MCML for low power digital
Out

In0
Out

VDD
In0
Pull Vlow

Circuits circuits in comparison to standard CMOS design

– Compare over a variety of VDDs and Currents
In1
In1

InN
Down
Network
VDD
Vlow

VDD + RFP
InN Vlow
Vlow
-
• Examine benefits of MCML in a mixed-signal Inputs Inputs
RFN

environment I

– Static Current => No dI/dt effects

Basic MCML Gate Variable Delay Controller (VDC)
– Small switching noise for neighboring analog circuitry
Jason Musicer • Apply MCML to develop a larger block of logic • Completely differential logic style with low voltage swing
Professor Jan Rabaey – Pipelined CORDIC algorithm implemented • VDC sets value of load resistance to fix voltage swing for
different currents

MCML Circuits Basic Equations Adaptive Pipelining

Datapath

RFP
RFP RFP RFP
CMOS MCML CMOS-CML Converter
CMOS-CML Converter
CML-CMOS Converter
CML-CMOS Converter
RFP RFP
N ×C ×V dd N ×C ×∆V
Logic

DCMOS =
OUT
Out Out Inputs and Outputs
DMCML = NRC =
OUT OUT OUT
Out (Out) Out (Out) Registers

×(V dd − Vt )α
C C C C C D D k I
CMOS-CML Converter
CMOS-CML Converter
CML-CMOS Converter
CML-CMOS Converter
In In
B B B B
B 2
PMCML = N ×I ×V dd
B CLK CLK

1
= N ×C ×Vdd2 ×
RFP2
RFN
A A
A A RFN PCMOS VDC2

DCMOS VDC1
RFP1
Critical Path Model

RFN
RFN

PD MCML = N ×C ×∆V ×V dd
DLL
PDCMOS = N ×C ×V 2 2 Vlow RFP3
VDC3 Phase
dd Control
N 3 ×C 2 ×Vdd ×∆V 2
Detector
Clock
Buffer/Inverter AND/NAND/OR/NOR XOR3 D Latch C2 V dd2 EDMCML =
= N ×2 × ×
CMOS-CML Converter Buffer
2
EDCMOS RFN
• Pull Down Network identical to ECL style logic k (V dd − Vt )α I
Adaptively pipelined MCML system

• RFN control voltage sets amount of current • MCML has no optimal point for Energy-Delay • DLL adjusts current to meet clock frequency
• Dynamically adjusts for process and voltage variations
• RFP control voltage sets the voltage swing • N = logic depth must be kept small!

CORDIC Algorithm CORDIC Results Conclusion and Future Work

Nominal VDD (V) 2.5 2.0 1.5 1.0
• MCML is best for high performance, shallow pipeline
Equations
Worst Case VDD (V)
Nominal Delay (ns)
2.25
2.71
1.8
3.38
1.35
5.01
0.9
12.1 • Process and voltage variation is
Modei- 1 Sign i-1 X i-1 Register Y i-1 Register Worst Case Delay (ns) 3.68 4.78 7.57 21.7 architectures
Clock Frequency (MHz) 250 190 120 40 eliminated with adaptive
X i = X i− 1 + σi− 1 ×2 − i ×Yi− 1
Power (mW) 22.6 10.3 3.45 0.48
– Probably not great for general synthesis or low performance
Power-Delay (pJ)
Energy-Delay (pJ*ns)
90.4
362
54.2
285
28.8
240
12.0
300 pipelining
XNOR XOR CMOS CORDIC Results requirements
−i
Yi = Yi− 1 − σi− 1 ×2 × X i − 1 Performance Level
VDD (V)
High
1.1
Med.
1.05
Low
1.0 • MCML has lower energy-delay – Can get significant power savings if extra design time is invested
σi = sign(Yi ) ∈ (1,− 1)
Voltage Swing (V) 0.4 0.35 0.3

MUX
+ + Worst Case Delay (ns)
Clock Frequency (MHz)
3.29
275
4.86
185
7.84
115
for the high performance regime • Need to do layout to see effects of interconnect and area
Power (mW) 18.6 9.00 4.33
Power-Delay (pJ)
Energy-Delay (pJ*ns)
67.6
246
48.6
263
37.7
328 • CMOS performs better in the constraints
Modei Sign i X i Register Y i Register MCML CORDIC Results - No Adaptive Pipelining

Performance Level High Med. Low low performance domain • Need more detailed noise and matching analysis
CORDIC Pipeline Stage VDD (V) 1.1 1.05 1.0
Voltage Swing (V) 0.4 0.35 0.3 – What is the lowest voltage swing we can use?
• CORDIC iteratively computes angles of vectors
Nominal Delay (ns)
Clock Frequency (MHz)
2.94
310
4.45
200
7.30
125 • Current variation in MCML is
Power (mW) 18.6 9.00 4.33 • MCML shows promise for high performance, low power,
Power-Delay (pJ) 60 45.0 34.6
less than 5%
• Fully unfolded and pipelined implementation is used
Energy-Delay (pJ*ns) 194 225
MCML CORDIC Results - With Adaptive Pipelining
277
mixed signal design