Linearising Dual Slope Digital Converter Suitable for a Thermistor

Madhu Mohan N, Jagadeesh Kumar V and Sankaran P

Department of Electrical Engineering, Indian Institute of Technology Madras Chennai 600036, India. vjk@iitm.ac.in
Abstract The exponential resistance-temperature characteristic of a thermistor necessitates the use of a linearising circuit to ensure proper measurements whenever a thermistor is employed as a sensor for measuring temperature. A dual slope type resistance to digital converter that accepts a thermistor as input and provides a digital output linear to the temperature being sensed by the thermistor, is presented in this paper. The practicality of the proposed linearising dual slope digital converter is established through simulation studies. Keywords - Thermistors; linearisation; direct digital converter; resistance to digital converter; dual slope resistance to digital converter

Venmathi G and Vani M

Department of Instrumentation and Control Engineering National Institute of Technology Tiruchirapalli, India that use the exponential charge-discharge characteristics of resistance capacitance (R-C) circuits employed in multivibrators, for obtaining differing degrees of linearity over limited ranges of temperatures, have also been proposed [7][13]. Another way in which the output of a thermistor has been sought to be linearised is by including it as part of a logarithmic amplifier network [14]-[16]. A modified form of a temperature to frequency converter has been implemented using a delay network [17], with promising results. An innovative approach to solving the thermistor linearisation problem has been accomplished by using the inverseexponential nature of the voltage-time relationship obtained during the discharge of a resistor capacitor network that forms part of a modified square wave generator [18]. The output of most of these linearising circuits is analog in nature and needs to be converted to a digital form before being interfaced to the digital instruments which are widely used today. It would evidently make for a simpler and more robust system if the analog to digital converter were to be made an integral part of the linearising circuit, so that the final output is digitally compatible and linear to the temperature being sensed by the thermistor. A dual slope scheme that provides such a digital output is presented in this work. Results from simulation studies validate the proposed method. II. LINEARISING DIGITAL CONVERTER FOR THERMISTORS

I.

INTRODUCTION

Temperature is an important physical quantity to be measured in industrial applications involving instrumentation and/or control. Of the several kinds of temperature sensors, the thermistor type is sought after when the need for compactness, sensitivity, ruggedness, response time and biocompatibility is to be coupled with low price. However, the exponential relationship between the temperature and the resistance R (R characteristic) of a thermistor limits its usefulness as a preferred temperature sensor despite all the above advantages. Predicting the precise nature of the R- characteristic as well as finding possible ways of converting the exponential R- characteristic to a linear one have been a matter of study for a long time. The exponential nature of the resistance-temperature relationship of a thermistor was known as far back as 1946 [1]. Bosson et al formulated a three-constant fit for the log R versus 1/ curve of a thermistor in 1950 [2]. Later, a four constant fit was shown to depict the R- characteristic of a thermistor better than the three constant fit advocated earlier by Bosson [3], [4]. Schemes for obtaining a linear output proportional to the temperature being sensed by a thermistor employing analog or mixed (analog-digital) signal conditioning circuitry have also been proposed. One of the simplest means to achieve linearization is to include a resistor in series and/or parallel with the thermistor so that the response is almost linear with the change in the thermistor temperature over a small temperature range [5]. But with this technique, achievement of sufficiently good linearity is at the expense of drastically reduced dynamic range and sensitivity. A technique presented earlier incorporated the thermistor as one of the arms of a Wheatstone bridge, with the output being linearised by a three-point method [6]. Schemes

The block schematic of the proposed dual slope linearising resistance to digital converter (LRDC) suitable for a thermistor is shown in Fig. 1. The thermistor is connected to one of the inputs of a logarithmic amplifier [19], whose other input is served by a fixed value resistor RS. The output of the logarithmic amplifier is given as input to a single pole double throw (SPDT) analog switch S1. The second input of S1 is tied to a dc reference voltage VR. The output terminal PS1 of S1 is
C VR RS log amplifier -VR 1 S1 PS1 vlog 2 A1 Timer - Counter Digital Output R
+

ic
OA
voi
+ -

OC

vc Timing and Control Unit (TCU)

R Thermistor Clock fc

vlog = log(R) log(RS)

Fig. 1 Schematic of the proposed dual slope LRDC for a thermistor

978-1-4244-2833-5/10/$25.00 2010 IEEE

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voi
vc = 1 A1= 0 0 vc = 0 A1= 1

A1 = 1
VR RC
vlog

A1= 0

one in the former case and one to zero in the latter), indicating to the TCU, the end of the auto-zero phase. B. Conversion cycle

RC

T1

T2

vc
1 vc = 1 0 or 0 1 START Conversion vc = 1 0 END

Auto Zero

Fig. 2 Voltage waveforms at the output of the integrator (voi) and the comparator (vc)

connected to the RC integrator of a dual slope digital converter. The integrator output voi is fed to a comparator, whose output vc serves as the input to a timing and control unit (TCU) comprising an N-bit (for binary output LRDC) or N-digit (for a BCD output LRDC) pre-settable timer-counter, driven by a clock of period Tc (frequency fc). Switch S1 is controlled by the control line A1 from the TCU. If A1 is 1 (logic high), position 1 is selected on S1 and the dc reference voltage VR is applied as input to the RC integrator. If A1 is 0 (logic low) then position 2 is set on S1 and the output of the logarithmic amplifier vlog is chosen as the input to the integrator. The output of the integrator is sensed by the comparator. If the integrator output voi 0 then the output of the comparator vc will be 1 (logic high); otherwise vc will be zero. For a conversion, the TCU is programmed to perform two integrations by sensing vc and suitably operating switch S1 through control line A1. The first integration is for a pre-set period, say T1 seconds and the measurement of the second period of integration T2 is accomplished such that the output of the timer-counter at the end of T2 directly indicates the temperature that is being sensed by the thermistor. As in a typical dual slope converter, a proper conversion can be initiated if and only if the output of the integrator is zero. Hence here too, an auto-zero phase, where the output of the integrator is forced to become zero, is required to precede a conversion phase. A. The auto-zero phase If, in the initial state of the circuit, the output of the integrator voi is negative, then the output of the comparator will be zero. Sensing vc to be zero, the TCU logic asserts A1 to be 1, connecting -VR to the integrator. The current through the capacitor C, ic = VR /R. This current will discharge the capacitor and the output voi will ramp up and reach zero as indicated by the dashed line in Fig. 2. Fig. 2 portrays the typical waveforms at cardinal points in the circuit of Fig. 1. On the other hand, if the output of the integrator is positive at the start then vc will be 1. Sensing vc, the TCU logic sets A1 to be 0, connecting vlog to the integrator. The current ic = - vlog /R. will discharge the capacitor and the output voi will ramp down and reach zero as indicated by the dotted line in Fig. 2. As soon as voi reaches zero, the output of the comparator vc will toggle (from zero to

The LRDC can be operated either in a controlled (startstop) conversion or continuous conversion mode. In the start stop conversion mode, an auto-zero phase precedes every conversion cycle. In the continuous conversion mode of operation, the auto-zero phase is invoked only once at the start. In this mode, a new conversion is initiated at the end of a previous conversion and hence the name continuous conversion mode. Once the output of the integrator voi reaches zero (indicated by the transition on vc) at the end of an autozero phase (or at the end of a conversion in the continuous conversion mode), the TCU starts a new conversion cycle by asserting A1 to be 1, thus connecting -VR to the input of the integrator. This condition is maintained for a pre-set time period of T1 (=N1 clock cycles), with the help of the timercounter, with its register NTCU pre-set with the value N1 and its mode set to count down. At the end of T1, the timer-counter will roll over indicating to the TCU the end of the first period of integration. At the end of T1, the TCU toggles the switch S1 (by making A1 zero), connecting vlog to the input of the integrator. Simultaneously, the TCU pre-sets the timer-counter with a value (NFS - Nk) and sets the mode to count-up. Here NFS is the full scale value of the counter-timer and Nk is a pre-determined value, chosen based on the thermistor characteristic. In this condition, the output of the integrator will ramp down and reach zero after a period of T2 (N2 clock cycles) as indicated in Fig. 2. As soon as voi reaches zero, vc will toggle from one to zero. Sensing this,
Start 0 A1 = 1 0 vC 1 Auto zero 1 N
NTCU = 0?

vC

1 A1 = 0 0 vC

A1 = 1; N1 NTCU; Mode = down; Start timer

A1 = 0; (NFS - Nk) NTCU; Mode = up; Start timer 1 0 Stop Timer; NTCU N2 : Output N2 End

vC

Fig. 3 Flowchart showing the auto zero and conversion logic of the proposed dual slope LRDC suitable for a thermistor

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Conversion

the TCU stops the timer-counter and outputs N2, the value of NTCU at that instant. The flow chart of Fig. 3 outlines the logic for both the conversion and the auto-zero phases. In a given conversion cycle, the net charge gained by the capacitor C of the integrator is zero. Hence, we have

vlog VR T1 = T2 RC RC

(1)

T1 = N1Tc and T2 = ( N1 + N k )Tc

(2)

Substituting the values of T1 and T2 from equation (2) in equation (1) results in N2 = VR N1 Nk vlog (3)

The resistance-temperature characteristic of a thermistor is given by the Bosson equation [2]

C. Simulation of the dual slope LRDC To simulate the proposed LRDC scheme, the PSpice from the OrCAD suite of software (version 16.2) from M/s Cadence Corporation package was chosen. The OP97 was the choice of opamp for the integrator while the LM311 was used as the comparator. The switch S1 was realized with the ADG508 analog switch from M/s Analog Devices. The LOG112 from M/s Texas Instruments was used for the logarithmic amplifier. The timing and control unit (TCU) was realized with simple digital gates, generating the logic necessary for initiating and controlling the switching sequence as given in the flow chart of Fig. 3. The clock was modeled as a simple digital stimulus running at a conservative 1 MHz, while the fixed time period T1 was chosen as 100 ms and generated using an NE555 IC. The resistance of the thermistor R , was replaced by a variable resistance whose value was varied as per the model (the expression and coefficients) provided by M/s Vishay Electronics for their SMD0603 Glass encapsulated series of negative temperature coefficient thermistors [20].
The simulation was run with Gmin stepping to improve the speed of convergence, on a notebook computer with an Intel Pentium (M) processor running at 1.7 GHz and having 2 GB of RAM. The resolution selected for voltages and currents were 10 V and 100 pA respectively. It has to be pointed that the circuit was simulated with as realistic a model as possible with the relevant sources of errors discussed in the previous section included in the model. The temperature was chosen as the parameter of variation, varying from 0 oC to 120 oC in steps of 5 oC. Fig. 4 shows the screen shot obtained at the end of a typical simulation run portraying the outputs at three significant points on the circuit, namely, the outputs of the timer, the comparator and the integrator. The outputs of the integrator, timer and the comparator are given the tags v(u1:out), v(timer) and v(COMP_1) respectively. The time period to be measured T2, is obtained by measuring the interval between the falling edges of the signals v(timer) and v(COMP_1). For each temperature setting the corresponding value of the thermistor resistance is obtained from the characteristic curve provided by the manufacturer and set as the value for R. The simulation was then run and T2 automatically measured and plotted against the set value of temperature. The expected value of T2 corresponding to the set temperature is then calculated from the manufacturers data sheet and compared with the measured value of T2, to determine the deviation of the output of the circuit from the ideal expected behavior, and hence the error in the output. The measured temperature versus the set temperature characteristics, obtained from the simulation study and the error calculated as explained above are plotted in Fig. 5. It is seen from Fig. 5 that the error in the digital output from the LRDC is less than 0.12 %, over the entire practically usable temperature range of 0 C to 120 C, thereby validating the discussion and analysis of the previous sections as well as justifying the prototyping of the circuit.

log R = k1 +

k2 , + k3

(4)

where, R is the resistance of the thermistor at the temperature and k1 , k2 and k3 are constants. The output of the logarithmic amplifier can be derived as [19]

vlog = log R log RS ,

(5)

Substituting the value of log R from equation (5) in equation (4) we get: k2 vlog = k1 + log RS . (6) + k3 If the value of RS is chosen such that log RS = k1 , then equation (6) simplifies to k2 vlog = , (7) + k3 Substituting the value of vlog from equation (7) in equation (3) results in

N2 =

V R N1 V N + R 1 k3 N k k2 k2

(8)

V R N1 k 3 , then we get, k2 V N N2 = R 1 . (9) k2 From equation (9), it is evident that the final digital output N2 is linear with respect to the temperature being sensed by the V N thermistor, provided log RS = k1 and N k = R 1 k 3 . In order k2 to verify the proposed technique, the circuit schematic given in Fig. 1 was simulated and its performance studied under various conditions.
If N k is chosen to be equal to

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A1

vc

voi

T1

T2

Auto Zero

Conversion

Fig. 4 Screenshot of a simulation run of the proposed LRDC

III.

CONCLUSIONS

A novel dual slope linearising resistance to digital converter that accepts a thermistor as input and provides a digital output directly proportional to the temperature being sensed by the thermistor is presented in this work. The exponential resistance-temperature characteristic is suitably compensated by employing a logarithmic amplifier. Criteria for the selection of the various circuit constants so as to obtain an elegant expression for the final digital output have been derived. The efficacy of the scheme has been verified through simulation
120 0.24 0.16 0.08 0.00 -0.08
Output Error

studies. Results obtained from the simulation validate the proposed technique. Testing of a prototype unit is being carried out. REFERENCES
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[2]

[3]

Measured temperature ( C)

100 80 60 40 20 0 0 20 40 60 80
o

[4]
Error (% FS)

[5] [6]

-0.16 -0.24

[7]

100

120

Set temperature ( C)

[8]

Fig. 5 Results of the PSpice Simulation of the proposed circuit

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