Multichannel ISM Band FSK/GFSK/OOK/GOOK/ASK Transmitter ADF7012

FEATURES
Single-chip, low power UHF transmitter 75 MHz to 1 GHz frequency operation Multichannel operation using Frac-N PLL 2.3 V to 3.6 V operation On-board regulatorstable performance Programmable output power: 16 dBm to +14 dBm, 0.4 dB steps Data rates: dc to 179.2 kbps Low current consumption: 868 MHz, 10 dBm, 21 mA 433 MHz, 10 dBm, 17 mA 315 MHz, 0 dBm, 10 mA Programmable low battery voltage indicator 24-lead TSSOP

GENERAL DESCRIPTION
The ADF7012 is a low power FSK/GFSK/OOK/GOOK/ASK UHF transmitter designed for short range devices (SRDs). The output power, output channels, deviation frequency, and modulation type are programmable by using four, 32-bit registers. The fractional-N PLL and VCO with external inductor enable the user to select any frequency in the 75 MHz to 1 GHz band. The fast lock times of the fractional-N PLL make the ADF7012 suitable in fast frequency hopping systems. The fine frequency deviations available and PLL phase noise performance facilitates narrow-band operation. There are five selectable modulation schemes: binary frequency shift keying (FSK), Gaussian frequency shift keying (GFSK), binary on-off keying (OOK), Gaussian on-off keying (GOOK), and amplitude shift keying (ASK). In the compensation register, the output can be moved in <1 ppm steps so that indirect compensation for frequency error in the crystal reference can be made. A simple 3-wire interface controls the registers. In power-down, the part has a typical quiescent current of <0.1 A.

APPLICATIONS
Low cost wireless data transfer Security systems RF remote controls Wireless metering Secure keyless entry

FUNCTIONAL BLOCK DIAGRAM

PRINTED INDUCTOR OSC1 OSC2 CLKOUT CPVDD CPGND L1 L2 CREG

CVCO

OOK\ASK CLK

VDD

VCO PA
RFOUT

R DVDD

PFD/ CHARGE PUMP

RF GND

DGND

CREG

OOK\ASK TxCLK

+FRACTIONAL N

LDO REGULATOR

TxDATA

FSK\GFSK

LE DATA CLK CE SERIAL INTERFACE

PLL LOCK DETECT

FREQUENCY COMPENSATION CENTER FREQUENCY

MUXOUT

MUXOUT BATTERY MONITOR

RSET
04617-0-001

AGND

Figure 1. Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2004 Analog Devices, Inc. All rights reserved.

ADF7012 TABLE OF CONTENTS

Specifications..................................................................................... 3 Timing Characteristics..................................................................... 5 Absolute Maximum Ratings............................................................ 6 Transistor Count........................................................................... 6 ESD Caution.................................................................................. 6 Pin Configuration and Function Descriptions............................. 7 Typical Performance Characteristics ............................................. 8 315 MHz ........................................................................................ 8 433 MHz ........................................................................................ 9 868 MHz ...................................................................................... 10 915 MHz ...................................................................................... 11 Circuit Description......................................................................... 12 PLL Operation ............................................................................ 12 Crystal Oscillator........................................................................ 12 Crystal Compensation Register................................................ 12 Clock Out Circuit ....................................................................... 12 Loop Filter ................................................................................... 13 Voltage-Controlled Oscillator (VCO) ..................................... 13 Voltage Regulators...................................................................... 13 FSK Modulation.......................................................................... 13 GFSK Modulation ...................................................................... 14 Power Amplifier.......................................................................... 14 GOOK Modulation .................................................................... 15 Output Divider ........................................................................... 16 MUXOUT Modes....................................................................... 16 Theory of Operation ...................................................................... 17 Choosing the External Inductor Value.................................... 17 Choosing the Crystal/PFD Value............................................. 17 Tips on Designing the Loop Filter ........................................... 17 PA Matching................................................................................ 18 Transmit Protocol and Coding Considerations ..................... 18 Application Examples .................................................................... 19 315 MHz Operation ................................................................... 20 433 MHz Operation ................................................................... 21 868 MHz Operation ................................................................... 22 915 MHz Operation ................................................................... 23 Register Descriptions ..................................................................... 24 R Register..................................................................................... 24 N-Counter Latch ........................................................................ 25 Modulation Register .................................................................. 26 Function Register ....................................................................... 27 Outline Dimensions ....................................................................... 28 Ordering Guide .......................................................................... 28

REVISION HISTORY
10/04Revision 0: Initial Version

Rev. 0 | Page 2 of 28

ADF7012 SPECIFICATIONS
DVDD = 2.3 V 3.6 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating temperature range is 40C to +85C. Table 1.
Parameter RF OUTPUT CHARACTERISTICS Operating Frequency Phase Frequency Detector MODULATION PARAMETERS Data Rate FSK/GFSK Data Rate ASK/OOK Deviation FSK/GFSK GFSK BT ASK Modulation Depth OOK Feedthrough (PA Off) POWER AMPLIFIER PARAMETERS Max Power Setting, DVDD = 3.6 V Max Power Setting, DVDD = 3.0 V Max Power Setting, DVDD = 2.3 V Max Power Setting, DVDD = 3.6 V Max Power Setting, DVDD = 3.0 V Max Power Setting, DVDD = 2.3 V PA Programmability POWER SUPPLIES DVDD Current Comsumption 315 MHz, 0 dBm/5 dBm 433 MHz, 0 dBm/10 dBm 868 MHz, 0 dBm/10 dBm/14 dBm 915 MHz, 0 dBm/10 dBm/14 dBm VCO Current Consumption Crystal Oscillator Current Consumption Regulator Current Consumption Power-Down Current REFERENCE INPUT Crystal Reference Frequency Single-Ended Reference Frequency Crystal Power-On Time 3.4 MHz/26 MHz Single-Ended Input Level B Version 75/1000 FRF/128 179.2 64 PFD/214 511 PFD/214 0.5 25 40 80 14 13.5 12.5 14.5 14 13 0.4 2.3/3.6 8/14 10/18 14/21/32 16/24/35 1/8 190 280 0.1/1 3.4/26 3.4/26 1.8/2.2 CMOS Levels Unit MHz min/max Hz min kbps Kbps Hz min Hz max typ dB max dBm typ dBm typ dBm dBm dBm dBm dBm dBm dB typ V min/V max mA typ mA typ mA typ mA typ mA min/max A typ A typ A typ/max MHz min/max MHz min/max ms typ CE to Clock Enable Valid Refer to the LOGIC INPUTS parameter. Applied to OSC 2 oscillator circuit disabled. DVDD = 3.0 V, PA is matched into 50 , IVCO = min Using 1 MHz loop bandwidth Based on US FCC 15.247 specfications for ACP; higher data rates are achievable depending on local regulations For example, 10 MHz PFD deviation min = 610 Hz For example, 10 MHz PFD deviation max = 311.7 kHz Conditions/Comments VCO range adjustable using external inductor; divide-by-2, -4, -8 options may be required

FRF = Fvco FRF = Fvco/2 FRF = 915 MHz, PA is matched into 50 FRF = 915 MHz, PA is matched into 50 FRF = 915 MHz, PA is matched into 50 FRF = 433 MHz, PA is matched into 50 FRF = 433 MHz, PA is matched into 50 FRF = 433 MHz, PA is matched into 50 PA output = 20 dBm to +13 dBm

VCO current consumption is programmable

Rev. 0 | Page 3 of 28

ADF7012
Parameter PHASE-LOCKED LOOP PARAMETERS VCO Gain 315MHz 433MHz 868MHz 915MHz VCO Tuning Range Spurious (IVCO Min/Max) Charge Pump Current Setting [00] Setting [01] Setting [10] Setting [11] Phase Noise (In band)1 315MHz 433MHz 868MHz 915MHz Phase Noise (Out of Band)1 315MHz 433MHz 868MHz 915MHz Harmonic Content (Second)2 Harmonic Content (Third)2 Harmonic Content (Others)2 Harmonic Content (Second)2 Harmonic Content (Third)2 Harmonic Content (Others)2 LOGIC INPUTS Input High Voltage,VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output High Current, IOH, Output Low Voltage, VOL B Version Unit Conditions/Comments

22 24 80 88 0.3/2.0 65/70 0.3 0.9 1.5 2.1 85 83 80 80 103 104 115 114 20 30 27 24 14 19 0.7 DVDD 0.2 DVDD 1 4.0 DVDD 0.4 500 0.4

MHz/V typ MHz/V typ MHz/V typ MHz/V typ V min/max dBc mA typ mA typ mA typ mA typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc typ dBc typ dBc typ dBc typ dBc typ dBc typ V min V max A max pF max V min A max V max

VCO divide-by-2 active VCO divide-by-2 active

IVCO is programmable Refering to DB[7:6] in Function Register Refering to DB[7:6] in Function Register Refering to DB[7:6] in Function Register Refering to DB[7:6] in Function Register PFD = 10 MHz, 5 kHz offset, IVCO = 2 mA PFD = 10 MHz, 5 kHz offset, IVCO = 2 mA PFD = 10 MHz, 5 kHz offset, IVCO = 3 mA PFD = 10 MHz, 5 kHz offset, IVCO = 3 mA PFD = 10 MHz, 1 MHz offset, IVCO = 2 mA PFD = 10 MHz, 1 MHz offset, IVCO = 2 mA PFD = 10 MHz, 1 MHz offset, IVCO = 3 mA PFD = 10 MHz, 1 MHz offset, IVCO = 3 mA FRF = FVCO

FRF = FVCO/N (where N = 2, 4, 8)

CMOS output chosen IOL = 500 A

1 2

Measurements made with NFRAC = 2048. Measurements made without harmonic filter.

Rev. 0 | Page 4 of 28

ADF7012 TIMING CHARACTERISTICS

DVDD = 3 V 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 2.
Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE setup time Data-to-clock setup time Data-to-clock hold time Clock high duration Clock low duration Clock to-LE setup time LE pulse width

t4
CLOCK

t5

t2
DATA DB23 (MSB) DB22

t3
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)

t7
LE

t1
LE

t6
04617-0-002

Figure 2. Timing Diagram

Rev. 0 | Page 5 of 28

ADF7012 ABSOLUTE MAXIMUM RATINGS

TA = 25C, unless otherwise noted. Table 3.
Parameter DVDD to GND (GND = AGND = DGND = 0 V) Digital I/O Voltage to GND Analog I/O Voltage to GND Operating Temperature Range Maximum Junction Temperature TSSOP JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Rating 0.3 V to +3.9 V 0.3 V to DVDD + 0.3 V 0.3 V to DVDD + 0.3 V 150C 150.4C/W 215C 220C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of 1 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly.

TRANSISTOR COUNT
35819 (CMOS)

ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 6 of 28

ADF7012 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

DVDD 1 CREG1 2 CPOUT 3 TxDATA 4 TxCLK 5 MUXOUT 6 TSSOP
24 23 22 21 20

CREG2 RSET AGND DVDD RFOUT

ADF7012

19 RFGND TOP VIEW DGND 7 (Not to Scale) 18 VCOIN

OSC1 8 OSC2 9 CLKOUT 10 CLK 11 DATA 12

17 16 15 14 13

CVCO L2 L1 CE LE
04617-0-003

Figure 3.

Table 4. Pin Functional Descriptions

Pin No. 1 2 3 4 5 Mnemonic DVDD CREG1 CPOUT TxDATA TxCLK Description Positive Supply for the Digital Circuitry. This must be between 2.3 V and 3.6 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. A 2.2 F capacitor should be added at CREG to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time, but may cause higher spurious noise. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Digital Data to Be Transmitted is inputted on this pin. GFSK and GOOK only. This clock output is used to synchronize microcontroller data to the TxDATA pin of the ADF7012. The clock is provided at the same frequency as the data rate. The microcontroller updates TxDATA on the falling edge of TxCLK. The rising edge of TxCLK is used to sample TxDATA at the midpoint of each bit. Provides the Lock_Detect Signal. This determines if the PLL is locked to the correct frequency and also monitors battery voltage. Other signals include Regulator_Ready, which indicates the status of the serial interface regulator. Ground for Digital Section. The reference crystal should be connected between this pin and OSC2. The reference crystal should be connected between this pin and OSC1. A TCXO reference may be used, by driving this pin with CMOS levels, and powering down the crystal oscillator bit in software. A divided-down version of the crystal reference with output driver. The digital clock output may be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark-space ratio. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 32-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Chip Enable. Bringing CE low puts the ADF7012 into complete power-down, drawing < 1uA. Register values are lost when CE is low and the part must be reprogrammed once CE is brought high. Connected to external printed or discrete inductor. See Choosing the External Inductor Value for advice on the value of the inductor to be connected between L1 and L2. Connected to external printed or discrete inductor. A 220 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7012. This capacitor is necessary to ensure stable VCO operation. The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage, the higher the output frequency. Ground for Output Stage of Transmitter. The modulated signal is available at this pin. Output power levels are from 16 dBm to +12 dBm. The output should be impedance matched using suitable components to the desired load. See the PA Matching section. Voltage supply for VCO and PA section. This should have the same supply as DVDD Pin 1, and should be between 2.3 V and 3.6 V. Place decoupling capacitors to the analog ground plane as close as possible to this pin. Ground Pin for the RF Analog Circuitry. External Resistor to set charge pump current and some internal bias currents. Use 3.6 kV as default. Add a 470 nF capacitor at CREG to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time and phase noise, but may have stability issues over the supply and temperature.
Rev. 0 | Page 7 of 28

6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

MUXOUT DGND OSC1 OSC2 CLKOUT CLK DATA LE CE L1 L2 CVCO VCOIN RFGND RFOUT DVDD AGND RSET CREG2

ADF7012 TYPICAL PERFORMANCE CHARACTERISTICS

315 MHZ
60 70 80 90 = NORMAL FREQUENCY = 9.08 kHz LEVEL = 84.47dBc/Hz
5 0 10 20 30 2 4 D1 41.5dBm 1MA REF LVL 5dBm 1 3 RBW 1MHz RF ATT 30dB 0.27dBm VBW 1MHz 308.61723447MHz SWT 17.5ms UNIT dBm
A

dBc (Hz)

100 110 120 130 140 1.0k

04617-0-004

40 50 60 70 1 [T1] 80 2 [T1] 90 95

4 [T1]

10.0k

100.0k PHASE NOISE (Hz)

1.0M

10.0M

CENTER 3.5MHz

700MHz/

SPAN 7GHz

Figure 4. Phase Noise ResponseDVDD = 3.0 V, ICP = 0.86 mA IVCO = 2.0 mA, FOUT = 315 MHz, PFD = 3.6864 MHZ, PA Bias = 5.5 mA
REF LVL 5dBm 5 0 10 20 30 40 50 60 70
04617-0-005

Figure 7. Harmonic Response, RFOUT Matched to 50 , No Filter

RBW 1MHz RF ATT 30dB 0.18dBm VBW 1MHz 308.61723447MHz SWT 17.5ms UNIT dBm
A

RBW 0.45dBm VBW 315.05060120MHz SWT 1 2

5kHz RF ATT 30dB 5kHz dBm 500ms UNIT

A

REF LVL 5dBm 5 0 10 20 1MA 30 40 50 60 70 1 [T1] 2 4 3 1

04617-0-007

0.27dBm 308.61723447MHz 35.43dBm 631.26252505MHz

3 [T1]

11.48dBm 939.87975952MHz 34.11dBm 1.26252505GHz

SGL

1MA D1 41.5dBm

2 [T1] 90 95

4 [T1]

90 95 CENTER 315MHz 50kHz/ SPAN 500kHz

CENTER 3.5MHz

700MHz/

SPAN 7GHz

Figure 5. FSK Modulation, Power = 0 dBm, Data Rate = 1 kbps, FDEVIATION = 50 kHz
REF LVL 5dBm 5 0 10 20 30 40 50 60 70
04617-0-006

Figure 8. Harmonic Response, Fifth-Order Butterworth Filter

RBW 20.33dBm VBW 26.55310621kHz SWT 1 5kHz RF ATT 30dB 5kHz dBm 500ms UNIT
A

RBW 500kHz RF ATT 30dB 0.31dBm VBW 500kHz 315.40080160MHz SWT dBm 5ms UNIT 1
A

REF LVL 5dBm 5 0 10 20

1MA

3 1MA

30 40 50 60 70 80 90 95 1 [T1] 3 [T1] 2 [T1] 3.49dBm 315.00012525MHz 20.33dB 26.55310621kHz 20.85dB 27.55511022kHz 50kHz/ SPAN 500kHz

D1 41.5dBm D2 49dBm

90 95

1 [T1]

0.31dBm 315.40080160MHz 40MHz/ SPAN 400MHz

CENTER 315MHz

CENTER 315MHz

Figure 6. Spurious ComponentsMeets FCC Specs

Rev. 0 | Page 8 of 28

Figure 9. OOK Modulation, Power = 0 dBm, Data Rate = 10 kbps

04617-0-009

80

04617-0-008

80

80

0.18dBm 308.61723447MHz 50.53dBm 631.26252505MHz

3 [T1]

42.93dBm 939.87975952MHz 55.48dBm 1.26252505GHz

ADF7012
433 MHZ
1 2.00V/ 2 1.00V/ 1.50ms 500s TRIG'D 1 720mv
15 10 0 10 20 1MA REF LVL 15dBm RBW 10.01dBm VBW 433.91158317MHz SWT 1 30kHz RF ATT 40dB 30kHz dBm 90ms UNIT
A

2 CLKOUT

30 40 50 60
04617-0-010

D1 36dBm

1 CE

80 85 CENTER 433.9500601MHz 3.2MHz/ SPAN 32MHz

Figure 10. Crystal Power-On Time, 4 MHz, Time = 1.6 ms

40 60 80 100 = NORMAL FREQUENCY = 393.38 kHz LEVEL = 102.34dBc/Hz

Figure 13. Spurious ComponentsMeets ETSI Specs

REF LVL 15dBm 15 10 0 10 20 2 1 3 4 1MA D1 30dBm D1 36dBm RBW 1MHz RF ATT 40dB 10.10dBm VBW 1MHz 434.86973948MHz SWT 17.5ms UNIT dBm
A

dBc (Hz)

120
30

140 160 180 200 1.0k

04617-0-011

40 50 60 1 [T1] 70 2 [T1] 80 85

4 [T1]

10.0k

100.0k PHASE NOISE (Hz)

1.0M

10.0M

CENTER 3.5GHz

700MHz/

SPAN 7GHz

Figure 11. Phase Noise ResponseICP = 2.0 mA, IVCO = 2.0 mA, RFOUT = 433.92 MHz, PFD = 4 MHz, PA Bias = 5.5 mA
REF LVL 15dBm 15 10 0 10 20 30 40 50 60
04617-0-012

Figure 14. Harmonic Response, RFOUT Matched to 50 , No Filter

RBW 1MHz RF ATT 40dB 9.51dBm VBW 1MHz 434.86973948MHz SWT 17.5ms UNIT dBm
A

RBW 10kHz RF ATT 40dB 5.60dBm VBW 300kHz 433.91158317MHz SWT dBm 44ms UNIT 1
A

REF LVL 15dBm 15 10 0 10 1MA 20 30 2 3 1

04617-0-014

10.10dBm 434.86973948MHz 15.25dBm 869.73947896MHz

3 [T1]

5.12dBm 1.30460922GHz 17.57dBm 1.73947896GHz

D1 30dBm 4 D1 36dBm

D1 36dBm

40 50 60 1 [T1]

2 [T1] 80 85

4 [T1]

80 85 START 433.05MHz 174kHz/ STOP 434.79kHz

CENTER 3.5GHz

700MHz/

SPAN 7GHz

Figure 12. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps, FDEVIATION = 19.28 kHz

Figure 15. Harmonic Response, Fifth-Order Butterworth Filter

Rev. 0 | Page 9 of 28

04617-0-015

70

70

9.51dBm 434.86973948MHz 33.75dBm 869.73947896MHz

3 [T1]

43.60dBm 1.30460922GHz 43.44dBm 1.73947896GHz

04617-0-013

70

SGL

1MA

ADF7012
868 MHZ
0 20 40 60 = NORMAL FREQUENCY = 251.3 kHz LEVEL = 99.39dBc/Hz
15 10 0 10 20 1MAX D1 30dBm REF LVL 15dBm 1 2 3 4 1MA RBW 12.27dBm VBW 869.33867735MHz SWT 1MHz RF ATT 40dB 1MHz dBm 16ms UNIT
A

dBc (Hz)

80 100 120 140 160 1.0k

04617-0-016

30 40 50 60 1 [T1] 70 80 85 2 [T1]

4 [T1]

10.0k

100.0k PHASE NOISE (Hz)

1.0M

10.0M

CENTER 3.8GHz

640MHz/

SPAN 6.4GHz

Figure 16. Phase Noise ResponseICP = 2.5 mA, IVCO = 1.44 mA, RFOUT = 868.95 MHz, PFD = 4.9152 MHz, Power = 12.5 dBm, PA Bias = Max
REF LVL 15dBm 15 10 0 10 20 1MAX 30 40 50 60 1 [T1] 70 2 [T1] 80 85
04617-0-017

Figure 19. Harmonic Response, RFOUT Matched to 50 , No Filter

30dB RBW 1kHz RF ATT 10.39dBm VBW 1kHz MIXER 20dBm 869.33867735MHz SWT 10ms UNIT dBm 1 [T1] 3 [T1] 2 [T1] 1MAX D2 30dBm 10.39dBm 869.33867735MHz 50.92dBm 1.72000000GHz 50.40dBm 2.59600000GHz
A

30dB RBW 10kHz RF ATT 40.44dBm VBW 10kHz MIXER 20dBm 869.20000000MHz SWT 15ms UNIT dBm 2
A

REF LVL 15dBm LN 15 10 0 10 1MA 20 30 1

04617-0-019

12.27dBm 869.33867735MHz 4.00dBm 1.72865731GHz

3 [T1]

16.88dBm 2.59699399GHz 15.06dBm 3.46913828GHz

LN

1MA

D2 36dBm

40 50 60
04617-0-020

40.44dBm 869.20000000MHz 8.02dBm 868.96673347MHz 60kHz/ SPAN 600kHz

70 80 85 START 3.8GHz 640MHz/ SPAN 6.4GHz

CENTER 868.944489MHz

Figure 17. FSK Modulation, Power = 12.5 dBm, Data Rate = 38.4 kbps, FDEVIATION = 19.2 kHz
REF LVL 15dBm 15 10 0 10 20 1MAX 30 40 50 60
04617-0-018

Figure 20. Harmonic Response, Fifth-Order Chebyshev Filter

RBW 12.55dBm VBW 869.025050100MHz SWT 1 1 [T1] 2 [T1] 3 [T1]

30dB 2kHz RF ATT 2kHz MIXER 20dBm dBm 16s UNIT 12.55dBm 869.02505010MHz 57.89dBm 859.16695500MHz 81.97dBm 862.00000000MHz
A

LN

1MA

D2 36dBm

D1 54dBm

70 80 85 3 START 856.5MHz 2.5MHz/ STOP 881.5MHz

Figure 18. Spurious ComponentsMeets ETSI Specs

Rev. 0 | Page 10 of 28

ADF7012
915 MHZ
40 60 80 100 = NORMAL FREQUENCY = 992.38 kHz LEVEL = 102.34dBc/Hz REF LVL 15dBm 15 10 0 10 20 120 30 140 160
04617-0-021

RBW 50MHz RF ATT 40dB 10.25dBm VBW 50MHz 907.81563126MHz SWT dBm 6.4s UNIT
A

2 1MAX 3 4 1MA

dBc (Hz)

40 50 60 1 [T1] 70 2 [T1] 80 85

D1 41.5dBm

180 200 1.0k

10.0k

100.0k PHASE NOISE (Hz)

1.0M

10.0M

4 [T1]

CENTER 3.8GHz

640MHz/

SPAN 6.4GHz

Figure 21. Phase Noise ResponseICP = 1.44 mA, IVCO = 3.0 mA, RFOUT = 915.2 MHz, PFD =10 MHz, Power = 10 dBm, PA Bias = 5.5 mA
REF LVL 15dBm 15 10 0 10 20 1MAX 30 40 50 60
04617-0-036

Figure 24. Harmonic Response, RFOUT Matched to 50 , No Filter

RBW 50MHz RF ATT 40dB 9.06dBm VBW 50MHz 907.81563126MHz SWT dBm 6.4s UNIT
A

RBW 10kHz RF ATT 40dB 3.88dBm VBW 300kHz 915.19098196MHz SWT 15ms UNIT dBm 1
A

REF LVL 15dBm 15 10 0 10 1MA 20 30 40 2 50 60 1 [T1] 1MAX 1

1MA

D1 41.5dBm

2 [T1] 80 85

4 [T1]

80 85 CENTER 915.190982MHz 50kHz/ SPAN 500kHz

CENTER 3.8GHz

640MHz/

SPAN 6.4GHz

Figure 22. FSK Modulation, Power = 10 dBm, Data Rate = 38.4 kbps, Fdeviation = 19.2 kHz
REF LVL 15dBm 15 10 0 10 20 30 40 50 60
04617-0-037

Figure 25. Harmonic Response, Fifth-Order Chebyshev Filter

RBW 10kHz RF ATT 40dB 9.94dBm VBW 300kHz 915.23167977MHz SWT 100ms UNIT dBm 1 *
A

SGL

1MA

D1 41.5dBm D1 49.5dBm

70 80 85 CENTER 915.2MHz 40MHz/ SPAN 400MHz

Figure 23. Spurious ComponentsMeets FCC Specs

Rev. 0 | Page 11 of 28

04617-0-039

70

70

9.06dBm 907.81563126MHz 48.40dBm 1.83126253GHz

3 [T1]

46.22dBm 2.74188377GHz 46.96dBm 3.65250501GHz

04617-0-038

10.25dBm 907.81563126MHz 10.06dBm 1.83126253GHz

3 [T1]

20.29dBm 2.74188377GHz 17.50dBm 3.65250501GHz

ADF7012 CIRCUIT DESCRIPTION

PLL OPERATION
A fractional-N PLL allows multiple output frequencies to be generated from a single-reference oscillator (usually a crystal) simply by changing the programmable N value found in the N register. At the phase frequency detector (PFD), the reference is compared to a divided-down version of the output frequency (VCO/N). If VCO/N is too low a frequency, typically the output frequency is lower than desired, and the PFD and charge-pump combination sends additional current pulses to the loop filter. This increases the voltage applied to the input of the VCO. Because the VCO of the ADF7012 has a positive frequency vs. voltage characteristic, any increase in the Vtune voltage applied to the VCO input increases the output frequency at a rate of kV, the tuning sensitivity of the VCO (MHz/V). At each interval of 1/PFD seconds, a comparison is made at the PFD until the PFD and charge pump eventually force a state of equilibrium in the PLL where PFD frequency = VCO/N. At this point, the PLL can be described as locked.
CRYSTAL/R R PFD CP VCO VCO/N
04617-0-022

OSC1
CP2

OSC2
CP1
04617-0-023

Figure 27.

Two parallel resonant capacitors are required for oscillation at the correct frequencythe value of these depend on the crystal specification. They should be chosen so that the series value of capacitance added to the PCB track capacitance adds to give the load capacitance of the crystal, usually 20 pF. Track capacitance values vary between 2 pF to 5 pF, depending on board layout. Where possible, to ensure stable frequency operation over all conditions, capacitors should be chosen so that they have a very low temperature coefficient and/or opposite temperature coefficients

LOOP FILTER FVCO

CRYSTAL COMPENSATION REGISTER

The ADF7012 features a 15-bit fixed modulus, which allows the output frequency to be adjusted in steps of FPFD/15. This fine resolution can be used to easily compensate for initial error and temperature drift in the reference crystal. FADJUST = FSTEP FEC where FSTEP = FPFD/215 and FEC = Bits F1 to F11 in the R Register. Note that the notation is twos compliment, so F11 represents the sign of the FEC number. Example FPFD = 10 MHz FADJUST = 11 kHz FSTEP = 10 MHz/215 = 305.176 Hz FEC = 11 kHz/305.17 Hz = 36 = (00000100100) = 11111011100 = 0x7DC (3)

Figure 26.

FOUT =

FCRYSTAL N = FPFD N R

(1)

For a Fractional N PLL

N FOUT = FPFD N INT + FRAC 12 2

(2)

where NFRAC can be bits M1 to M12 in the fractional N register.

CRYSTAL OSCILLATOR
The on-board crystal oscillator circuitry (Figure 27) allows an inexpensive quartz crystal to be used as the PLL reference. The oscillator circuit is enabled by setting XOEB low. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected using the error correction register within the R register. A single-ended reference may be used instead of a crystal, by applying a square wave to the OSC2 pin, with XOEB set high.

CLOCK OUT CIRCUIT

The clock out circuit takes the reference clock signal from the oscillator section above and supplies a divided-down 50:50 mark-space signal to the CLKOUT pin. An even divide from 2 to 30 is available. This divide is set by the DB[19:22] in the R register. On power-up, the CLKOUT defaults to divide by 16.
DVDD CLKOUT ENABLE BIT

Figure 28.
Rev. 0 | Page 12 of 28

04617-0-024

OSC1

DIVIDER 1 TO 15

CLKOUT

ADF7012
The output buffer to CLKOUT is enabled by setting Bit DB4 in the function register high. On power-up, this bit is set high. The output buffer can drive up to a 20 pF load with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A small series resistor (50 ) can be used to slow the clock edges to reduce these spurs at FCLK. Figure 32 shows the VCO gain over temperature and frequency. VCO gain is important in determining the loop filter design predictable changes in VCO gain resulting in a change in the loop filter bandwidth can be offset by changing the chargepump current in software.

VCO Bias Current

VCO bias current may be adjusted using bits VB1 to VB4 in the function register. Additional bias current will reduce spurious levels, but increase overall current consumption in the part. A bias value of 0x5 should ensure oscillation at most frequencies and supplies. Settings 0x0, 0xE ,and 0xF are not recommended. Setting 0x3 and Setting 0x4 are recommended under most conditions. Improved phase noise can be achieved for lower bias currents.

LOOP FILTER
The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop filter design is shown in Figure 29.

CHARGE PUMP OUT

VCO
04617-0-025

VOLTAGE REGULATORS
There are two band gap voltage regulators on the ADF7012 providing a stable 2.25 V internal supply: a 2.2 F capacitor (X5R, NP0) to ground at CREG1 and a 470 nF capacitor at CREG2 should be used to ensure stability. The internal reference ensures consistent performance over all supplies and reduces the current consumption of each of the blocks. The combination of regulators, band gap reference, and biasing typically consume 1.045 mA at 3.0 V and can be powered down by bringing the CE line low. The serial interface is supplied by Regulator 1, so powering down the CE line causes the contents of the registers to be lost. The CE line must be high and the regulators must be fully powered on to write to the serial interface. Regulator power-on time is typically 100 s and should be taken into account when writing to the ADF7012 after power-up. Alternatively, regulator status may be monitored at the MUXOUT pin once CE has been asserted, because MUXOUT defaults to the regulator ready signal. Once Regulator_ready is high, the regulator is powered up and the serial interface is active.

Figure 29.

In FSK, the loop should be designed so that the loop bandwidth (LBW) is a minimum of two to three times the data rate. Widening the LBW excessively reduces the time spent jumping between frequencies, but results in reduced spurious attenuation. See the section Tips on Designing the Loop Filter. For OOK/ASK systems, a wider loop bandwidth than for FSK systems is desirable. The sudden large transition between two power levels results in VCO pulling (VCO temporarily goes to incorrect frequency) and can cause a wider output spectrum. By widening the loop bandwidth a minimum of 10 data rate, VCO pulling is minimized because the loop settles quickly back to the correct frequency. The free design tool ADIsimPLL can be used to design loop filters for the ADI family of transmitters.

VOLTAGE-CONTROLLED OSCILLATOR (VCO)

The ADF7012 features an on-chip VCO with an external tank inductor, which is used to set the frequency range. The center frequency of oscillation is governed by the internal varactor capacitance and that of the external inductor combined with the bond-wire inductance. An approximation for this is given in the Equation 4. For a more accurate selection of the inductor, see the section Choosing the External Inductor Value.

FSK MODULATION
FSK modulation is performed internally in the PLL loop by switching the value of the N register based on the status of the TxDATA line. The TxDATA line is sampled at each cycle of the PFD block (every 1/FPFD seconds). When TxDATA makes a lowto-high transition, an N value representing the deviation frequency is added to the N value representing the center frequency. Immediately the loop begins to lock to the new frequency of FCENTER + FDEVIATION. Conversely, when TxDATA makes a high-to-low transition, the N value representing the deviation is subtracted from the PLL N value representing the center frequency and the loop transitions to FCENTER FDEVIATION.

FVCO =

2 ( LINT + LEXT ) (CVAR + CFIXED )

(4)

The varactor capacitance can be adjusted in software to increase the effective VCO range by writing to bits VA1 and VA2 in the R register. Under typical conditions, setting VA1 and VA2 high increases the center frequency by reducing the varactor capacitance by approximately 1.3 pF.

Rev. 0 | Page 13 of 28

ADF7012
For GFSK and GOOK, the incoming bit stream to be transmitted needs to be synchronized with an on-chip sampling clock which provides one sample per bit to the Gaussian FIR filter. To facilitate this, the sampling clock is routed to the TxCLK pin where data is fetched from the host microcontroller or microprocessor on the falling edge of TxCLK, and the data is sampled at the midpoint of each bit on TxCLKs rising edge. Inserting external RC LPFs on TxDATA and TxCLK lines creates smoother edge transitions and improves spurious performance. As an example, suitable components would be a 1 kV resistor and 10 nF capacitor for a data rate of 5 kbps.
I/O C INT FETCH FETCH FETCH FETCH TxDATA
04617-0-040

4R

PFD/ CHARGE PUMP

PA STAGE VCO

FSK DEVIATION FREQUENCY N FDEV +FDEV TxDATA FRACTIONAL-N INTEGER-N

Figure 30.

04617-0-026

THIRD-ORDER - MODULATOR

The deviation from the center frequency is set using bits D1 to D9 in the modulation register. The frequency deviation may be set in steps of

ADF7012
TxCLK

SAMPLE SAMPLE

SAMPLE

FSTEP ( Hz) =

FPFD 214 FPFD ModulationNumber 214

(5)

Figure 31. TxCLK/TxDATA Synchronization.

The deviation frequency is therefore

The number of steps between symbol 0 and symbol 1 is determined by the setting for the index counter. (6) The GFSK deviation is set up as

FDEVIATION ( Hz) =

where ModulationNumber is set by bits D1 to D9. The maximum data rate is a function of the PLL lock time (and the requirement on FSK spectrum). Because the PLL lock time is reduced by increasing the loop-filter bandwidth, highest data rates can be achieved for the wider loop filter bandwidths. The absolute maximum limit on loop filter bandwidth to ensure stability for a fractional-N PLL is FPFD/7. For a 20 MHz PFD frequency, the loop bandwidth could be as high as 2.85 MHz. FSK modulation is selected by setting bits S1 and S2 in the modulation register low.

GFSK DEVIATION ( Hz) =

FPFD 2 m 212

(7)

where m is the mod control (Bits MC1 to MC3 in the modulation register). The GFSK sampling clock samples data at the data rate:

DataRate (bps) =

FPFD DividerFactor IndexCounter

(8)

where DividerFactor can be bits D1 to D7, and IndexCounter can be bits IC1 and IC2 in the modulation register.

GFSK MODULATION
Gaussian Frequency Shift Keying, or GFSK, represents a filtered form of frequency shift keying. The data to be modulated to RF is prefiltered digitally using an finite impulse response filter (FIR). The filtered data is then used to modulate the sigmadelta fractional-N to generate spectrally-efficient FSK. FSK consists of a series of sharp transitions in frequency as the data is switched from one level to an other. The sharp switching generates higher frequency components at the output, resulting in a wider output spectrum. With GFSK, the sharp transitions are replaced with up to 128 smaller steps. The result is a gradual change in frequency. As a result, the higher frequency components are reduced and the spectrum occupied is reduced significantly. GFSK does require some additional design work as the data is only sampled once per bit, and so the choice of crystal is important to ensure the correct sampling clock is generated.

POWER AMPLIFIER
The output stage is based on a Class E amplifier design, with an open drain output switched by the VCO signal. The output control consists of six current mirrors operating as a programmable current source. To achieve maximum voltage swing, the RFOUT pin needs to be biased at DVDD. A single pull-up inductor to DVDD ensures a current supply to the output stage, PA biased to DVDD volts, and with the correct choice of value transforms the impedance. The output power can be adjusted by changing the value of bits P1 to P6. Typically, this is P1 to P6 output 20dBm at 0x0, and 13 dBm at 0x7E at 868MHz, with the optimum matching network.

Rev. 0 | Page 14 of 28

ADF7012
The nonlinear characteristic of the output stage results in an output spectrum containing harmonics of the fundamental, especially the third and fifth. To meet local regulations, a lowpass filter usually is required to filter these harmonics. The output stage can be powered down by setting Bit PD2 in the function register low.
POWER (dBm)

As is the case with GFSK, GOOK requires the bit stream applied at TxDATA to be synchronized with the sampling clock, TxCLK (see the GFSK Modulation section).
10 0 10 OOK 20 30 40 50 60 70 80 909.43
04617-0-043

GOOK MODULATION
Gaussian on-off keying (GOOK) represents a prefiltered form of OOK modulation. The usually sharp symbol transitions are replaced with smooth Gaussian-filtered transitions with the result being a reduction in frequency pulling of the VCO. Frequency pulling of the VCO in OOK mode can lead to a wider than desired bandwidth, especially if it is not possible to increase the loop filter bandwidth to > 300kHz. The GOOK sampling clock samples data at the data rate:
DataRate (bps) = FPFD DividerFactor IndexCounter

GOOK

910.43 FREQUENCY (MHz)

910.93

(9)

Figure 33. GOOK vs. OOK Frequency Spectra (Narrow-Band Measurement)

POWER (dBm)

Bits D1 to D6 represent the output power for the system for a positive data bit. Divider Factor = 0x3F represents the maximum possible deviation from PA at minimum to PA at maximum output. An index counter setting of 128 is recommended. Figure 32 shows the step response of the Gaussian FIR filter. An index counter of 16 is demonstrated for simplicity. While the pre-filter data would switch the PA directly from off to on with a low-to-high data transition, the filtered data gradually increases the PA output in discrete steps. This has the effect of making the output spectrum more compact.
PRE-FILTER DATA (0 TO 1 TRANSITION) PA SETTING 16 (MAX) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (PA OFF)

20 10 0 10 20 30 40 50 60 70 80 90 885.43 GOOK 910.43 FREQUENCY (MHz)

04617-0-044

OOK

935.93

Figure 34. GOOK vs. OOK Frequency Spectra (Wideband Measurement)

Figure 32. Varying PA Output for GOOK (Index Counter = 16).

Rev. 0 | Page 15 of 28

04617-0-041

DISCRETIZED FILTER OUTPUT

ADF7012
OUTPUT DIVIDER
An output divider is a programmable divider following the VCO in the PLL loop. It is useful when using the ADF7012 to generate frequencies of < 500 MHz.
REFERENCE DIVIDER PFD CP LOOP FILTER VCO OUTPUT DIVIDER 1/2/4/8 N PA
04617-0-042

Battery Voltage Read back

By setting MUXOUT to 1010 to 1101, the battery voltage can be estimated. The battery measuring circuit features a voltage divider and a comparator where the divided-down supply voltage is compared to the regulator voltage. Table 6.
MUXOUT 1010 1011 1100 1101 MUXOUT High DVDD > 3.25 V DVDD > 3.0 V DVDD > 2.75 V DVDD > 2.35 V MUXOUT Low DVDD < 3.25 V DVDD < 3.0 V DVDD < 2.75 V DVDD < 2.35 V

Figure 35. Output Divider Location in PLL.

The output divider may be used to reduce feedthrough of the VCO by amplifying only the VCO/2 component, restricting the VCO feedthrough to leakage. Because the divider is in loop, the N register values should be set up according to the usual formula. However, the VCO gain (KV) should be scaled according to the divider setting, as shown in the following example. Fout = 433 MHz, Fvco = 866 MHz, KV @ 868 MHz = 60 MHz/V Therefore, KV for loop filter design = 30 MHz/V. The divider value is set in the R register. Table 5.
OD1 0 0 1 1 OD2 0 1 0 1 Divider Status Divider off Divide by 2 Divide by 4 Divide by 8

The accuracy of the measurement is limited by the accuracy of the regulator voltage and also the internal resistor tolerances.

Regulator Ready
The regulator has a power-up time, dependant on process and the external capacitor. The regulator ready signal indicates that the regulator is fully powered, and that the serial interface is active. This is the default setting on power-up at MUXOUT.

Digital Lock Detect

Digital lock detect indicates that the status of the PLL loop. The PLL loop takes time to settle on power-up and when the frequency of the loop is changed by changing the N value. When lock detect is high, the PFD has counted a number of consecutive cycles where the phase error is < 15 ns. The lock detect precision bit in the function register determines whether this is 3 cycles (LDP = 0), or 5 cycles (LDP=1). It is recommended that LDP be set to 1. The lock detect is not completely accurate and goes high before the output has settled to exactly the correct frequency. In general, add 50% to the indicated lock time to obtain lock time to within 1 kHz. The lock detect signal can be used to decide when the power amplifier (PA) should be enabled.

MUXOUT MODES
The MUXOUT pin allows the user access to various internal signals in the transmitter, and provides information on the PLL lock status, the regulator, and the battery voltage. The MUXOUT is accessed by programming Bits M1 to M4 in the function register and observing the signal at the MUXOUT pin.

R Divider
MUXOUT provides the output of the R divider. This is a narrow pulsed digital signal at frequency FPFD. This signal may be used to check the operation of the crystal circuit and the R divider. R divider/2 is a buffered version of this signal at FPFD/2.

Rev. 0 | Page 16 of 28

ADF7012 THEORY OF OPERATION

CHOOSING THE EXTERNAL INDUCTOR VALUE
The ADF7012 allows operation at many different frequencies by choosing the external VCO inductor to give the correct output frequency. Figure 36 shows both the minimum and maximum frequency vs. the inductor value. These are measurements based on 0603 CS type inductors from Coilcraft, and are intended as guidelines in choosing the inductor because board layout and inductor type varies between applications. The inductor value should be chosen so it is between the minimum and maximum value.
1200 MIN (meas) 1100 1000
FREQUENCY (MHz)

Standard Crystal Values

Standard crystal values are 3.6864 MHz, 4 MHz, 4.096 MHz, 4.9152 MHz, 7.3728 MHz, 9.8304 MHz, 10 MHz, 11.0592 MHz, 12 MHz, and 14.4792 MHz. Crystals with these values are usually available in stock and cost less than crystals with nonstandard values.

Reference Spurious Levels

Reference spurious levels (spurs) occur at multiples of the PFD frequency. The reference spur closest to the carrier is usually highest with the spur further out being attenuated by the loop filter. The level of reference spur is lower for lower PFD frequencies. In designs with high output power where spurious levels are the main concern, a lower PFD frequency (<5 MHz) may be desirable.

MAX (meas) MIN (eqn) MAX (eqn)

900 800 700 600 500 400 300 0 5 10 15 20 INDUCTANCE (nH) 25 30

04617-0-031

Beat Note Spurs

These are spurs occurring for very small or very large values in the fractional register. These are quickly attenuated by the loop filter. Selection of the PFD therefore determines their location, and ensures that they have negligible effect on the transmitter spectrum.

Phase Noise
The phase noise of a frequency synthesizer improves by 3dB for every doubling of the PFD frequency. Because ACP is related to the phase noise, the PFD may be increased to reduce the ACP in the system. PFD frequencies of < 5MHz typically deliver sufficient phase noise performance for most systems.

35

Figure 36. Output Frequency vs. External Inductor Value Ibias = 2.0 mA.

For frequencies between 270 MHz and 550 MHz, it is recommended to operate the VCO at twice the desired output frequency and use the divide-by-2 option. This ensures reliable operation over temperature and supply. For frequencies between 130 MHz and 270 MHz, it is recommended to operate the VCO at four times the desired output frequency and use the divide-by-4 option. For frequencies below 130 MHz, it is best to use the divide-by-8 option. It is not necessary to use the VCO divider for frequencies above 550 MHz. ADIsimPLL is a PLL design tool which can perform the frequency calculations for the ADF7012, and is available at www.analog.com/pll.

Deviation Frequency
The deviation frequency is adjustable in steps of

FSTEP ( Hz) =

FPFD 214

(10)

To get the exact deviation frequency required, ensure FSTEP is a factor of the desired deviation.

TIPS ON DESIGNING THE LOOP FILTER

The loop filter design is crucial in ensuring stable operation of the transmitter, meeting Adjacent Channel Power (ACP) specifications, and meeting spurious requirements for the relevant regulations. ADIsimPLL is a free tool available to aid the design of loop filters. The user enters the desired frequency range, the reference crystal and PFD values, and the desired loop bandwidth. ADIsimPLL gives a good starting point for the filter, and the filter can be further optimized based on the criteria below.

CHOOSING THE CRYSTAL/PFD VALUE

The choice of crystal value is an important one. The PFD frequency must be the same as the crystal value or an integer division of it. The PFD determines the phase noise, spurious levels and location, deviation frequency, and the data rate in the case of GFSK. The following sections describe some factors that should be considered when choosing the crystal value.

Rev. 0 | Page 17 of 28

ADF7012
Setting Tuning Sensitivity Value
The tuning sensitivity or kV is usually denoted in MHz/V and is required for the loop filter design. It refers to the amount that a change of a volt in the voltage applied to VCOIN pin, changes the output frequency. Typical data for the ADF7012 over a frequency range is shown.
120

PA MATCHING
The ADF7012 exhibits optimum performance in terms of transmit power and current consumption only if the RF output port is properly matched to the antenna impedance. ZOPT_PA depends primarily on the required output power, and the frequency range. Selecting the optimum ZOPT_PA helps to minimize the current consumption. This data sheet contains a number of matching networks for common frequency bands. Under certain conditions it is recommended to obtain a suitable ZOPT_PA value by means of a load-pull measurement.
DVDD

100

80
KV (MHz/V)

60

40 RFOUT ANTENNA LPF ZOPT_PA

04716-0-033

004617-0-032

20

PA

0 200

300

400

500 600 700 800 FREQUENCY (MHz)

900

1000

1100

Figure 37. kV vs. VCO Frequency

Figure 38. ADF7012 with Harmonic Filter

Charge-Pump Current
The charge-pump current allows the loop filter bandwidth to be changed using the registers. The loop bandwidth reduces as the charge pump current is reduced and vice versa.

Selecting Loop Filter Bandwidth

Data Rate The loop filter bandwidth should usually be at two to three times the data rate. This ensures that the PLL has ample time to jump between the mark and space frequencies. ACP In the case where the ACP specifications are difficult to meet, the loop filter bandwidth can be reduced further to reduce the phase noise at the adjacent channel. The filter rolls off at 20 dB per decade. Spurious Levels In the case where the output power is quite high, a reduced loop filter bandwidth reduces the spurious levels even further, and provides additional margin on the specification. The following sections provide examples of loop filter designs for typical applications in specific frequencies.

The impedance matching values provided in the next section are for 50 environments. An additional matching network may be required after the harmonic filter to match to the antenna impedance. This can be incorporated into the filter design itself in order to reduce external components.

TRANSMIT PROTOCOL AND CODING CONSIDERATIONS

PREAMBLE SYNC WORD ID FIELD DATA FIELD CRC
04617-0-034

Figure 39. Typical Format of a Transmit Protocol

A dc-free preamble pattern such as 10101010 is recommended for FSK/ASK/OOK demodulation. Preamble patterns with longer run-length constraints such as 11001100. can also be used. However, this can result in a longer synchronization time of the received bit stream in the chosen receiver.

Rev. 0 | Page 18 of 28

ADF7012 APPLICATION EXAMPLES

R2 C1 VDD C5+ 10F C5 2.2F C6 2.2F C5 100pF
1

C2 R1

C3

VDD

U1 ADF7012
DVDD CREG1 CPOUT TxDATA TxCLK MUXOUT CREG2 RSET AGND DVDD RFOUT RFGND VCOIN CVCO L2 L1

CREG2
24

C10 470nF

C11 0.22F

CREG1
2

23

R9 3.6k

22

J1

TxDATA

1k 1k 1k MUXOUT Y1 C7 27pF C8 27pF

TxDATA TxCLK

C12 100pF
21

C13 2.2F

VDD

TxCLK

20

L1

L2 C15

C14

LF1

LF2

J4

MUXOUT 6

19

CF1

CF2

CF2

DGND

18

OSC1

OSC1

17

J2

C9

OSC2

OSC2 CLKOUT CLK

16

1k
CLKOUT J33 R3 1k R4 1k R5 1k CLK CLK

L3 CLKOUT
10 15

11

CE

14

VDD

9 PIN D-TYPE PLUG

J35

DATA

DATA

12

DATA

LE

13

CE LE LE

J37 J36 J38

TxDATA R6 1k R7 1k R8 1k MUXOUT CLK LE VDD

J51 J53 J55 J57 J59

J52 J54 J55 J58 J510

TxCLK CLKOUT DATA CE

04617-0-035

10 PIN HEADER (5X2)

Figure 40. Applications Diagrams with Harmonic Filter

Rev. 0 | Page 19 of 28

ADF7012
315 MHZ OPERATION
The recommendations here are guidelines only. The design should be subject to internal testing prior to FCC site testing. Matching components need to be adjusted for board layout. The FCC standard 15.231 regulates operation in the band from 260MHz to 470MHz in the US. This is used generally in the transmission of RF control signals, such as in a satellitedecoder remote control, or remote keyless entry system. The band cannot be used to send any continuous signal. The maximum output power allowed is governed by the duty cycle of the system. A typical design example for a remote control is shown next.

Bias Current
Because low current is desired, a 2.0 mA VCO bias can be used. Additional bias current reduces any spur, but increases current consumption. The PA bias can be set to 5.5 mA and achieve 0 dBm.

Loop Filter Bandwidth

The loop filter is designed with ADIsimPLL Version 2.5. The loop bandwidth design is straightforward because the 20 dB bandwidth is generally of the order of >400 kHz (0.25% of center frequency). A loop bandwidth of close to 100 kHz strikes a good balance between lock time and spurious suppression. If it is found that pulling of the VCO is more than desired in OOK mode, the bandwidth could be increased.

Design Criteria
315 MHz center frequency FSK/OOK modulation 1 mW output power House range Meets FCC 15.231 The main requirements in the design of this remote are a long battery life and sufficient range. It is possible to adjust the output power of the ADF7012 to increase the range depending on the antenna performance. The center frequency is 315 MHz. Because the ADF7012 VCO is not recommended for operation in fundamental mode for frequencies below 400 MHz, the VCO needs to operate at 630 MHz. Figure 36 (Output Frequency vs. External Inductor Value) implies an inductor value of 7.6 nH or close to this. The chip inductor chosen = 7.5 nH (0402CS-7N5 from Coilcraft). Coil inductors are recommended to provide sufficient Q for oscillation.

Design of Harmonic Filter

The main requirement of the harmonic filter should ensure that the third harmonic level is < 41.5 dBm. A fifth-order Chebyshev filter is recommended to achieve this, and a suggested starting point is given next. The Pi format is chosen to minimize the more expensive inductors.

Component ValuesCrystal: 3.6864MHz

Loop Filter ICP 0.866 mA LBW 100 kHz C1 680 pF C2 12 nF C3 220 pF R1 1.1 kV R2 3 kV Matching L1 56 nH L2 1 nF C14 Short C15 Open Harmonic Filter L4 22 nH L5 22 nH CF1 3.3 pF CF2 8.2 pF CF3 3.3 pF

Crystal and PFD

Phase noise requirements are not excessive as the adjacent channel power requirement is 20 dB. The PFD is chosen so as to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. PFD = 3.6864 MHz Power-Up Time 1.6ms. Figure 10 shows a typical power-on time for a 4 MHz crystal.

N-Divider
The N Divider is determined as being: Nint = 85 Nfrac = (1850)/4096 VCO divide-by-2 is enabled

Deviation
The deviation is set to 50 kHz so as to accommodate a simple receiver architecture. The modulation steps available are in 3.6864 MHz/214 : Modulation steps = 225 Hz Modulation number = 50 kHz/225 Hz = 222
Rev. 0 | Page 20 of 28

ADF7012
433 MHZ OPERATION
The recommendations here are guidelines only. The design should be subject to internal testing prior to ETSI site testing. Matching components need to be adjusted for board layout. The ETSI standard EN 300-220 governs operation in the 433.050 MHz to 434.790 MHz band. For many systems, 10% duty is sufficient for the transmitter to output 10 dBm.

Loop Filter Bandwidth

The loop filter is designed with ADIsimPLL Version 2.5. The loop bandwidth design requires that the channel power be < 36 dBm at 870 kHz from the center. A loop bandwidth of close to 160 kHz strikes a good balance between lock time for data rates, including 32 kbps and spurious suppression. If it is found that pulling of the VCO is more than desired in OOK mode, the bandwidth could be increased.

Design Criteria
433.92 MHz center frequency FSK modulation 10 mW output power 200 m range Meets ETSI 300-220 The main requirement in the design of this remote is a long battery life and sufficient range. It is possible to adjust the output power of the ADF7012 to increase the range depending on the antenna performance. The center frequency is 433.92 MHz. It is possible to operate the VCO at this frequency. Figure 36 shows the inductor value vs. center frequency. The inductor chosen is 22 nH. Coilcraft inductors such as 0603-CS-22NXJBU are recommended.

Design of Harmonic Filter

The main requirement of the harmonic filter should ensure that the third harmonic level is < 30 dBm. A fifth-order Chebyshev filter is recommended to achieve this, and a suggested starting point is given next. The Pi format is chosen to minimize the more expensive inductors.

Component ValuesCrystal: 4.9152 MHz

Loop Filter Icp 2.0 mA LBW 100 kHz C1 680 pF C2 12 nF C3 270 pF R1 910 V R2 3.3 kV Matching L1 22 nH L2 10 pF C14 Short C15 Open Harmonic Filter L4 22 nH L5 22 nH CF1 3.3 pF CF2 8.2 pF CF3 3.3 pF

Crystal and PFD

The phase noise requirement is such to ensure the power at the edge of the band is < 36 dBm. The PFD is chosen so as to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. PFD = 4.9152 MHz Power-Up Time 1.6 ms. Figure 10 shows a typical power-up time for a 4 MHz crystal.

N-Divider
The N Divider is determined as being: Nint = 88 Nfrac = (1152)/4096 VCO divide-by-2 is not enabled

Deviation
The deviation is set to 50 kHz so as to accommodate a simple receiver architecture. The modulation steps available are in 4.9152 MHz/214 : Modulation steps = 300 Hz Modulation number = 50 kHz/300Hz = 167

Bias Current
Because low current is desired, a 2.0 mA VCO bias can be used. Additional bias current reduces any spurious, but increases current consumption. The PA bias can be set to 5.5 mA and achieve 10 dBm.

Rev. 0 | Page 21 of 28

ADF7012
868 MHZ OPERATION
The recommendations here are guidelines only. The design should be subject to internal testing prior to ETSI site testing. Matching components need to be adjusted for board layout. The ETSI standard EN 300-220 governs operation in the 868 MHz to 870MHz band. The band is broken down into several subbands each having a different duty cycle and output power requirement. Narrowband operation is possible in the 50kHz channels, but both the output power and data rate are limited by the 36 dBm adjacent channel power specification. There are many different applications in this band, including remote controls for security, sensor interrogation, metering and home control. The modulation steps available are in 4.9152 MHz/214 : Modulation steps = 300 Hz Modulation number = 19.2 kHz/300 Hz = 64.

Bias Current
Because low current is desired, a 2.5 mA VCO bias can be used. Additional bias current reduces any spurious, but increases current consumption. A 2.5 mA bias current gives the best spurious vs. phase noise trade-off. The PA bias should be set to 7.5 mA to achieve 12 dBm.

Loop Filter Bandwidth

The loop filter is designed with ADIsimPLL Version 2.5. The loop bandwidth design requires that the channel power be < 36 dBm at 250 kHz from the center. A loop bandwidth of close to <60 kHz is required to bring the phase noise at the edge of the band sufficiently low to meet the ACP specification. This represents a compromise between the data rate requirement and the phase noise requirement.

Design Criteria
868.95 MHz center frequency (band 868.7MHz 869.2 MHz) FSK modulation 12 dBm output power 300 m range Meets ETSI 300-220 38.4 kbps data rate The design challenge is to enable the part to operate in this particular subband and meet the ACP requirement 250 kHz away from the center. The center frequency is 868.95 MHz. It is possible to operate the VCO at this frequency. Figure 31 shows the inductor value vs. center frequency. The inductor chosen is 1.9 nH. Coilcraft inductors such as 0402-CS-1N9XJBU are recommended.

Design of Harmonic Filter

The main requirement of the harmonic filter should ensure that the second and third harmonic levels are < 30 dBm. A fifthorder Chebyshev filter is recommended to achieve this, and a suggested starting point is given next. The Pi format is chosen to minimize the more expensive inductors.

Component ValuesCrystal: 4.9152 MHz

Loop Filter Icp 1.44 mA LBW 60 kHz C1 1.5 nF C2 22 nF C3 560 pF R1 390 V R2 910 V Matching L1 27 nH L2 6.2 nH C14 470 pF C15 Open Harmonic Filter L4 8.2 nH L5 8.2 nH CF1 4.7 pF CF2 6.8 pF CF3 4.7 pF

Crystal and PFD

The phase noise requirement is such to ensure the power at the edge of the band is < 36 dBm. This requires close to 100 dBc/Hz phase noise at the edge of the band. The PFD is chosen so as to minimize spurious levels (beat note and reference), and to ensure a quick crystal power-up time. A PFD of < 6 MHz places the largest PFD spur at a frequency of greater than 862 MHz, and so reduces the requirement on the spur level to 36 dBm instead of 54 dBm. PFD = 4.9152 MHz Power Up-Time 1.6 ms. Figure 10 shows a typical power-on time for a 4MHz crystal.

N-Divider
The N divider is determined as being: Nint = 176 Nfrac = (3229)/4096 VCO divide-by-2 is not enabled.

Deviation
The deviation is set to 19.2 kHz so as to accommodate a simple receiver architecture and also ensure that the modulation spectrum is narrow enough to meet the adjacent channel power (ACP) requirements.
Rev. 0 | Page 22 of 28

ADF7012
915 MHZ OPERATION
The recommendations here are guidelines only. The design should be subject to internal testing prior to FCC site testing. Matching components need to be adjusted for board layout. FCC 15.247 and FCC 15.249 are the main regulations governing operation in the 902 MHz to 928 MHz Band. FCC 15.247 requires some form of spectral spreading. Typically, the ADF7012 would be used in conjunction with the frequency hopping spread spectrum (FHSS) or it may be used in conjunction with the digital modulation standard which requires large deviation frequencies. Output power of < 1 W is tolerated on certain spreading conditions. Compliance with FCC 15.249 limits the output power to 1.5 dBm, but does not require spreading. There are many different applications in this band, including remote controls for security, sensor interrogation, metering, and home control.

Deviation
The deviation is set to 19.2 kHz so as to accommodate a simple receiver architecture, and also to ensure the available spectrum is used efficiently. The modulation steps available are in 10 MHz/214 : Modulation steps = 610 Hz Modulation number = 19.2 kHz/610 Hz = 31.

Bias Current
Because low current is desired, a 3 mA VCO bias can be used and still ensure oscillation at 928 MHz. Additional bias current reduces any spurious noise, but increases current consumption. A 3 mA bias current gives the best spurious vs. phase noise trade-off. The PA bias should be set to 5.5 mA to achieve 10 dBm power.

Design Criteria
915.2MHz center frequency FSK modulation 10 dBm output power 200 m range Meets FCC 15.247 38.4 kbps data rate The center frequency is 915.2 MHz. It is possible to operate the VCO at this frequency. Figure 36 shows the inductor value vs. center frequency. The inductor chosen is 1.6 nH. Coilcraft inductors such as 0603-CS-1N6XJBU are recommended. Additional hopping frequencies can easily be generated by changing the N value. Crystal and PFD The phase noise requirement is such to ensure that the 20 dB bandwidth requirements are met. These are dependant on the channel spacing chosen. A typical channel spacing would be 400 kHz, which would allow 50 channels in 20 MHz and enable the design to avoid the edges of the band. The PFD is chosen so as to minimize spurious levels. There are beat note spurious levels at 910 MHz and 920 MHz, but the level is usually significantly less than the modulation power. They are also attenuated quickly by the loop filter to ensure a quick crystal power-up time. PFD = 10 MHz Power-Up Time 1.8 ms (approximately). Figure 10 shows a typical power-on time for a 4 MHz crystal.

Loop Filter Bandwidth

The loop filter is designed with ADIsimPLL Version 2.5. A data rate of 170 kHz is chosen, which allows for data rates of > 38.4 kbps. It also attenuates the beat note spurs quickly to ensure they have no effect on system performance.

Design of Harmonic Filter

The main requirement of the harmonic filter should ensure that the third harmonic level is < 41.5 dBm. A fifth-order Chebyshev filter is recommended to achieve this, and a suggested starting point is given next. The Pi format is chosen to minimize the number of inductors in the system.

Component ValuesCrystal: 10 MHz

Loop Filter Icp 1.44 mA LBW 170 kHz C1 470 pF C2 12 nF C3 120 pF R1 470 V R2 1.8 kV Matching L1 27 nH L2 6.2 nH C14 470 pF C15 Open Harmonic Filter L4 8.2 nH L5 8.2 nH CF1 4.7 pF CF2 6.8 pF CF3 4.7 pF

N-Divider
The N divider is determined as being: Nint = 91 Nfrac = (2130)/4096 VCO divide-by-2 is not enabled

Rev. 0 | Page 23 of 28

ADF7012 REGISTER DESCRIPTIONS

R REGISTER

OUTPUT VCO DIVIDER ADJUST

CLOCK OUT DIVIDER

CRYSTAL DOUBLER

4-BIT R DIVIDER

11-BIT FREQUENCY ERROR CORRECTION

DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C2 (0) DB1

D1 CRYSTAL DOUBLER 0 CRYSTAL DOUBLER OFF 1 CRYSTAL DOUBLER ON

F11 0 0 0 0 0 1 1 . 1 1

....... ....... ....... ....... ....... ....... ....... ....... ....... ....... .......

F3 1 1 . 0 0 1 1 . 0 0

F2 0 0 . 0 0 1 1 . 0 0

F1 0 1 . 1 0 1 0 . 1 0

F-COUNTER OFFSET +1023 +1022 . +1 +0 1 0 1 1023 1024

OD2 0 0 1 1

OD1 0 1 0 1

OUTPUT DIVIDER DISABLED DIVIDE BY 2 DIVIDE BY 4 DIVIDE BY 8

X1 XOEB 0 XTAL OSCILLATOR ON (DEFAULT) 1 XTAL OSCILLATOR OFF

VA2 0 0 1 1

VA1 0 1 0 1

VCO ADJUST NO VCO ADJUSTMENT (FCENTER (1 f)) (FCENTER (2 f)) (FCENTER (3 f))

e.g., F-COUNTER OFFSET = 1, FRACTIONAL OFFSET = 1/215

CL4 0 0 0 0 . . . 1 1

CL3 0 0 0 1 . . . 1 1

CL2 0 1 1 0 . . . 1 1

CL1 1 0 1 0 . . . 0 1

CLKOUT DIVIDE RATIO 2 4 6 8 . 16 (DEFAULT) . 28 30

Figure 41.

Rev. 0 | Page 24 of 28

04617-0-027

RL4 0 0 0 0 . . . 1 1 1 1

RL3 0 0 0 1 . . . 1 1 1 1

RL2 0 1 1 0 . . . 0 0 1 1

RL1 1 0 1 0 . . . 0 1 0 1

RF R COUNTER DIVIDE RATIO 1 2 3 4 . . . 12 13 14 15

C1 (0) DB0

OD2

OD1

VA2

VA1

CL4

CL3

CL2

CL1

F11

F10

D1

R4

R3

R2

R1

X1

F9

F8

F7

F6

F5

F4

F3

F2

F1

ADDRESS BITS

XOEB

ADF7012
N-COUNTER LATCH

DB22 PRESCALER

8-BIT INTEGER-N

12-BIT FRACTIONAL-N

DB23

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

C2 (0) DB1

M12 0 0 0 . . . 1 1 1 1

M11 0 0 0 . . . 1 1 1 1

M10 ....... 0 0 0 . . . 1 1 1 1 ....... ....... ....... ....... ....... ....... ....... ....... ....... .......

M3 0 0 0 . . . 1 1 1 1

M2 0 0 1 . . . 0 0 1 1

M1 0 1 0 . . . 0 1 0 1

MODULUS DIVIDE RATIO 0 1 2 . . . 4092 4093 4094 4095

e.g., SETTING F = 0 IN FSK MODE TURNS ON THE - WHILE THE PLL IS AN INTEGER VALUE

N8 0 0 0 . . . 1 1

N7 0 0 0 . . . 1 1

N6 0 0 0 . . . 1 1

N5 0 0 0 . . . 1 1

N4 0 0 0 . . . 1 1

N3 0 0 0 . . . 1 1

N2 0 0 1 . . . 1 1

N1 0 1 0 . . . 0 1

N-COUNTER DIVIDE RATIO 1 2 3 . . . 254 255

e.g., MODULUS DIVIDE RATIO = 2048 - > 1/2

C1 (1) DB0
04617-0-028

M12

M11

M10

M9

M8

M7

M6

M5

M4

M3

M2

P1 PRESCALER 0 4/5 1 8/9

THE N-VALUE CHOSEN IS A MINIMUM OF P2 + 3P + 3. FOR PRESCALER 8/9 THIS MEANS A MINIMUM N-DIVIDE OF 91.

Figure 42.

Rev. 0 | Page 25 of 28

M1

N8

N7

N6

N5

N4

N3

N2

N1

P1

ADDRESS BITS

ADF7012
MODULATION REGISTER

INDEX COUNTER

MOD CONTROL DB3 DB2

TEST BITS

GFSK MOD CONTROL

MODULATION DEVIATION

POWER AMPLIFIER

DB31

DB30

DB29

DB28

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

C2 (1) DB1

MUST BE LOW

G1 GAUSSIAN OOK 0 ON 1 OFF

S2 0 0 1 1

S1 0 1 0 1

MODULATION SCHEME FSK GFSK ASK OOK

IF AMPLITUDE SHIFT KEYING SELECTED, TxDATA = 0 D6 0 . 0 0 . . 1 . . . . . . . 1 . . . . . . . 1 D2 X 0 0 1 . . 1 D1 X 0 1 0 . . 1

POWER AMPLIFIER OUTPUT LEVEL P6 0 0 0 0 . . 1 . . . . . . . 1 . . . . . . . 1 P2 X 0 1 1 . . 1 P1 X 1 0 1 . . 1

PA OFF 16.0dBm 1/31 * 14dBm 2/31 * 14dBm . . 14dBm

PA OFF 16.0dBm 1/31 * 14dBm 2/31 * 14dBm . . 13dBm

IF FREQUENCY SHIFT KEYING SELECTED D9 0 0 0 0 . 1 ....... ....... ....... ....... ....... ....... ....... D3 0 0 0 0 . 1 D2 0 0 1 1 . 1 D1 0 1 0 1 . . F DEVIATION PLL MODE 1 FSTEP 2 FSTEP 3 FSTEP ....... 511 FSTEP

FSTEP = FPFD /214

IF GAUSSIAN FREQUENCY SHIFT KEYING SELECTED IC2 0 0 1 1 MC3 0 0 . 1 IC1 0 1 0 1 MC2 0 0 . 1 INDEX COUNTER 16 32 64 128 MC1 0 1 . 1 GFSK MOD CONTROL 0 1 . 7 D7 0 0 0 0 . 1... ....... ....... ....... ....... ....... ....... ....... D3 0 0 0 0 . 1 D2 0 0 1 1 . 1 D1 0 1 0 1 . 1 DIVIDER FACTOR 0 1 2 3 ....... 127

C1 (0) DB0
04617-0-029

MC2

MC3

MC1

IC2

IC1

G1

D9

D8

D7

D6

D5

D4

D3

D2

D1

P6

P5

P4

P3

P2

P1

S2

Figure 43.

Rev. 0 | Page 26 of 28

S1

ADDRESS BITS

GOOK

ADF7012
FUNCTION REGISTER
DATA INVERT CLKOUT ENABLE PA ENABLE PLL ENABLE

LD PRECISION

SD TEST MODES
DB31 DB30 DB29 DB28 DB27

PLL TEST MODES

DB26 DB25 DB24 DB23 DB22

PA BIAS

VCO BIAS

MUXOUT

BLEED CHARGE CURRENT PUMP

DB9 DB8 DB7 DB6

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB5

DB4

DB3

DB2

C2 (1) DB1

I1 0 1

DATA INVERT DATA DATA

PA3 0 0 0 . . 1

PA2 0 0 1 . . 1

PA1 0 1 0 . . 1

PA BIAS 5A 6A 7A . . 12A

CP4 0 1

BLEED DOWN BLEED OFF BLEED ON

PD1 0 1

PLL ENABLE PLL OFF PLL ON

CP3 0 1

BLEED UP BLEED OFF BLEED ON

PD2 0 1

PA ENABLE PA OFF PA ON

CP2 0 0 1 1

CP1 0 1 0 1

CHARGE PUMP CURRENT 0.3mA 0.9mA 1.5mA 2.1mA

VB4 0 0 . 1

VB3 0 0 . 1

VB2 0 1 . 1

VB1 1 0 . 1

VCO BIAS CURRENT 0.5mA 1mA . 8mA

VD1 0 1

VCO DISABLE VCO ON VCO OFF

PD3 0 1

CLKOUT CLKOUT OFF CLKOUT ON

Figure 44.

Rev. 0 | Page 27 of 28

04617-0-030

M4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

M3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

M2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

M1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

MUXOUT LOGIC LOW LOGIC HIGH INVALID MODE DO NOT USE REGULATOR READY (DEFAULT) DIGITAL LOCK DETECT ANALOG LOCK DETECT R DIVIDER/2 OUTPUT N DIVIDER/2 OUTPUT RF R DIVIDER OUTPUT DATA RATE BATTERY MEASURE IS > 3.25V BATTERY MEASURE IS > 3V BATTERY MEASURE IS > 2.75V BATTERY MEASURE IS > 2.35V NORMAL TEST MODES - TEST MODES

C1 (1) DB0

PA3

PA2

PA1

VB4

VB3

VB2

VB1

VD1

PD3

PD2

PD1

CP4

CP3

CP2

CP1

LD1

ST4

ST3

ST2

ST1

PT5

PT4

PT3

PT2

PT1

M4

M3

M2

M1

I1

ADDRESS BITS

VCO DISABLE

ADF7012 OUTLINE DIMENSIONS

7.90 7.80 7.70

24

13

4.50 4.40 4.30 6.40 BSC

1 12

PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153AD 1.20 MAX

SEATING PLANE

0.20 0.09

8 0

0.75 0.60 0.45

Figure 45. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24)

ORDERING GUIDE
Model ADF7012BRU ADF7012BRU-REEL ADF7012BRU-REEL7 EVAL-ADF7012EB1 EVAL-ADF7012EB2 EVAL-ADF7012EB3 EVAL-ADF7012EB4 EVAL-ADF7012EB5 Temperature Range 40C to +85C 40C to +85C 40C to +85C Package Description TSSOP TSSOP, 13REEL TSSOP, 7 REEL Evaluation Board Evaluation Board Evaluation Board Evaluation Board Evaluation Board Package Option RU-24 RU-24 RU-24 Frequency Range 50 MHz to 1 GHz 50 MHz to 1 GHz 50 MHz to 1 GHz 902 MHz to 928 MHz 860 MHz to 880 MHz 418 MHz to 435 MHz 310 MHz to 330 MHz 50 MHz to 1 GHz

2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04617010/04(0)

Rev. 0 | Page 28 of 28