Institut fr Integrierte Systeme u Integrated Systems Laboratory

Analog Integrated Circuits Exercise 2: Introduction to Cadence

Luca Bettini J61, Ren Blattmann J64.2, Schekeb Fateh J64.2 e Hand out: 14.10.2011 Hand in: 28.10.2011

The exercise takes place in room ETZ D96. The exercise starts at 13:15 and ends at 15:00. For the course attendance certicate (testat), solutions to all problems have to be handed in by 28th October.

1 Introduction
Analog integrated circuit design is usually done by paper and pencil with very simple models in a rst stage. In a second stage, the behavior of the circuit is veried by a simulation software tool with more precise models and the circuit is then modied based on these results. However, the results from the simulation software should more or less agree with the considerations made in the rst stage, when all components have been dimensioned. Currently, the most sophisticated and wide-spread software package for the analysis and synthesis of analog and digital integrated circuits is the Design Framework II (DFII) of Cadence Inc., which is referred to as Cadence in the following. The purpose of this exercise is to become familiar with the schematic entry and simulation environment of Cadence. You are going to perform the most important analyses on the basis of simple analog integrated circuits. Note that the material conveyed in this exercise forms the basis for all subsequent labs and is a prerequisite for their successful completion. We therefore suggest that you keep this exercise within reach in the future labs.

2 Getting Started
Open a terminal session and enter the following commands: cd mkdir uebung2 cd uebung2 icdesign ams-hk3.70 -tech c35b3 & The last command starts Cadence with the conguration for the c35b3 process, a 0.35m 2P3M CMOS process of the Austrian chip foundry AMS (Austria Micro Systems, see http://www.ams.co.at).

The nominal supply voltage for this process is 3.3 V. The process specic parameters for Cadence are provided by the chip foundry as design kits. However, AMS calls its design kit AMS Hit Kit. When starting Cadence, multiple windows appear on the screen. Fig. 1 shows the Command Interpreter Window (CIW) of Cadence. In this window, tools and functions may be invoked either through the menu or by typing a SKILL command in the command line. SKILL is a Cadence proprietary dialect of the programming language LISP. Note that the tools display important messages in the area above the command line! Therefore it is a good idea to enlarge this window a litte bit.

Figure 1: Command Interpreter Window (CIW). The window of Fig. 2 entitled Library Manager is Cadences le manager that manages libraries and cells. The Library Manager may be invoked from the Command Interpreter Window by clicking Tools.Library Manager 1 . The window entitled Whats New in 4.4.6 informs about changes of the DFII environment. If needed the window can be re-accessed from the Command Interpreter Window with File.Whats New. You may close it for the moment.

3 The Library and Cell Hierarchy

Have a look at Fig. 2: the column to the far right shows the different views of the transistor nmos4. At the moment only the schematic view, needed to draw a circuit representation, and maybe the layout view with the physical layout of the transistor are relevant to us. Generally, circuits may become large and complex. Therefore, it makes sense to sum up self-contained parts of a circuit as blocks - especially if these blocks are to be used more than once in the overall circuit. A hierarchy level above, only a graphical representation of the block is necessary, which is called the symbol view. This concept allows to structure circuits in a hierarchical way. Different cells may be arranged in categories for the sake of more clarity. The cells that have not been assigned to a certain category appear in the category Uncategorized. The category display may be enabled and disabled with the tick box Show Categories in the upper left corner of the Library Manager. Note that a cell may belong to more than one category. Therefore, the category does not constitute a hierarchical structure. Cells and categories are assigned to a library. At the moment, the libraries analogLib and PRIMLIB
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Command1.Command2 means you should click Command2 in the menu Command1.

Figure 2: Library Manager.

are relevant to us. PRIMLIB is an AMS library and contains the components (MOSFETs, resistors, capacitors, etc.) of the selected technology. Generate your own library for this exercise by clicking File.New.Library in the Library Manager. Enter MyLibrary for Name and click OK. A technology le has to be assigned to your library. Accept the default Attach to an existing techfile and select TECH C35B3 as Technology Library in the subsequent dialog box. The generated library MyLibrary should now appear in the Library Manager. Now generate a cell called nmos dc and its schematic view. To do this, rst select MyLibrary in the Library Manager. Then click File.New.Cell View and choose nmos dc for Cell Name, schematic for View Name, and Composer-Schematic for Tool. After clicking OK the schematic entry window pops up and we are ready to assemble our circuit.

4 Schematic Entry in Virtuoso Composer

The composer serves as graphical schematic entry tool. This section introduces the most relevant commands by means of a simple example. If you followed the tutorial correctly so far, then you should have the window displayed in Fig. 3 on your 3

Figure 3: Composer Window.

screen now. On the left, you can see a column of buttons for frequently used commands. Moving the mouse cursor over a button allows you to get a short help text such as Check and Save for the topmost button. Further help for the active command is provided in the status line of the composer window, where at the moment AMS HIT - KIT : 3.70 is displayed. By pressing ESC you can terminate the active command before completion2 . The schematic of your rst circuit is depicted in Fig. 4. At rst, place the transistor by clicking Add.Instance. In the dialog box, you can specify the wanted component either by lling in the elds Library, Cell, and View by hand, or by using the browser. Now press Browse and look for nmos4 in the library PRIMLIB and select the symbol view. Move the mouse cursor over the composer window. The mouse cursor now shows the symbol of the NMOS transistor. Before you place the transistor, enter 0.7u for Width and 0.35u for Length in the Add Instance window. Use the same value for WidthStripe as for Width. Note that no space is allowed between the value and the factor u! Before you place the component it may be rotated in 90 steps by pressing the right mouse button. You may now nally place the transistor with the left mouse button.
Since uncompleted commands are stacked a stack overow may occur. Press ESC a couple of times in such situations possibly in different windows - in order to clear the stack. Nest Limit and the number of Undos may be set in the Command Interpreter Window in Options.User Preferences.
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Figure 4: Schematic for the NMOS DC characteristics.

In order to edit the parameters select the component with the left mouse button. Then either click on the Property button in the button column on the left or choose Edit.Properties.Objects from the menu. As a shortcut you may also just press the key q. For working efciently with Cadence it pays to memorize the shortcuts of the most often used commands. The shortcuts are shown in the pertaining q . Have a look at the menus Edit and Add to get an overview menu entries, e.g. Objects... of the most important commands for drawing a circuit! From the analogLib, place the ground connection gnd and a voltage source vdc for both the gate and drain voltage according to Fig. 4. Use the symbol view here as well. For both voltage sources enter 3 V for the DC voltage. Note: the gnd connection is absolutely needed by the simulator in order to dene a reference potential and therefore has to be included in each circuit!!! The ports of the components may be connected with the command Add.Wire (narrow). If this command is active, the composer suggests a connection with the symbol near the mouse cursor. Pressing s (for snap) accepts the proposal and allows to connect the various components in a convenient manner. Usually a net is assigned a name automatically, e.g. net2. With the button Wire Name or the menu command Add.Wire Name you may assign names explicitly, e.g. vds and vgs as in Fig. 4. Enter the desired label in the Names eld of the corresponding dialog box and position the label on the wire you would like to name. Like wires, components are designated automatically as well, e.g. V0 in case of a voltage source. To change the name select the corresponding component and press q. You may now change the eld Instance Name accordingly. Now change all the net and instance names in your circuit according to Fig. 4 and save your design with Design.Check and Save.

5 Simulation with Analog Environment

The circuit may now be simulated directly from the Composer Window. There are different kinds of simulations. One of them is the DC analysis. The DC analysis returns the DC operating points of the circuit components. Additionally, a parameter such as the voltage of a voltage source or the temperature may be varied to determine the DC operating points for each condition. The transient analysis determines the behavior of the circuit in the time domain, e.g. the step response for a low pass lter. The AC analysis linearizes the circuit around the specied operating point and then determines the behavior of the circuit in the frequency domain in steady state for a sinusoidal source. It can e.g. return the amplitude and phase response of an amplier. The AC analysis is a small signal analysis which means that the nonlinear components are linearized in their bias points rst. Only then is the actual frequency analysis performed by the simulator. Besides the mentioned analyses there are many others. However, these are not in our interest at the moment. Now start the simulation tool Analog Environment (long known as Analog Artist) from the Composer with the command Tools.Analog Environment. The window depicted in Fig. 5 will appear on your screen.

Figure 5: Analog Environment.

The menu entry Setup.Simulator/Directory/Host allows you to select the simulator (we are going to use spectre) and to specify the directory in Project Directory where the simulation data should be written to. Accept the defaults here. The le path to the simulation models may be specied with Setup.Model Libraries. Again, 6

accept the defaults.

5.1 The DC Analysis

Select Analyses.Choose in the Analog Environment and click on dc in the following dialog box. Make sure to tick Save DC Operation Point and click OK. Now run the simulation by clicking Simulation.Run. First, the netlist is generated which is then passed to the simulator along with the model parameters and simulation settings. Finally, the simulator is invoked. After the simulation has completed you can have the DC bias values printed by rst clicking Results.Print.DC Operating Points and then selecting the NMOS transistor symbol. 5.1.1 The DC Sweep

Now we want to simulate the steady state behavior of the NMOS transistor when the drain source voltage is rising from 0 to 3.6 V. Select Analyses.Choose dc Component Parameter Select Component and select the voltage source V1 in the composer (see Fig. 6). A dialog box with a selection of parameters pops up. Choose DC voltage and click OK. For the Sweep Range use 0-3.6 and proceed with OK. With these settings, a DC analysis is performed for each relevant value of VDS within the given range. Before you start the simulation, you have to dene which voltages and currents should be saved. Choose Output.Save All in the Analog Environment and make sure that allpub is ticked for Select signals to output (save) and that all is ticked for Select device currents (currents). Proceed with OK and start the simulation. After the simulation has completed, open the window shown in Fig. 7 with Tools.Calculator. Have a look at the second column from the left (vt, vf, . . . ). The rst letter stands for voltage and the second one denotes the type of analysis: t for transient analysis, f for frequency analysis, s for DC sweep, and dc for DC analysis. The third column from the left contains the same analyses pertaining to currents. In order to plot the drain current IDS as a function of the drain source voltage VDS , click is in the calculator and then on the drain port (marked by a red square) of the transistor in the Composer Window. Now the display line of the calculator reads IS("/M1/D"). If so, click the plot button to get the characteristic shown in Fig. 8. Instead of using the calculator you may plot the simulation results directly from the Analog Environment with help of the command Results.Direct Plot.DC and by selecting the port or net of interest with the mouse in the schematic. Press ESC to terminate the selection and to plot the curve. 5.1.2 The Parametric Analysis

The parametric analysis allows you to simulate the IDS (VDS ) characteristic for various VGS in a single pass. For this, replace the DC voltage value of the source V0 with the variable vgs and save the changes with Design.Check and Save. Now click Variables.Copy from Cellview in the Analog Environment in order to import your variable. The command Tools.Parametric Analysis brings the window depicted in Fig. 9 to your screen.

Figure 6: DC Sweep.

Enter vgs for Variable Name and choose a range of 1 to 3.5. Set Step Control to Linear Steps and enter 0.5 for Step Size. Now start the simulation with Analysis.Start. The plot may be produced the same way as for the DC sweep analysis, i.e. choose is in the calculator, click on the drain port, and hit plot afterwards. However, if you have kept the plot window from the DC sweep open, click on Edit.Delete All before you hit plot in order to clear the old contents. This should result in the IDS (VDS , VGS ) characteristic of Fig. 10. Problems: DC Analysis of a MOSFET 1. (a) The range where the output characteristic is almost at may be interpreted as a nite outputresistance source controlled by its VGS voltage. What kind of source is this? (b) What is the value of this resistance
dVDS dIDS

at VGS = 3 V and VDS = 3 V?

Use the following two procedures to determine the resistance: i. Determine the operating points of the transistor. Use the command Results.Print.DC 8

Figure 7: Calculator.

Figure 8: Output characteristic of the NMOS transistor.

Operating Points and click on the transistor in the composer. Determine the wanted resistance with the help of the parameter gds. ii. Calculate the resistance from the slope of the corresponding characteristic. Click on Special Functions in the calculator and select deriv (for derivation). The display line of the calculator now reads deriv(IS("/M1/D")). Pressing plot (without deleting the former plot) results in the the wanted set of curves that are shown together with the IDS (VDS , VGS ) characteristics in the same plot. Split the curves with 9

Figure 9: Input window for the parametric analysis.

Axes.To Strip to separate plots. Zoom in on the area around VDS = 3 V with Zoom.Zoom In and activate marker A with Markers.Crosshair Marker A. You should now be able to read out the slope of the wanted characteristic conveniently. 2. In the following three problems you are going to simulate the output characteristic of various transistor channel lengths and widths. We are going to use variables for these parameters so we do not have to adjust the quantities in the composer each time. First close the Waveform Window and the input window for the parametric analysis. Select the transistor in the composer and hit q. If you get the wrong window here, press ESC and try again. Now enter the variable w for Width and Width Stripe and use the variable l for Length. Make sure that the factor u does not stay there undeliberately. Click OK and Design.Check and Save. Remember that you have to copy the new variables from the composer with Variables.Copy From Cellview into the Analog Environment. The variables may now be edited with Variables.Edit. Choose vgs=3, w=0.7u, l=0.35u, proceed with OK and start the simulation with Simulation.Run. Plot the IDS (VDS ) characteristic. Now double the channel width W and simulate again! (a) How did the current IDS change in response to the new channel width W? 3. Now also double the channel length L! Compare the output characteristic for W = 0.7 m, L = 0.35 m to the characteristic for W = 1.4 m, L = 0.7 m! (a) How did the controlled source change? (b) How did its resistance change? 4. Set W = 50 m, L = 2 m and repeat the parametric analysis from the beginning of this section. Choose a range of 0.8-1.8 V for the variable vgs and set the Step Control to Linear. Enter 11 for Total Steps and start the simulation with Analysis.Start.

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Figure 10: IDS (VDS , VGS ) characteristic.

After you have plotted the characteristics in the Waveform Window, print the curves to a le and send it through the VPP homepage to the prefered printer. Close the Analog Environment with Session.Quit. A dialog box will ask you whether you want to save the current state. Answer Yes. Next, options on what to save are presented. Accept the default by pressing OK. You could also save the current state without quitting Analog Environment with Session.Save State. At a later point in time, you may load the simulation settings again with Session.Load State. Now close all windows except the Command Interpreter Window and the Library Manager. Simple Amplier Circuit A simple single-stage amplier is to be built with a n-channel MOSFET as shown in Fig. 11. VDD is 3.3 V and the n-channel MOSFET has the following dimensions: W = 50 m, L = 2 m. The MOSFET should operate at a gate source bias of VGS = 1.4 V and a drain source bias of VDS = 2.3 V.

VDD VOUT

VIN

Figure 11: Simple NMOS amplier.

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1. Mark the operating point on your characteristics sheet obtained before! 2. Draw the load line! How large is the load resistance? 3. Create a new cell amplifier in your library MyLibrary. Open the schematic view for this cell and draw the amplier circuit of Fig. 11 in the same manner as in section 4. Use the cell res of analogLib to model the resistor R. Simulate the output voltage VOUT as a function of VIN with the help of the DC sweep analysis. Choose the range 0-3.3 V for VIN . After the simulation, click on vs in the calculator window and then on the net representing VOUT in the composer. (a) Based upon your VOUT = f (VIN ) plot, specify the range of VIN in which the circuit works as an amplier! (b) Is this range also visible on your sheet with the load line? Mark the range on this sheet! (c) Determine the gain
dVOUT dVIN

in a couple of operating points with help of VOUT = f (VIN ) plot!

4. As you may see, the gain is fairly small. (a) How must the load resistance or the load line be changed in order to achieve a higher gain? (b) Is it reasonable to replace the load R with an ideal current source? Draw the load line of an ideal current source in a qualitative manner! Now quit the Analog Environment with Session.Quit and close all windows except the Command Interpreter Window and the Library Manager.

5.2 The AC Analysis

In this section, you are going to simulate the amplitude and phase response of a RLC network. Draw the schematic of the RLC net circuit as shown in Fig. 12.

Figure 12: RLC network.

Select the voltage source and press q. Set AC Magnitude to 1 V. Save the design and start the Analog Environment. Click Analyses.Choose and select ac. For Sweep Range choose 1K for the start 12

frequency and 1G for the stop frequency. Pick Logarithmic as Sweep Type and set the number of points per decade to 100. Proceed with OK and start the simulation. In order to plot the amplitude response of the circuit, press the vf button in the calculator and select the VOUT net in the composer. Now click onto dB20 and then plot. Repeat the procedure for the phase response but use phase instead of db20 this time.

5.3 The Transient Analysis

Now we would like to simulate the step response for the RLC network. Replace the voltage source V0 with the cell vpulse from the library analogLib and set the following values: Voltage1 Voltage2 Delay time Rise time Fall time Pulse Width Period :=0V :=5V :=500ns :=20ns :=20ns :=5us :=10us

Save the design and click Analyses.Choose in the Analog Environment. Now pick the tran analysis and enter 9u for Stop Time. Make sure that Enabled in the lower left corner of the window is ticked and proceed with OK. Delete the contents of the Waveform Window and start the simulation. Now plot the input voltage by pressing vt in the calculator and clicking on the net V IN in the composer. Press the plot button afterwards. Use the same procedure to plot the output voltage V OUT. Measure the peak of over- and undershoot with help of marker A. Now conduct the same analysis with the initial conditions VC(t=0) = 5 V and IL(t=0) = 400 mA. For this, select the capacitor and press q. You may now specify the initial voltage in the eld Initial condition. The same procedure applies to the inductor. Save the design and start the simulation. Use the command Window.Update Results of the Waveform Window to refresh the input and output voltage plots. Again, measure the peak of over- and undershoot. This completes the introduction to Cadence. You may now close the Analog Environment and quit Cadence with the command File.Exit of the Command Interpreter Window.

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