VELAMMAL ENGINEERING COLLEGE

DEPARTMENT OF INFORMATION TECHNOLOGY

CS2252 MICROPROCESSOR AND MICROCONTROLLER

AIM
To learn the architecture programming microprocessors and microcontrollers. and interfacing of

OBJECTIVES
To introduce the architecture and programming of 8085 microprocessor. To introduce the interfacing of peripheral devices with 8085 microprocessor. To introduce the architecture and programming of 8086 microprocessor. To introduce the architecture, programming and interfacing of 8051 micro controller.

Unit 1. THE 8085 AND 8086 MICROPROCESSORS

ARCHITECHTURE or FUNCTIONAL BLOCK DIAGRAM OF 8085
The functional block diagram or architechture of 8085 Microprocessor is very important as it gives the complete details about a Microprocessor. Fig. shows the Block diagram of a Microprocessor.

8085 Bus Structure:

Address Bus:

The address bus is a group of 16 lines generally identified as A0 to A15. The address bus is unidirectional: bits flow in one direction-from the MPU to peripheral devices. The MPU uses the address bus to perform the first function: identifying a peripheral or a memory location.

Data Bus:

The data bus is a group of eight lines used for data flow. These lines are bi-directional - data flow in both directions between the MPU and memory and peripheral devices. The MPU uses the data bus to perform the second function: transferring binary information. The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF (28 = 256 numbers). The largest number that can appear on the data bus is 11111111.

Control Bus:

The control bus carries synchronization signals and providing timing signals. The MPU generates specific control signals for every operation it performs. These signals are used to identify a device type with which the MPU wants to communicate.

Registers of 8085:

The 8085 have six general-purpose registers to store 8-bit data during program execution. These registers are identified as B, C, D, E, H, and L. They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit operations.

Accumulator (A):

The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator.

Flags:

The ALU includes five flip-flops that are set or reset according to the result of an operation. The microprocessor uses the flags for testing the data conditions. They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most commonly used flags are Sign, Zero, and Carry.

The bit position for the flags in flag register is,

1.Sign Flag (S): After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remaining is the magnitude of number. If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be viewed as positive number. 2.Zero Flag (z):

If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it is reset. 3.Auxiliary Carry Flag (AC): If D3 generates any carry when doing any arithmetic and logical operation, this flag is set. Otherwise it is reset. 4.Parity Flag (P): If the result of arithmetic and logical operation contains even number of 1's then this flag will be set and if it is odd number of 1's it will be reset. 5.Carry Flag (CY): If any arithmetic and logical operation result any carry then carry flag is set otherwise it is reset. Temporary Register: It is used to hold the data during the arithmetic and logical operations. Instruction Register: When an instruction is fetched from the memory, it is loaded in the instruction register. Instruction Decoder: It gets the instruction from the instruction register and decodes the instruction. It identifies the instruction to be performed. Serial I/O Control: It has two control signals named SID and SOD for serial data transmission. Interrupt Control Unit:

It receives hardware interrupt signals and sends an acknowledgement for receiving the interrupt signal.

Arithmetic and Logic Unit (ALU):

It is used to perform the arithmetic operations like addition, subtraction, multiplication, division, increment and decrement and logical operations like AND, OR and EX-OR. It receives the data from accumulator and registers. According to the result it set or reset the flags.

Program Counter (PC):

This 16-bit register sequencing the execution of instructions. It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The function of the program counter is to point to the memory address of the next instruction to be executed. When an opcode is being fetched, the program counter is incremented by one to point to the next memory location.

Stack Pointer (Sp):

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading a 16-bit address in the stack pointer (register).

Timing and Control unit:

It has three control signals ALE, RD (Active low) and WR (Active low) and three status signals IO/M(Active low), S0 and S1. ALE is used for provide control signal to synchronize the components of microprocessor and timing for instruction to perform the operation. RD (Active low) and WR (Active low) are used to indicate whether the operation is reading the data from memory or writing the data into memory respectively.

IO/M(Active low) is used to indicate whether the operation is belongs to the memory or peripherals. If,

Interrupt Control Unit:

It receives hardware interrupt signals and sends an acknowledgement for receiving the interrupt signal

PIN DIAGRAM AND PIN DESCRIPTION OF 8085

1. Power supply and Clock frequency signals:

Vcc + 5 volt power supply Vss Ground X1, X2 : Crystal or R/C network or LC network connections to set the frequency of internal clock generator. The frequency is internally divided by two. Since the basic operating timing frequency is 3 MHz, a 6 MHz crystal is connected externally. CLK (output)-Clock Output is used as the system clock for peripheral and devices interfaced with the microprocessor. 8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as follows Power supply and clock signals Address bu Data bus Control and status signals Interrupts and externally initiated signals Serial I/O ports

1. 2. 3. 4. 5. 6.

Timing Diagram is a graphical representation. It represents the execution time taken by each instruction in a graphical format. The execution time is represented in T-states. Instruction Cycle: The time required to execute an instruction is called instruction cycle. Machine Cycle: The time required to access the memory or input/output devices is called machine cycle. T-State: The machine cycle and instruction cycle takes multiple clock periods. A portion of an operation carried out in one system clock period is called as T-state. MACHINE CYCLES OF 8085: The 8085 microprocessor has 5 (seven) basic machine cycles. They are Opcode fetch cycle (4T) 1. 1. 1. 1. Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T)

Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order. The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states.

One T-state is equal to the time period of the internal clock signal of the processor. The T-state starts at the falling edge of a clock.

Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram. 2. Address Bus:

A8 - A15 (output; 3-state) It carries the most significant 8 bits of the memory address or the 8 bits of the I/O address;

3. Multiplexed Address / Data Bus:

AD0 - AD7 (input/output; 3-state) These multiplexed set of lines used to carry the lower order 8 bit address as well as data bus. During the opcode fetch operation, in the first clock cycle, the lines deliver the lower order address A0 - A7. In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.

The CPU may read or write out data through these lines.

4. Control and Status signals:

ALE (output) - Address Latch Enable. This signal helps to capture the lower order address presented on the multiplexed address / data bus. RD (output 3-state, active low) - Read memory or IO device. This indicates that the selected memory location or I/O device is to be read and that the data bus is ready for accepting data from the memory or I/O device. WR (output 3-state, active low) - Write memory or IO device. This indicates that the data on the data bus is to be written into the selected memory location or I/O device. IO/M (output) - Select memory or an IO device. This status signal indicates that the read / write operation relates to whether the memory or I/O device. It goes high to indicate an I/O operation. I It goes low for memory operations.

5. Status Signals: It is used to know the type of current operation of the microprocessor.

The microprocessor is a clock-driven semiconductor device consisting of electronic logic circuits manufactured by using either a large-scale integration (LSI) or very-large-scale integration (VLSI) technique. The microprocessor is capable of performing various computing functions and making decisions to change the sequence of program execution.

In large computers, a CPU implemented on one or more circuit boards performs these computing functions. The microprocessor is in many ways similar to the CPU, but includes the logic circuitry, including the control unit, on one chip. The microprocessor can be divided into three segments for the sake clarity, arithmetic/logic unit (ALU), register array, and control unit.

TIMING DIAGRAM OF 8085 INSTRUCTIONS

Timing diagram for STA 526AH.

STA means Store Accumulator -The contents of the accumulator is stored in the specified address(526A). The opcode of the STA instruction is said to be 32H. It is fetched from the memory 41FFH(see fig). - OF machine cycle Then the lower order memory address is read(6A). - Memory Read
Machine Cycle Cycle

Read the higher order memory address (52).- Memory Read Machine The combination of both the addresses are considered and the content from accumulator is written in 526A. - Memory Write
Machine Cycle

Assume the memory address for the instruction and let the content of accumulator is C7H. So, C7H from accumulator is now stored in 526A.

Timing diagram for IN C0H.

Fetching the Opcode DBH from the memory 4125H. Read the port address C0H from 4126H. Read the content of port C0H and send it to the accumulator. Let the content of port is 5EH.

Timing diagram for INR M

Fetching the Opcode 34H from the memory 4105H. (OF cycle) Let the memory address (M) be 4250H. (MR cycle -To read Memory address and data) Let the content of that memory is 12H. Increment the memory content from 12H to 13H. (MW machine cycle)

Timing diagram for MVI B, 43H.

Fetching the Opcode 06H from the memory 2000H. (OF machine cycle) Read (move) the data 43H from memory 2001H. (memory read)

ADDRESSING MODES OF 8085

Every instruction of a program has to operate on a data. The method of specifying the data to be operated by the instruction is called Addressing. The 8085 has the following 5 different types of addressing. 1. 2. 3. 4. 5. Immediate Addressing Direct Addressing Register Addressing Register Indirect Addressing Implied Addressing

1. Immediate Addressing:

In immediate addressing mode, the data is specified in the instruction itself. The data will be a part of the program instruction. EX. MVI B, 3EH - Move the data 3EH given in the instruction to B register; LXI SP, 2700H.

2. Direct Addressing:

In direct addressing mode, the address of the data is specified in the instruction. The data will be in memory. In this addressing mode, the program instructions and data can be stored in different memory. EX. LDA 1050H - Load the data available in memory location 1050H in to accumulator; SHLD 3000H

3. Register Addressing:

In register addressing mode, the instruction specifies the name of the register in which the data is available. EX. MOV A, B - Move the content of B register to A register; SPHL; ADD C.

4. Register Indirect Addressing:

In register indirect addressing mode, the instruction specifies the name of the register in which the address of the data is available. Here the data will be in memory and the address will be in the register pair. EX. MOV A, M - The memory data addressed by H L pair is moved to A register. LDAX B.

5. Implied Addressing: In implied addressing mode, the instruction itself specifies the data to be operated. EX. CMA - Complement the content of accumulator; RAL

8085 INSTRUCTION SET CLASSIFICATION

The 8085 instruction set can be classified into the following five functional headings. 1. DATA TRANSFER INSTRUCTIONS: It includes the instructions that move (copies) data between registers or between memory locations and registers. In all data transfer operations the content of source register is not altered. Hence the data transfer is copying operation. Ex: (1) Mov A,B (2) MVI C,45H 2. ARITHMETIC INSTRUCTIONS: Includes the instructions, which performs the addition, subtraction, increment or decrement operations. The flag conditions are altered after execution of an instruction in this group. Ex: (1) ADD A,B (2) SUI B,05H 3. LOGICAL INSTRUCTIONS: The instructions which performs the logical operations like AND, OR, EXCLUSIVE- OR, complement, compare and rotate instructions are grouped under this heading. The flag conditions are altered after execution of an instruction in this group. Ex: (1) ORA A (2) ANI B, 01H 4. BRANCHING INSTRUCTIONS: The instructions that are used to transfer the program control from one memory location to another memory location are grouped under this heading. Ex: (1) CALL (2) JMP 4100

5. MACHINE CONTROL INSTRUCTIONS: It includes the instructions related to interrupts and the instruction used to stop the program execution. Ex: (1) NOP (2) END

DATA TRANSFER INSTRUCTIONS Opcode Operand Rd, Rs MOV M, Rs Rd, M MVI Rd, data
Move immediate 8-bit

Explanation of
Instruction

Description

This instruction copies the contents of the source register into the destination register; the contents of the source register are not altered. If one of the operands is a memory location, its location is Copy from source(Rs) specified by the contents of the HL registers. to destination(Rd)

Example: MOV B, C or MOV B, M

The 8-bit data is stored in the destination register or memory. If the operand is a memory location, its location is specified by the contents of the HL registers.

M, data 16-bit address

Example: MVI B, 57H or MVI M, 57H

Load accumulator The contents of a memory location, specified by a 16-bit address in the operand, are copied to the accumulator. The contents of the source are not altered.

LDA

Example: LDA 2034H

Load accumulator indirect The contents of the designated register pair point to a memory location. This instruction copies the contents of that memory location into the accumulator. The contents of either the register pair or the memory location are not altered.

LDAX

B/D Reg. pair Reg. pair, 16-bit data 16-bit address 16-bit address

Example: LDAX B LXI

Load register pair immediate The instruction loads 16-bit data in the register pair designated in the operand. Example:

LXI H, 2034H or LXI H, XYZ

LHLD STA

Load H and L registers direct

The instruction copies the contents of the memory location pointed out by the 16-bit address into register L and copies the contents of the next memory location into register H. The contents of source memory locations are not altered.

Example: LHLD 2040H

16-bit address The contents of the accumulator are copied into the memory location specified by the operand. This is a 3-byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address.

Example: STA 4350H STAX Reg. pair

Store accumulator indirect The contents of the accumulator are copied into the memory location specified by the contents of the operand (register pair). The contents of the accumulator are not altered.

Example: STAX B 16-bit address

The contents of register L are stored into the memory location specified by the 16-bit address in the operand and the contents of H register are stored into the next memory location by incrementing the operand. The contents of registers HL are not altered. This is a 3byte instruction, the second byte specifies the low-order address and the third byte specifies the high-order address.

SHLD

Store H and L registers direct

Example: SHLD 2470H XCHG none

Exchange H and L with D and E The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E.

Example: XCHG
The instruction loads the contents of the H and L registers into the stack pointer register, the contents of the H register provide the high-order address and the contents of the L register provide the Copy H and L low-order address. The contents of the H registers to the stack and L registers are not altered. pointer

SPHL

none

Example: SPHL
Exchange H and L with top of stack The contents of the L register are exchanged with the stack location pointed out by the contents of the stack pointer register. The contents of the H register are exchanged with the next stack location (SP+1); however, the contents of the stack pointer register are not altered.

XTHL

none

Example: XTHL
The contents of the register pair designated in the operand are copied onto the stack in the following sequence. The stack pointer register is decremented and the contents of the highorder register (B, D, H, A) are copied into that location. The stack pointer register is decremented again and the contents of the low-order register (C, E, L, flags) are copied to that location.

PUSH

Reg. pair

Push register pair onto stack

Example: PUSH B or PUSH A

The contents of the memory location pointed out by the stack pointer register are copied to the low-order register (C, E, L, status flags) of the operand. The stack pointer is incremented by 1 and the contents of that memory location are copied to the high-order register (B, D, H, A) of the operand. The stack pointer register is again incremented by 1.

POP

Reg. pair

Pop off stack to register pair

Example: POP H or POP A OUT 8-bit port address

The contents of the accumulator are copied into the I/O port Output data from specified by the operand. accumulator to a port with 8-bit address

Example: OUT F8H

IN

8-bit port address

The contents of the input port designated in the operand are read Input data to and loaded into the accumulator. accumulator from a port with 8-bit address Example: IN 8CH

ARITHMETIC INSTRUCTIONS Opcode Operand R M Explanation of Instruction Description

ADD

The contents of the operand (register or memory) are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its location is Add register or memory, specified by the contents of the HL registers. All flags are modified to accumulator to reflect the result of the addition.

Example: ADD B or ADD M R M

The contents of the operand (register or memory) and M the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. If the operand is a memory location, its Add register to location is specified by the contents of the HL registers. All flags accumulator with carry are modified to reflect the result of the addition.

ADC

Example: ADC B or ADC M ADI 8-bit data

Add immediate to accumulator The 8-bit data (operand) is added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition.

Example: ADI 45H ACI 8-bit data

Add immediate to accumulator with carry The 8-bit data (operand) and the Carry flag are added to the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the addition.

Example: ACI 45H LXI DAD Reg. pair, 16-bit data Reg. pair
Load register pair immediate The instruction loads 16-bit data in the register pair designated in the operand. Example:

LXI H, 2034H or LXI H, XYZ

Add register pair to H The 16-bit contents of the specified register pair are added to the and L registers contents of the HL register and the sum is stored in the HL register. The contents of the source register pair are not altered. If

the result is larger than 16 bits, the CY flag is set. No other flags are affected.

Example: DAD H R M
Subtract register or memory from accumulator The contents of the operand (register or memory ) are subtracted from the contents of the accumulator, and the result is stored in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction.

SUB

Example: SUB B or SUB M R M

Subtract source and borrow from accumulator The contents of the operand (register or memory ) and M the Borrow flag are subtracted from the contents of the accumulator and the result is placed in the accumulator. If the operand is a memory location, its location is specified by the contents of the HL registers. All flags are modified to reflect the result of the subtraction.

SBB

Example: SBB B or SBB M SUI 8-bit data

Subtract immediate from accumulator The 8-bit data (operand) is subtracted from the contents of the accumulator and the result is stored in the accumulator. All flags are modified to reflect the result of the subtraction.

Example: SUI 45H SBI 8-bit data

Subtract immediate from accumulator with borrow The contents of register H are exchanged with the contents of register D, and the contents of register L are exchanged with the contents of register E.

Example: XCHG

INR

R M R R M R none

The contents of the designated register or memory) are incremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the Increment register or contents of the HL registers. memory by 1

Example: INR B or INR M

Increment register pair by 1 The contents of the designated register pair are incremented by 1 and the result is stored in the same place.

INX

Example: INX H

DCR

The contents of the designated register or memory are M decremented by 1 and the result is stored in the same place. If the operand is a memory location, its location is specified by the Decrement register or contents of the HL registers. memory by 1

Example: DCR B or DCR M

Decrement register pair by 1 Decimal adjust accumulator The contents of the designated register pair are decremented by 1 and the result is stored in the same place.

DCX DAA

Example: DCX H
The contents of the accumulator are changed from a binary value to two 4-bit binary coded decimal (BCD) digits. This is the only instruction that uses the auxiliary flag to perform the binary to BCD conversion, and the conversion procedure is described below. S, Z, AC, P, CY flags are altered to reflect the results of the operation.

If the value of the low-order 4-bits in the accumulator is greater than 9 or if AC flag is set, the instruction adds 6 to the low-order four bits. If the value of the high-order 4-bits in the accumulator is greater than 9 or if the Carry flag is set, the instruction adds 6 to the highorder four bits.

Example: DAA

BRANCHING INSTRUCTIONS Opcode Explanation Operand of Instruction 16-bit address

Flag Status Jump unconditionally

Description
The program sequence is transferred to the memory location specified by the 16-bit address given in the operand.

JMP

Example: JMP 2034H or JMP XYZ

Opcode

Description

JC

Jump on Carry CY = 1 Jump on no JNC CY = 0 Carry Jump on JP S=0 positive

16-bit address

Jump conditionally The program sequence is transferred to the memory location specified by the 16-bit address given in the operand based on the specified flag of the PSW as described below.

Example: JZ 2034H or JZ XYZ

JM JZ

Jump on minus S = 1 Jump on zero Z=1 Jump on no JNZ Z=0 zero Jump on parity JPE P=1 even Jump on parity JPO P=0 odd
Opcode Description Flag Status

CC CNC CP CM CZ CNZ

Call on Carry CY = 1 Call on no Carry CY = 0 Call on positive S = 0 Call on minus S = 1 Call on zero Z=1 Call on no zero Z = 0 Call on parity CPE P=1 even Call on parity CPO P=0 odd

16-bit address

Unconditional subroutine call

The program sequence is transferred to the memory location specified by the 16-bit address given in the operand. Before the transfer, the address of the next instruction after CALL (the contents of the program counter) is pushed onto the stack.

Example: CALL 2034H or CALL XYZ

RET

none

Return from subroutine unconditionally

The program sequence is transferred from the subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter,and program execution begins at the new address.

Example: RET
Opcode Description Flag Status

none

RC RNC RP RM RZ RNZ RPE

Return on Carry CY = 1 Return on no CY = 0 Carry Return on positive S = 0 Return on S=1 minus Return on zero Z = 1 Return on no Z=0 zero Return on parity P = 1

Return from subroutine conditionally

The program sequence is transferred from the subroutine to the calling program based on the specified flag of the PSW as described below. The two bytes from the top of the stack are copied into the program counter, and program execution begins at the new address.

Example: RZ

even Return on parity RPO P=0 odd

Load program counter with HL contents The contents of registers H and L are copied into the program counter. The contents of H are placed as the high-order byte and the contents of L as the low-order byte. Example: PCHL The RST instruction is equivalent to a 1byte call instruction to one of eight memory locations depending upon the number. The instructions are generally used in conjunction with interrupts and inserted using external hardware. However these can be used as software instructions in a program to transfer program execution to one of the eight locations. The addresses are: Instruction Restart Address

PCHL

none

RST

0-7

Restart

RST 0 RST1 RST 2 RST 3 RST 4 RST 5 RST 6 RST 7

0000H 0008H 0010H 0018H 0020H 0028H 0030H 0038H

The 8085 has four additional interrupts and these interrupts generate RST instructions internally and thus do not require any external hardware. These instructions and their Restart addresses are: Interrupt Restart Address

TRAP RST 5.5 RST 6.5 RST 7.5

0024H 002CH 0034H 003CH

LOGICAL Opcode Operand

INSTRUCTIONS
Description
The contents of the operand (register or memory) are M compared with the contents of the accumulator. Both contents are preserved . The result of the comparison is shown by setting the flags of the PSW as follows:

Explanation of Instruction

CMP

R M

Compare register or memory with accumulator

if (A) < (reg/mem): carry flag if (A) = (reg/mem): zero flag if (A) > (reg/mem): carry and zero flags are reset

is is

set set

Example: CMP B or CMP M

The second byte (8-bit data) is compared with the contents of the accumulator. The values being compared remain unchanged. The result of the comparison is shown by setting the flags of the PSW as follows:

CPI

8-bit data

Compare immediate with accumulator

if (A) < data: carry if (A) = data: zero if (A) > data: carry and zero flags are reset

flag flag

is is

set set

Example: CPI 89H R M 8-bit data

The contents of the accumulator are logically ANDed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its Logical AND register or address is specified by the contents of HL registers. S, Z, P are memory with modified to reflect the result of the operation. CY is reset. AC is set. accumulator

ANA

Example: ANA B or ANA M ANI

Logical AND immediate The contents of the accumulator are logically ANDed with the with accumulator 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the

operation. CY is reset. AC is set.

Example: ANI 86H R M

The contents of the accumulator are Exclusive ORed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its Exclusive OR register or address is specified by the contents of HL registers. S, Z, P are memory with modified to reflect the result of the operation. CY and AC are reset. accumulator

XRA

Example: XRA B or XRA M XRI 8-bit data

The contents of the accumulator are Exclusive ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are Exclusive OR immediate reset. with accumulator

Example: XRI 86H R M

The contents of the accumulator are logically ORed with M the contents of the operand (register or memory), and the result is placed in the accumulator. If the operand is a memory location, its Logical OR register or address is specified by the contents of HL registers. S, Z, P are memory with modified to reflect the result of the operation. CY and AC are reset. accumulator

ORA

Example: ORA B or ORA M ORI 8-bit data

The contents of the accumulator are logically ORed with the 8-bit data (operand) and the result is placed in the accumulator. S, Z, P are modified to reflect the result of the operation. CY and AC are Logical OR immediate reset. with accumulator

Example: ORI 86H RLC none

Rotate accumulator left Each binary bit of the accumulator is rotated left by one position. Bit D7 is placed in the position of D0 as well as in the Carry flag. CY is modified according to bit D7. S, Z, P, AC are not affected.

Example: RLC RRC none

Rotate accumulator right Each binary bit of the accumulator is rotated right by one position. Bit D0 is placed in the position of D7 as well as in the Carry flag. CY is modified according to bit D0. S, Z, P, AC are not affected.

Example: RRC RAL none

Each binary bit of the accumulator is rotated left by one position through the Carry flag. Bit D7 is placed in the Carry flag, and the Carry flag is placed in the least significant position D0. CY is Rotate accumulator left modified according to bit D7. S, Z, P, AC are not affected. through carry

Example: RAL RAR CMA none none

Rotate accumulator right through carry Each binary bit of the accumulator is rotated right by one position through the Carry flag. Bit D0 is placed in the Carry flag, and the Carry flag is placed in the most significant position D7. CY is modified according to bit D0. S, Z, P, AC are not affected.

Example: RAR
Complement accumulator The contents of the accumulator are complemented. No flags are affected.

Example: CMA
The Carry flag is complemented. No other flags are affected.

CMC STC

none none

Complement carry Set Carry Set Carry

Example: CMC Example: STC

CONTROL INSTRUCTIONS Explanation Opcode Operand of Instruction NOP HLT none none
No operation

Description

No operation is performed. The instruction is fetched and decoded. However no o is executed.

Example: NOP

Halt and enter wait The CPU finishes executing the current instruction and halts any further execu state interrupt or reset is necessary to exit from the halt state.

Example: HLT DI EI none none

Disable interrupts The interrupt enable flip-flop is reset and all the interrupts except the TRAP are No flags are affected.

Example: DI

Enable interrupts The interrupt enable flip-flop is set and all interrupts are enabled. No flags are After a system reset or the acknowledgement of an interrupt, the interrupt enable f reset, thus disabling the interrupts. This instructio necessary to reenable the interrupts (except TRAP).

Example: EI

This is a multipurpose instruction used to read the status of interrupts 7.5, 6.5, 5.5 serial data input bit. The instruction loads eight bits in the accumulator with the f interpretations.

Example: RIM RIM none

Read interrupt mas

This is a multipurpose instruction and used to implement the 8085 interrupts 7.5 and serial data output. The instruction interprets the accumulator contents as follo

Example: SIM

SIM

none

Set interrupt mask

Programming 8085

Unit 2: 8086 SOFTWARE ASPECTS

Overview or Features of 8086

It is a 16-bit Microprocessor(p).Its ALU, internal registers works with 16bit binary word. 8086 has a 20 bit address bus can access up to 220= 1 MB memory locations. 8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at a time. It can support up to 64K I/O ports. It provides 14, 16 -bit registers. Frequency range of 8086 is 6-10 MHz It has multiplexed address and data bus AD0- AD15 and A16 A19. It requires single phase clock with 33% duty cycle to provide internal timing. It can prefetch upto 6 instruction bytes from memory and queues them in order to speed up instruction execution. It requires +5V power supply. A 40 pin dual in line package. 8086 is designed to operate in two modes, Minimum mode and Maximum mode.
o

The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a single microprocessor configuration. The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a multi micro processors configuration.

Pin Diagram of 8086 and Pin description of 8086

Figure shows the Pin diagram of 8086. The description follows it.

The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40 pin CERDIP or plastic package. The 8086 operates in single processor or multiprocessor configuration to achieve high performance. The pins serve a particular function in minimum mode (single processor mode ) and other function in maximum mode configuration (multiprocessor mode ).

The 8086 signals can be categorised in three groups.

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The first are the signal having common functions in minimum as well as maximum mode. The second are the signals which have special functions for minimum mode The third are the signals having special functions for maximum mode.

The following signal descriptions are common for both modes.

AD15-AD0 : These are the time multiplexed memory I/O address

and data lines.
o

Address remains on the lines during T1 state, while the data is available on the data bus during T2, T3, Tw and T4. These lines

are active high and float to a tristate during interrupt acknowledge and local bus hold acknowledge cycles.

A19/S6,A18/S5,A17/S4,A16/S3
multiplexed address and status lines.
o

: These are the time

During T1 these are the most significant address lines for memory operations. During I/O operations, these lines are low. During memory or I/O operations, status information is available on those lines for T2,T3,Tw and T4. The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. The S4 and S3 combinely indicate which segment register is presently being used for memory accesses as in below fig. These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is always low. The address bit are separated from the status bit using latches controlled by the ALE signal.

o o

The following pin functions are for the minimum mode operation of
8086.

M/IO Memory/IO : This is a status line logically equivalent to

S2 in maximum mode. When it is low, it indicates the CPU is having

an I/O operation, and when it is high, it indicates that the CPU is having a memory operation. This line becomes active high in the previous T4 and remains active till final T4 of the current cycle. It is tristated during local bus hold acknowledge .

INTA Interrupt Acknowledge : This signal is used as a read

strobe for interrupt acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.

ALE Address Latch Enable : This output signal indicates the

availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated.

DT/R Data Transmit/Receive: This output is used to decide

the direction of data flow through the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high and when the processor is receiving data, this signal is low.

DEN Data Enable : This signal indicates the availability of

valid data over the address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is tristated during hold acknowledge cycle.

HOLD, HLDA- Acknowledge : When the HOLD line goes high,

it indicates to the processor that another master is requesting the bus access. The processor, after receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after completing the current bus cycle.

At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should be externally synchronized. If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided :

1.The request occurs on or before T2 state of the current cycle. 2.The current cycle is not operating over the lower byte of a word. 3.The current cycle is not the first acknowledge of an interrupt acknowledge 4. A Lock instruction is not being executed. sequence.

The following pin functions are applicable for maximum mode operation of 8086.

S2, S1, S0 Status Lines : These are the status lines which
reflect the type of operation, being carried out by the processor. These become activity during T4 of the previous cycle and active during T1 and T2 of the current bus cycles.

LOCK : This output pin indicates that other system bus master will
be prevented fromgaining the system bus, while the LOCK signal is low. The LOCK signal is activated by the LOCK prefix instruction and remains active until the completion of the next instruction. When the CPU is executing a critical instruction which requires the system bus, the LOCK prefix instruction ensures that other processors connected in the system will not gain the control of the bus.

The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an external bus controller. By prefetching the instruction, there is a considerable speeding up in instruction execution in 8086. This is known as

instruction pipelining.

S2 S1 S0 0 0 0 0 0 0 0 1 1 1 0 1

Indication Interrupt Acknowledge Read I/O port Write I/O port Halt

1 1 1 1

0 0 1 1

0 1 0 1

Code Access Read Memory Write Memory Passive

At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty an the microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if the CS:IP address is even.

The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and is a part of opcode, in case of some instructions ( two byte opcode instructions), the remaining part of code lie in second byte.

The second byte is then decoded in continuation with the first byte to decide the instruction length and the number of subsequent bytes to be treated as instruction data. The queue is updated after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently executing the fetched instructions.

The next byte after the instruction is completed is again the first opcode byte of the next instruction. A similar procedure is repeated till the complete execution of the program. The fetch operation of the next instruction is overlapped with the execution of the current instruction. As in the architecture, there are two separate units, namely Execution unit and Bus interface unit.

While the execution unit is busy in executing an instruction, after it is completely decoded, the bus interface unit may be fetching the bytes of the next instruction from memory, depending upon the queue status.

QS1 QS0 0 0 1 1

0 1 0 1

Indication No Operation First Byte of the opcode from the queue Empty Queue Subsequent Byte from the Queue

RQ/GT0, RQ/GT1 Request/Grant : These pins are used by

the other local bus master in maximum mode, to force the processor to release the local bus at the end of the processor current bus cycle.

Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins have internal pull-up resistors and may be left unconnected. Request/Grant sequence is as follows:

1.A pulse of one clock wide from another bus master requests the bus access to 8086. 2.During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter the hold acknowledge state at next cycle. The CPU bus interface unit is likely to be disconnected from the local bus of the system. 3.A one clock wide pulse from the another master indicates to the 8086 that the hold request is about to end and the 8086 may regain control of the local bus at the next clock cycle. Thus each master to master exchange of the local bus is a sequence of 3 pulses. There must be at least one dead clock cycle after each bus exchange. The request and grant pulses are active low.For the bus request those are received while 8086 is performing memory or I/O cycle, the granting of the bus is governed by the rules as in case of HOLD and HLDA in minimum mode.

Architecture of 8086 or Functional Block diagram of 8086

8086 has two blocks Bus Interfacing Unit (BIU) and Execution Unit (EU).

The BIU performs all bus operations such as instruction fetching, reading and writing operands for memory and calculating the addresses of the memory operands. The instruction bytes are transferred to the instruction queue.

EU executes instructions from the instruction system byte queue. Both units operate asynchronously to give the 8086 an overlapping instruction fetch and execution mechanism which is called as Pipelining. This results in efficient use of the system bus and system performance.

BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.

EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,Flag register.

BUS INTERFACE UNIT:

It provides a full 16 bit bidirectional data bus and 20 bit address bus. The bus interface unit is responsible for performing all external bus operations.

Specifically it has the following functions: Instruction fetch, Instruction queuing, Operand fetch and storage, Address relocation and Bus control.

The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the BIU is not full, it has room for at least

two more bytes and at the same time the EU is not requesting it to read or write operands from memory, the BIU is free to look ahead in the program by prefetching the next sequential instruction.

These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches two instruction bytes in a single memory cycle.

After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to the empty location nearest the output.

The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. If the queue is full and the EU is not requesting access to operand in memory.

These intervals of no bus activity, which may occur between bus cycles are known as Idle state.

If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle.

The BIU also contains a dedicated adder which is used to generate the 20bit physical address that is output on the address bus. This address is formed by adding an appended 16 bit segment address and a 16 bit offset address.

For example: The physical address of the next instruction to be fetched is formed by combining the current contents of the code segment CS register and the current contents of the instruction pointer IP register.

The BIU is also responsible for generating bus control signals such as those for memory read or write and I/O read or write.

EXECUTION UNIT

The Execution unit is responsible for decoding and executing all instructions.

The EU extracts instructions from the top of the queue in the BIU, decodes them, generates operands if necessary, passes them to the BIU and requests it to perform the read or write bys cycles to memory or I/O and perform the operation specified by the instruction on the operands.

During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction.

If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue.

When the EU executes a branch or jump instruction, it transfers control to a location corresponding to another set of sequential instructions.

Whenever this happens, the BIU automatically resets the queue and then begins to fetch instructions from this new location to refill the queue.

Minimum Mode Interface

When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface.

The minimum mode signal can be divided into the following basic groups :

1. Address/data bus 2. Status 3. Control 4. Interrupt and 5. DMA. Each and every group is explained clearly.

Address/Data Bus :

These lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space. More over it has an independent I/O address space which is 64K bytes in length.

The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles.

D15 is the MSB and D0 LSB. When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller.

Status signal:

The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3. These status bits are output on the bus at the same time that data are transferred over the other bus lines.

Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers are used to generate the physical address that was output on the address bus during the current bus cycle.Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address.

Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level.
S4 0 0 1 1 S3 0 1 0 1 Segment Register Extra Stack Code / none Data

Memory segment status codes

Control Signals :

The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus.

ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.

Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These lines also serves a second function, which is as the S7 status line.

Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. The logic level of M/IO tells external circuitry whether a

memory or I/O transfer is taking place over the bus. Logic 1 at this output signals a memory operation and logic 0 an I/O operation.

The direction of data transfer over the bus is signaled by the logic level output at DT/R. When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written into memory or output to an I/O device. On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port.

The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus.

On the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read operations, one other control signal is also supplied. This is DEN ( data enable) and it signals external devices when they should put data on the bus. There is one other control signal that is involved with the memory and I/O interface. This is the READY signal.

READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by the memory or I/O sub-system to signal the 8086 when they are ready to permit the data transfer to be completed.

Interrupt signals :

The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge ( INTA). INTR is an input to the 8086 that can be used by an external device to signal that it need to be serviced. Logic 1 at INTR represents an active interrupt request. When an interrupt request has been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA output.

The TEST input is also related to the external interrupt interface. Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input.

If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086 no longer executes instructions, instead it repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0.

As TEST switches to 0, execution resume with the next instruction in the program. This feature can be used to synchronize the operation of the 8086 to an event in external hardware.

There

are

two

more

inputs

in

the

interrupt

interface:

the

nonmaskable interrupt NMI and the reset interrupt RESET. On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service routine. The RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service routine.

DMA Interface signals :

The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signals. When an external device wants to take control of the system bus, it signals to the 8086 by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state.

The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 level.

Maximum Mode Interface

When the 8086 is set for the maximum-mode configuration, it provides signals for implementing a multiprocessor / coprocessor system environment.

By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program.

Usually in this type of system environment, there are some system resources that are common to all processors.They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources.

Coprocessor also means that there is a second processor in the system. In this two processor does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation.

In the maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor .

8288 Bus Controller Bus Command and Control Signals:

8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfaces.

Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow.

S2S1S0 are input to the external bus controller device, the bus controller generates the appropriately timed command and control signals.

S2 S1 S0 0 0 0 0 1 1 1 1

Indication Interrupt Acknowledge Read I/O port Write I/O port Halt Instruction Fetch Read Memory Write Memory Passive

8288 Command INTA IORC IOWC , AIOWC None MRDC MRDC MWTC, AMWC None

0 0 1

0 1 0

1 1 0 0 1 1 0 1 0 1

The 8288 produces one or two of these eight command signals for each bus cycles. For instance, when the 8086 outputs the code S2S1S0 equals 001, it indicates that an I/O read cycle is to be performed.

In the code 111 is output by the 8086, it is signaling that no bus activity is to take place. The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals provide the same functions as those described for the minimum system mode. This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems.

The output of 8289 are bus arbitration signals:

Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority in (BPRN), bus request (BREQ) and bus clock (BCLK).

They correspond to the bus exchange signals of the Multibus and are used to lock other processor off the system bus during the execution of an instruction by the 8086.

In this way the processor can be assured of uninterrupted access to common system resources such as global memory. Queue Status Signals : Two new signals that are produced by the 8086 in the maximum-mode system are queue status outputs QS0 and QS1. Together they form a 2-bit ueue status code, QS1QS0.

Following table shows the four different queue status. QS1 0 (low) 0 1 QS0 0 1 0 Queue Status Queue Empty. The queue has been reinitialized as a result of the execution of a transfer instruction. First Byte. The byte taken from the queue was the first byte of the instruction. Queue Empty. The queue has been reinitialized as a result of the execution of a transfer instruction. Subsequent Byte. The byte taken from the queue was a subsequent byte of the instruction.

Table - Queue status codes

Local Bus Control Signal Request / Grant Signals: In a maximum mode configuration, the minimum mode HOLD, HLDA interface is also changed. These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus access mechanism for accessing the local bus.

General purpose registers

The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer. It is divided into four groups. They are:

Four General purpose registers Four Index/Pointer registers Four Segment registers Two Other registers

General purpose registers :

Accumulator register consists of two 8-bit registers AL and AH, which

can be combined together and used as a 16-bit register AX. AL in this case contains the loworder byte of the word, and AH contains the highorder byte. Accumulator can be used for I/O operations and string manipulation.

Base register consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH contains the highorder byte. BX register usually contains a data pointer used for based, based indexed or register indirect addressing.

Count register consists of two 8-bit registers CL and CH, which can
be combined together and used as a 16-bit register CX. When combined, CL register contains the loworder byte of the word, and CH contains the high-order byte. Count register can be used in Loop, shift/rotate instructions and as a counter in string manipulation

Data register consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX. When combined, DL register contains the low order byte of the word, and DH contains the high-order byte. Data register can be used as a port number in I/O operations. In integer 32-bit multiply and divide instruction the DX register contains high-order word of the initial or resulting number.

Index or Pointer Registers

These registers can also be called as Special Purpose registers.

Stack Pointer (SP) is a 16-bit register pointing to program stack, ie it

is used to hold the address of the top of stack. The stack is maintained as a LIFO with its bottom at the start of the stack segment (specified by the SS segment register).Unlike the SP register, the BP can be used to specify the offset of other program segments.

Base Pointer (BP) is a 16-bit register pointing to data in stack

segment. It is usually used by subroutines to locate variables that were passed on the stack by a calling program. BP register is usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based

indexed and register indirect addressing, as well as a source data address in string manipulation instructions. Used in conjunction with the DS register to point to data locations in the data segment.

Destination Index (DI) is a 16-bit register. Used in conjunction with

the ES register in string operations. DI is used for indexed, based indexed and register indirect addressing, as well as a destination data address in string manipulation instructions. In short, Destination Index and SI Source Index registers are used to hold address.

Segment Registers
Most of the registers contain data/instruction offsets within 64 KB memory segment. There are four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1 MB of processor memory these 4 segments are located the processor uses four segment registers.

Code segment (CS) is a 16-bit register containing address of 64 KB

segment with processor instructions. The processor uses CS segment for all accesses to instructions referenced by instruction pointer (IP) register. CS register cannot be changed directly. The CS register is automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB

segment with program stack. By default, the processor assumes that all data referenced by the stack pointer (SP) and base pointer (BP) registers is located in the stack segment. SS register can be changed directly using POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB

segment with program data. By default, the processor assumes that all data referenced by general registers (AX, BX, CX, DX) and index register (SI, DI) is located in the data segment. DS register can be changed directly using POP and LDS instructions.

Extra segment (ES) used to hold the starting address of Extra

segment. Extra segment is provided for programs that need to access a second data segment. Segment registers cannot be used in arithmetic operations.

Other registers of 8086

Instruction Pointer (IP) is a 16-bit register. This is a crucially

important register which is used to control which instruction the CPU executes. The ip, or program counter, is used to store the memory location of the next instruction to be executed. The CPU checks the program counter to ascertain which instruction to carry out next. It then updates the program counter to point to the next instruction. Thus the program counter will always point to the next instruction to be executed.

Flag Register contains a group of status bits called flags that indicate
the status of the CPU or the result of arithmetic operations. There are two types of flags: 1. The status flags which reflect the result of executing an instruction. The programmer cannot set/reset theseflagsdirectly. 2. The control flags enable or disable certain CPU operations. The programmer can set/reset these bits to control the CPU's operation. Nine individual bits of the status register are used as control flags (3 of them) and status flags (6 of them).Theremaining7arenotused. A flag can only take on the values 0 and 1. We say a flag is set if it has the value 1.The status flags are used to record specific characteristics of arithmetic and of logical instructions.

Control Flags: There are three control flags

1. The Direction Flag (D): Affects the direction of moving data blocks by such instructions as MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can be set/reset by the STD (set D) and CLD (clear D) instructions. 2. The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts are actions initiated by hardware block such as input devices that will interrupt the normal execution of programs. The flag values are 0 = disable interrupts or 1 = enable interrupts and can be manipulated by the CLI (clear I) and STI (set I) instructions. 3. The Trap Flag (T): Determines whether or not the CPU is halted after the execution of each instruction. When this flag is set (i.e. = 1), the programmer can single step through his program to debug any errors. When this flag = 0 this feature is off. This flag can be set by the INT 3 instruction.

Status Flags: There are six status flags

1. The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is too large to fit in the destination register. This happens when there is an end carry in an addition operation or there an end borrows in a subtraction operation. A value of 1 = carry and 0 = no carry.

2. The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too large to fit in the destination register (i.e. when an overflow occurs). Overflow can occur when adding two numbers with the same sign (i.e. both positive or both negative). A value of 1 = overflow and 0 = no overflow. 3. The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is negative. This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 means negative and 0 = positive. 4. The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal to zero. A value of 1 means the result is zero and a value of 0 means the result is not zero. 5. The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to bit 4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no carry. 6. The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If the number of 1s is even its value = 1 and if the number of 1s is odd then its value = 0.

Addressing Modes of 8086

Definition: An instruction acts on any number of operands.The way an instruction accesses its operands is called its Addressing modes.
Operands may be of three types :
o o o

Implicit Explicit Both Implicit and Explicit.

Implicit operands mean that the instruction by definition has some

specific operands. The programmers do NOT select these operands.

Example: Implicit operands

XLAT ; automatically takes AL and BX as operands AAM ; it operates on the contents of AX.

Explicit operands mean the instruction operates on the operands specified by the programmer. Example: Explicit operands
MOV AX, BX; it takes AX and BX as operands XCHG SI, DI; it takes SI and DI as operands

Implicit and explicit operands Example: Implicit/Explicit operands

MUL BX; automatically multiply BX explicitly times AX

The location of an operand value in memory space is called the

Effective Address (EA)

We can classify the addressing modes of 8086 into four groups:

Immediate addressing Register addressing Memory addressing I/O port addressing

The first three Addresssing modes are clearly explained.

Immediate addressing mode & Register addressing mode

Immediate Addressing Mode
In this addressing mode, the operand is stored as part of the instruction. The immediate operand, which is stored along with the instruction, resides in the code segment -- not in the data segment. This addressing mode is also faster to execute an instruction because the operand is read with the instruction from memory. Here are some examples:

Example: Immediate Operands

MOV AL, 20 ; move the constant 20 into register AL ADD AX, 5 ; add constant 5 to register EAX MOV DX, offset msg ; move the address of message to register DX

Register addressing mode

In this addressing mode, the operands may be:

reg16: 16-bit general registers: AX, BX, CX, DX, SI, DI, SP or BP. reg8 : 8-bit general registers: AH, BH, CH, DH, AL, BL, CL, or DL. Sreg : segment registers: CS, DS, ES, or SS. There is an exception: CS cannot be a destination.

For register addressing modes, there is no need to compute the effective address. The operand is in a register and to get the operand there is no memory access involved.

Example: Register Operands

MOV AX, BX ; mov reg16, reg16 ADD AX, SI ; add reg16, reg16 MOV DS, AX ; mov Sreg, reg16

Some rules in register addressing modes: May not specify CS as the destination operand. Example: mov CS, 02h > wrong 2. Only one of the operands can be a segment register. You cannot move data from one segment register to another with a single mov instruction. To copy the value of cs to ds, would have to use some sequence like: Movds,cs->wrong movax,cs mov ds, ax -> the way we do it should never use the segment registers as data registers to hold arbitrary values. They should only contain segment addresses.

Immediate addressing mode & Register addressing mode

Immediate Addressing Mode

In this addressing mode, the operand is stored as part of the instruction. The immediate operand, which is stored along with the instruction, resides in the code segment -- not in the data segment. This addressing mode is also faster to execute an instruction because the operand is read with the instruction from memory. Here are some examples:

Example: Immediate Operands

MOV AL, 20 ; move the constant 20 into register AL ADD AX, 5 ; add constant 5 to register EAX MOV DX, offset msg ; move the address of message to register DX

Register addressing mode

In this addressing mode, the operands may be:

reg16: 16-bit general registers: AX, BX, CX, DX, SI, DI, SP or BP. reg8 : 8-bit general registers: AH, BH, CH, DH, AL, BL, CL, or DL. Sreg : segment registers: CS, DS, ES, or SS. There is an exception: CS cannot be a destination.

For register addressing modes, there is no need to compute the effective address. The operand is in a register and to get the operand there is no memory access involved.

Example: Register Operands

MOV AX, BX ; mov reg16, reg16 ADD AX, SI ; add reg16, reg16 MOV DS, AX ; mov Sreg, reg16

Some rules in register addressing modes: 1. may not specify CS as the destination operand. Example: mov CS, 02h > wrong 2. Only one of the operands can be a segment register. You cannot move data from one segment register to another with a single mov

instruction. To copy the value of cs to ds, you would have to use some sequence like: movds,cs->wrong movax,cs mov ds, ax -> the way we do it should never use the segment registers as data registers to hold arbitrary values. They should only contain segment addresses

Memory Addressing Modes

Memory (RAM) is the main component of a computer to store temporary data and machine instructions. In a program, programmers many times need to read from and write into memory locations. There are different forms of memory addressing modes 1.DirectAddressing 2.Registerindirectaddressing 3.Basedaddressing 4.Indexedaddressing 5.Basedindexedaddressing 6. Based indexed with displacement

Direct Addressing Mode & Register Indirect Addressing Mode

Direct Addressing Mode
The instruction mov al,ds:[8088h] loads the AL register with a copy of the byte at memory location 8088h. Likewise, the instruction mov ds: [1234h],dl stores the value in the dl register to memory location 1234h. By default, all displacement-only values provide offsets into the

data segment. If you want to provide an offset into a different segment, you must use a segment override prefix before your address. For example, to access location 1234h in the extra segment (es) you would use an instruction of the form mov ax,es:[1234h]. Likewise, to access this location in the code segment you would use the instruction mov ax, cs:[1234h]. The ds: prefix in the previous examples is not a segment override.

The instruction mov al,ds:[8088h] is same as mov al, [8088h]. If not mentioned DS register is taken by default.

Register Indirect Addressing Mode

The 80x86 CPUs let you access memory indirectly through a register using the register indirect addressing modes. There are four forms of this addressing mode on the 8086, best demonstrated by the following instructions: moval,[bx] moval,[bp] moval,[si] mov al, [di]

Code Example

MOVBX,100H MOV AL, [BX]

The [bx], [si], and [di] modes use the ds segment by default. The [bp] addressing mode uses the stack segment (ss) by default. You can use the segment override prefix symbols if you wish to access data in different segments. The following instructions demonstrate the use of these overrides: moval,cs:[bx] moval,ds:[bp] moval,ss:[si] mov al, es:[di] Intel refers to [bx] and [bp] as base addressing modes and bx and bp as base registers (in fact, bp stands for base pointer). Intel refers to the [si] and [di] addressing modes as indexed addressing modes (si stands for source index, di stands for destination index). However, these addressing modes are functionally equivalent. This text will call these forms register indirect modes to be consistent.

Based Addressing Mode and Indexed Addressing Modes

Based Addressing Mode
8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the resulting value is a pointer to location where data resides. Moval,[bx],[si] Movbl,[bp],[di] Mov cl , [bp],[di]

Code Example
Ifbx=1000hsi=0880h MovAL,[1000+880] Mov AL,[1880]

Indexed Addressing Modes

The indexed addressing modes use the following syntax: moval,[bx+disp] moval,[bp+disp] moval,[si+disp] mov al, [di+disp]

Code Example
MOVBX,100H MOVAL,[BX+15] MOV AL, [BX + 16] If bx contains 1000h, then the instruction mov cl, [bx+20h] will load cl from memory location ds:1020h. Likewise, if bp contains 2020h, mov dh, [bp+1000h] will load dh from location ss:3020. The offsets generated by these addressing modes are the sum of the constant and the specified register. The addressing modes involving bx, si, and di all use the data segment, the [bp+disp] addressing mode uses the stack

segment by default. As with the register indirect addressing modes, you can use the segment override prefixes to specify a different segment: moval,ss:[bx+disp] moval,es:[bp+disp] moval,cs:[si+disp] mov al, ss:[di+disp]

Example: MOV AX, [DI + 100]

Based Indexed Addressing Modes & Based Indexed Plus Displacement Addressing Mode
Based Indexed Addressing Modes
The based indexed addressing modes are simply combinations of the register indirect addressing modes. These addressing modes form the offset by adding together a base register (bx or bp) and an index register (si or di). The allowable forms for these addressing modes are: moval,[bx+si] moval,[bx+di] moval,[bp+si] mov al, [bp+di]

Code Example
MOVBX,100H MOVSI,200H MOVAL,[BX+SI] INCBX INC SI

Suppose that bx contains 1000h and si contains 880h. Then the instruction mov al,[bx][si] would load al from location DS:1880h. Likewise, if bp contains 1598h and di contains 1004, mov ax,[bp+di] will load the 16 bits in ax from locations SS:259C and SS:259D. The addressing modes that do not involve bp use the data segment by default. Those that have bp as an operand use the stack segment by default.

Based Indexed Plus Displacement Addressing Mode

These addressing modes are a slight modification of the base/indexed addressing modes with the addition of an eight bit or sixteen bit constant. The following are some examples of these addressing modes moval,disp[bx][si] moval,disp[bx+di] moval,[bp+si+disp] mov al, [bp][di][disp]

Code Example
MOVBX,100H MOVSI,200H MOVAL,[BX+SI+100H] INCBX INC SI

8086 Instruction Set and its Classification

The instructions of 8086 are classified into SIX groups. They are: 1. DATA TRANSFER INSTRUCTIONS 2. ARITHMETIC INSTRUCTIONS 3. BIT MANIPULATION INSTRUCTIONS 4. STRING INSTRUCTIONS 5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS 6. PROCESS CONTROL INSTRUCTIONS

1.DATA TRANSFER INSTRUCTIONS

The DATA TRANSFER INSTRUCTIONS are those, which transfers the DATA from any one source to any one destination.The datas may be of any type. They are again classified into four groups.They are:
GENERAL PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS MOV PUSH POP XCHG XLAT SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION SPECIAL ADDRESS TRANSFER INSTRUCTION LEA LDS LES FLAG TRANSFER INSTRUCTIONS LAHF SAHF PUSHF POPF

IN OUT

2.ARITHMETIC INSTRUCTIONS
These instructions are those which are useful to perform Arithmetic calculations, such as addition, subtraction, multiplication and division.They are again classified into four groups.They are:
ADDITION INSTRUCTIONS ADD ADC INC AAA DAA SUBTRACTION INSTRUCTIONS SUB SBB DEC NEG CMP AAS DAS MULTIPLICATION INSTRUCTIONS MUL IMUL AAM DIVISION INSTRUCTIONS DIV IDIV AAD CBW CWD

3.BIT MANIPULATION INSTRUCTIONS

These instructions are used to perform Bit wise operations.

LOGICAL INSTRUCTIONS NOT AND OR XOR TEST

SHIFT INSTRUCTIONS SHL / SAL SHR SAR

ROTATE INSTRUCTIONS ROL ROR RCL RCR

4. STRING INSTRUCTIONS
The string instructions function easily on blocks of memory.They are user friendly instructions, which help for easy program writing and execution. They can speed up the manipulating code.They are useful in array handling, tables and records.
STRING INSTRUCTIONS REP REPE / REPZ REPNE / REPNZ MOVS / MOVSB / MOVSW COMPS / COMPSB / COMPSW SCAS / SCASB / SCASW LODS / LODSB / LODSW STOS / STOSB / STOSW

5.PROGRAM EXECUTION TRANSFER INSTRUCTIONS

These instructions transfer the program control from one address to other address. ( Not in a sequence). They are again classified into four groups.They are:
UNCONDITIONAL TRANSFER INSTRUCTIONS CALL RET JMP CONDITIONAL TRANSFER INSTRUCTIONS JA / JNBE JAE / JNB JB / JNAE JBE / JNA JC JE / JZ JG / JNLE JGE / JNL JL / JNGE JLE / JNG JNC JNE / JNZ JNO JNP / JPO JNS JO JP / JPE JS ITERATION CONTROL INSTRUCTIONS LOOP LOOPE / LOOPZ LOOPNE / LOOPNZ JCXZ INTERRUPT INSTRUCTIONS INT INTO IRET

6.PROCESS CONTROL INSTRUCTIONS

These instructions are used to change the process of the

Microprocessor. They change the process with the stored information. They are again classified into Two groups.They are:

FLAG SET / CLEAR INSTRUCTIONS STC CLC CMC STD CLD STI CLI

EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS HLT WAIT ESC LOCK NOP

Complete 8086 Instruction set with clear Explanation and sample Programs
Click on each instruction to read its function,explanation and its sample Program. DATA TRANSFER INSTRUCTIONS
GENERAL PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS MOV PUSH POP XCHG XLAT/XLATB SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTION SPECIAL ADDRESS TRANSFER INSTRUCTION LEA LDS LES FLAG TRANSFER INSTRUCTIONS LAHF SAHF PUSHF POPF

IN OUT

ARITHMETIC INSTRUCTIONS
ADDITION INSTRUCTIONS ADD ADC INC AAA DAA SUBTRACTION INSTRUCTIONS SUB SBB DEC NEG CMP AAS DAS MULTIPLICATION INSTRUCTIONS MUL IMUL AAM DIVISION INSTRUCTIONS DIV IDIV AAD CBW CWD

BIT MANIPULATION INSTRUCTIONS

LOGICAL INSTRUCTIONS NOT AND OR XOR TEST SHIFT INSTRUCTIONS SHL / SAL SHR SAR ROTATE INSTRUCTIONS ROL ROR RCL RCR

STRING INSTRUCTIONS
STRING INSTRUCTIONS REP REPE / REPZ REPNE / REPNZ MOVS / MOVSB / MOVSW COMPS / COMPSB / COMPSW SCAS / SCASB / SCASW LODS / LODSB / LODSW STOS / STOSB / STOSW

PROGRAM EXECUTION TRANSFER INSTRUCTIONS

UNCONDITIONAL TRANSFER INSTRUCTIONS CALL RET JMP CONDITIONAL TRANSFER INSTRUCTIONS JA / JNBE JAE / JNB JB / JNAE JBE / JNA JC JE / JZ JG / JNLE JGE / JNL JL / JNGE JLE / JNG JNC JNE / JNZ JNO JNP / JPO JNS JO JP / JPE JS ITERATION CONTROL INSTRUCTIONS LOOP LOOPE / LOOPZ LOOPNE / LOOPNZ JCXZ INTERRUPT INSTRUCTIONS INT INTO IRET

PROCESS CONTROL INSTRUCTIONS

FLAG SET / CLEAR INSTRUCTIONS STC CLC CMC STD CLD STI CLI EXTERNAL HARDWARE SYNCHRONIZATION INSTRUCTIONS HLT WAIT ESC LOCK NOP

1.Addition of two 8-bit data: assume cs:code,ds:data data segment a db offh b db offh res dw 01 dup(?) data ends code segment start: mov ax,data mov ds,ax xor ax,ax mov al,a add al,b jnc next inc ah next: mov di,offset res mov [di],ax mov ah,4ch int 21h code ends end start end 2.Addition of two 16-bit data: assume cs:code,ds:data data segment a dw offffh b dw offffh res dw 02 dup(?) data ends code segment start: mov ax,data

mov ds,ax xor ax,ax mov bx,bx mov ax,a add ax,b jnc next inc bx next: mov di,offset res mov [di],ax mov [di+2],bx mov ah,4ch int 21h code ends end start end 3.Subtraction of two 8-bit data: assume cs:code,ds:data data segment a db oafh b db offh res dw 01 dup(?) data ends code segment start: mov ax,data mov ds,ax xor ax,ax mov al,a sub al,b jnc next inc ah neg al next: mov di,offset res mov [di],ax mov ah,4ch int 21h code ends

end start end

4.Subtraction of two 16 bit data: assume cs:code,ds:data data segment a dw oafffh b dw offffh res dw 02 dup(?) data ends code segment start: mov ax,data mov ds,ax xor ax,ax mov bx,bx mov ax,a sub ax,b jnc next inc bx neg ax next: mov di,offset res mov [di],ax mov [di+2],bx mov ah,4ch int 21h code ends end start end 5.Largest of n 16-bit numbers: assume cs:code,ds:data data segment list dw ............. count equ(100n-1) largest dw 01h dup(?)

data ends code segment start: mov ax,data mov ds,ax mov dl,count mov si,offset mov ax,[si] loop: cmp ax,[si+2] jnc next mov ax,[si+2] next: inc si dec dl jnz loop mov di,offset largest mov [di],ax mov ah,4ch int 21h code ends end start end 6.Smallest of n 16-bit data: assume cs:code,ds:data data segment list dw ............. count equ(100n-1) largest dw 01h dup(?) data eds code segment start: mov ax,data mov ds,ax mov dl,count mov si,offset mov ax,[si] loop: cmp ax,[si+2] jc next mov ax,[si+2]

next: inc si dec dl jnz loop mov di,offset largest mov [di],ax mov ah,4ch int 21h code ends end start end 7.Ascending order: assume cs:code,ds:data data segment list dw ............ count equ 10d data ends code segment start: mov ax,data mov ds,ax mov dx,count-1 again1: mov cx,dx mov si,offset list mov ax,[si] again: cmp ax,[si+2] jc next xchg [si+2],ax xchg [si],ax next: add si,02h loopz again (doubt) dec dx jnz again1 mov ah,4ch int 21h code ends end start end

8.Dcending order: assume cs:code,ds:data data segment list dw ............ count equ 10d data ends code segment start: mov ax,data mov ds,ax mov dx,count-1 again1: mov cx,dx mov si,offset list mov ax,[si] again: cmp ax,[si+2] jnc next xchg [si+2],ax xchg [si],ax next: add si,02h loopz again (check) dec dx jnz again1 mov ah,4ch int 21h code ends end start end

Assembler Directive Procedure Macros Interrupt and interrupt service routine BIOS Function call

Unit 3 MULTIPROCESSOR CONFIGURATION

Unit 4
I/O INTERFACING
MEMORY INTERFACING WITH 8085
The memory is made up of semiconductor material used to store the programs and data. Three types of memory is,
Process memory Primary or main memory Secondary memory

TYPICAL EPROM AND STATIC RAM:

A typical semiconductor memory IC will have n address pins, m data pins (or output pins).

Having two power supply pins (one for connecting required supply voltage (V and the other for connecting ground).

The control signals needed for static RAM are chip select (chip enable), read control (output enable) and write control (write enable).

The control signals needed for read operation in EPROM are chip select (chip enable) and read control (output enable).

DECODER: It is used to select the memory chip of processor during the execution of a program. No of IC's used for decoder is,
2-4 decoder (74LS139)

3-8 decoder (74LS138)

Table - Number of Address Pins and Data Pins in Memory ICs

Fig - Block diagram and Truth table of 3-8 decoder

Fig - Block diagram and Truth table of 2-4 decoder

EXAMPLE-1 Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processor.
The memory capacity is 64 Kbytes. i.e 2^n = 64 x 1000 bytes where n = address lines. So, n = 16. In this system the entire 16 address lines of the processor are connected to address input pins of memory IC in order to address the internal locations of memory. The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground). Since the processor is connected to EPROM, the active low RD pin is connected to active low output enable pin of EPROM. The range of address for EPROM is 0000H to FFFFH.

Fig - Interfacing 64Kb EPROM with 8085 EXAMPLE-2 Consider a system in which the available 64kb memory space is equally divided between EPROM and RAM. Interface the EPROM and RAM with 8085 processor.
Implement 32kb memory capacity of EPROM using single IC 27256. 32kb RAM capacity is implemented using single IC 62256. The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the processor are connected to 15 address pins of both EPROM and RAM. The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If A15 is 0, it select EPROM. Inverter is used for selecting the memory. The memory used is both Ram and EPROM, so the low RD and WR pins of processor are connected to low WE and OE pins of memory respectively. The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 8000H to FFFFH

Fig - Interfacing 32Kb EPROM and 32Kb RAM with 8085 EXAMPLE-3 Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor.
The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM. Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are connected to 13 address pins of all the memory. The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chip select signals. These four chip select signals can be used to select one of the four memory IC at any one time. The address line A15 is used as enable for decoder. The simplified schematic memory organization is shown.

Fig - Interfacing 16Kb EPROM and 16Kb RAM with 8085

The address allotted to each memory IC is shown in following table.

EXAMPLE-4 Consider a system in which the 64kb memory space is implemented using eight numbers of 8kb memory. Interface the EPROM and RAM with 8085 processor.
The total memory capacity is 64Kb. So, let 3 numbers of 8Kb EPROM and 5 numbers of 8Kb RAM. Each 8kb memory requires 13 address lines. So the address line A0 - A12 of the processor are connected to 13address pins of all the memory lCs. The address lines A13, A14 and A]5 are decoded using a 3-to-8 coder to generate eight chip select signals. These eight chip select signals can be used to select one of the eight memories at any one time. The memory interfacing is shown in following figure.

Fig - Interfacing 4 no.

The address allocation for Interfacing 4 no. 8Kb EPROM and 4 no. 8Kb RAM with 8085 is,

I/O INTERFACING WITH 8085

I/O STRUCTURE OF A TYPICAL MICROCOMPUTER: There are three major types of data transfer between the microcomputer and art I/O device. They are,
Programmed I/O : In programmed I/O the data transfer is accomplished through an I/O port and controlled by software. Interrupt driven I/O : In interrupt driven I/O, the I/O device will interrupt the processor, and initiate data transfer. Direct memory access (DMA) : In DMA, the data transfer between memory and I/O can be performed by bypassing the microprocessor.

INTERFACING I/O AND PERIPHERAL DEVICES: 1. For data transfer from input device to processor the following operations are performed.
The input device will load the data to the port. When the port receives a data, it sends message to the processor to read the data. The processor will read the data from the port. After a data have been read by the processor the input device will load the next data into the port.

2. For data transfer from processor to output device the following operations are performed.
The processor will load the data to the port. The port will send a message to the output device to read the data. The output device will read the data from the port. After the data have been read by the output device the processor can load the next data to the port. The various INTEL 110 port devices are 8212, 8155/8156, 8255, 8355 and 8755. 8212 The 8212 is a 24 pin IC. It consists of eight number of D-type latches. It has 8-input lines DI1 to DI8 and 8-output lines DO1 to DO8 The 8212 can be used as an input or output device It has two selecting device DS1 (low) and DS2.

If,
IO Interfacing Methods ..(Contd) - Page2

Fig - Internal address of 8155

8155:
It has two numbers of 8-bit parallel I/O port (port-A and B) One number of 6-bit parallel I/O port (port-C). It has 14 bit timer (operating in 4 modes). It has six internal addresses. It has one chip select pin CS (low).

8156: It has two numbers of 8-bit parallel I/O port (port-A and B) One number of 6-bit parallel 1 port (port-C). It has 14 bit timer (operating in 4 modes). It has six internal addresses. It has one chip select pin CS (low).

Fig - Internal address of 8156 8255:

It has 3 numbers of 8-bit parallel I/O ports (port A, B and C). Port-A can be programmed in mode-0 mode-1 or mode-2 as input or output port. Port-B can be programmed in mode-1 and mode-2 as 1/Oport. When ports A and B are in mode-0, the port-C can be used as I/O port. One logic low chip select (CS) pin. It requires four internal addresses

8355:
It It It It has has has has 2KB ROM. two number of 8 bit port (A,B). one CS(low). four internal addresses.

8755:
It It It It has has has has 2Kb EPROM. two number of 8 bit port (A,B). one CS(low). four internal addresses.

Fig - Internal address of 8255

Fig - Internal address of 8355

Fig - Internal address of 8755

There are two types for interfacing I/O devices: 1. Memory mapped I/O device. 1. Standard I/O mapped I/O device or isolated I/O mapping.

Example 1: A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255, one number of 8279, one number of 8251 and one number of 8254. (8255 - Programmable peripheral interface; 8279Keyboard/display controller, 8251 - USART and 8254 - Timer). Draw the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O mapped.
The I/O devices in the system should be mapped by standard I/O mapping. Hence separate decoders can be used to generate chip select signals for memory IC and peripheral IC's. For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM. For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM. The 8kb memories require 13 address lines. Hence the address lines A0 - A12 are used for selecting the memory locations. The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low) of 8085, so that this decoder is enabled for memory read/write operation. The other enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of the decoder are used to select memory lCs and the remaining 4 are kept for future expansion. The EPROM is mapped in the beginning of memory space from 0000H to 3FFF. The RAM is mapped at the end of memory space from C000 to FFFFH. There are five peripheral IC's to be interfaced to the system. The chip-select signals for these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to this decoder is A11, A12 and A13 The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O decoder. The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this decoder is enabled for I/O read/write operation.

Fig - Memory and I/O Port Interfacing with 8085

The 16 bit address for the memory and 8255 devices are,

Example 2: A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255, one number of 8279, one number of 8251 and one number of 8254. (8255 - Programmable peripheral interface; 8279Keyboard/display controller, 8251 - USART and 8254 - Timer). Draw the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O mapped.

The I/O devices in the system should be mapped by standard I/O mapping. Hence separate decoders can be used to generate chip select signals for memory IC and peripheral IC's. For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM. For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM. The 8kb memories require 13 address lines. Hence the address lines A0 - A12 are used for selecting the memory locations. The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-to-8-deeoder) of memory IC. The logic low enables of this decoder are tied to IO/ M(low) of 8085, so that this decoder is enabled for memory read/write operation. The other enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of the decoder are used to select memory lCs and the remaining 4 are kept for future expansion. The EPROM is mapped in the beginning of memory space from 0000H to 3FFF. The RAM is mapped at the end of memory space from C000 to FFFFH. There are five peripheral IC's to be interfaced to the system. The chip-select signals for these IC's are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to this decoder is A11, A12 and A13 The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O decoder. The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this decoder is enabled for I/O read/write operation.

The 16 bit address for the memory and IO devices are

Fig - Memory and I/O Port Interfacing with 8085

Example 3: A system requires 8kb EPROM and 8kb RAM. Also the system has 2 numbers of 8155. Draw the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O mapped.

The IC 2764 (8k x 8) is selected for EPROM memory and IC 6264 (8k x 8) is selected for RAM memory. Both the memory IC has time compatibility with 8085 processor. The 8kb memory requires 13 address lines. Hence the address lines A0 - A12 are used to select memory locations. The RAM locations of 8155 are selected by address lines A0 to A7. 3-to-8 decoder, 74LS138 is used for generating chip select signals by decoding the address lines A13, A14 and A15. Eight bit addresses are allotted to ports of 8l55 and sixteen bit addresses are allotted to RAM memory locations of 8155.

The 16 bit address for the memory and IO devices are,

Fig - Memory and I/O Port Interfacing with 8085

PROGRAMMABLE PERIPHERAL INTERFACE - INTEL 8255 Pins, Signals and internal block diagram of 8255:

It has 40 pins and requires a single +5V supply.

The INTEL 8255 is a device used to parallel data transfer between processor and slow peripheral devices like ADC, DAC, keyboard, 7-segment display, LCD, etc.

The 8255 has three ports: Port-A, Port-B and Port-C.

Port-A can be programmed to work in any one of the three operating modes mode-0, mode-1 and mode-2 as input or output port.

Port-B can be programmed to work either in mode-0 or mode-1 as input or output port. Port-C (8-pins) has different assignments depending on the mode of port-A and port-B.

If port-A and B are programmed in mode-0, then the port-C can perform any one of the following functions.

As 8-bit parallel port in mode-0 for input or output.

As two numbers of 4-bit parallel ports in mode-0 for input or output.

The individual pins of port-C can be set or reset for various control applications.

If port-A is programmed in mode- 1/mode-2 and port-B is programmed in mode-1 then some of the pins of port-C are used for handshake signals and the remaining pins can be used as input/ output lines or individually set/reset for control applications.

The read/write control logic requires six control signals. These signals are given below.

1. RD (low): This control signal enables the read operation. When this signal is low, the microprocessor reads data from a selected I/O port of the 8255A. 2. WR (low): This control signal enables the write operation. When this signal goes low, the microprocessor writes into a selected I/O port or the control register. 3. RESET: This is an active high signal. It clears the control register and set all ports in the input mode. 4. CS (low), A0 and A1: These are device select signals. They are,

Interfacing of 8255 with 8085 processor:

A simple schematic for interfacing the 8255 with 8085 processor is shown in fig.

PIN DESCRIPTION - INTEL 8255

Block diagram of 8255:

The internal block diagram of 8255 is shown in fig:

The 8255 can be either memory mapped or I/O mapped in the system. In the schematic shown in above is I/O mapped in the system.

Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in this, the chip select IOCS- 1 is used to select 8255.

The address line A7 and the control signal IO/M (low) are used as enable for the decoder.

The address line A0 of 8085 is connected to A0 of 8255 and A1 of 8085 is connected to A1 of 8255 to provide the internal addresses.

The data lines D0-D7 are connected to D0-D7 of the processor to achieve parallel data transfer.

The I/O addresses allotted to the internal devices of 8255 are listed in table.

serial communication interface

INTERFACING WITH INTEL 8251A (USART)

The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication.

It supports the serial transmission of data.

It is packed in a 28 pin DIP.

Read/Write control logic:

The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.

It monitors the data flow.

This section has three registers and they are control register, status register and data buffer.

The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.

When C/D(low) is high, the control register is selected for writing control word or reading status word.

When C/D(low) is low, the data buffer is selected for read/write operation.

When the reset is high, it forces 8251A into the idle mode.

The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section:

The transmitter section accepts parallel data from CPU and converts them into serial data.

The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.

When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

If buffer register is empty, then TxRDY is goes to high.

If output register is empty then TxEMPTY goes to high.

The clock signal, TxC (low) controls the rate at which the bits are transmitted by the USART.

The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

The receiver section accepts serial data and convert them into parallel data

The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again.

If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

The CPU reads the parallel data from the buffer register.

When the input register loads a parallel data to buffer register, the RxRDY line goes high.

The clock signal RxC (low) controls the rate at which bits are received by the USART.

During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

This unit takes care of handshake signals for MODEM interface.

Block Diagram: The functional block diagram of 825 1A consists five sections. They are:

Read/Write control logic Transmitter Receiver Data bus buffer Modem control.

The functional block diagram is shown in fig:

Functional block diagram of 8251A-USART

The 825 1A can be either memory mapped or I/O mapped in the system.

8251A in I/O mapped in the system is shown in the figure.

Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 8251A.

The address line A7 and the control signal IO / M(low) are used as enable for decoder.

The address line A0 of 8085 is connected to C/D(low) of 8251A to provide the internal addresses.

The data lines D0 - D7 are connected to D0 - D7 of the processor to achieve parallel data transfer. The RESET and clock signals are supplied by the processor. Here the processor clock is directly connected to 8251A. This clock controls the parallel data transfer between the processor and 8251A.

The output clock signal of 8085 is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

The TTL logic levels of the serial data lines and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then terminated on a standard 9-pin D-.type connector.

In 8251A the transmission and reception baud rates can be different or same.

The device which requires serial communication with processor can be connected to this 9-pin D-type connector using 9-core cable

The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

I/O addresses of 8251A interfaced to 8085 is,

timer-keyboard/display controller

KEYBOARD/DISPLAY CONTROLLER - INTEL 8279

The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086/8088 microprocessor based system. The important features of 8279 are,
o o o o o o o

Simultaneous keyboard and display operations. Scanned keyboard mode. Scanned sensor mode. 8-character keyboard FIFO. 1 6-character display. Right or left entry 1 6-byte display RAM. Programmable scan timing.

The four major sections of 8279 are keyboard, scan, display and CPU interface.

Keyboard section:

The keyboard section consists of eight return lines RL0 - RL7 that can be used to form the columns of a keyboard matrix. It has two additional input : shift and control/strobe. The keys are automatically debounced. The two operating modes of keyboard section are 2-key lockout and N-key rollover. In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized. In the N-key rollover mode simultaneous keys are recognized and their codes are stored in FIFO. The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM. The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,

Functional block diagram

KEYBOARD AND DISPLAY INTERFACE USING 8279 o

Block diagram of 8279:

The functional block diagram of 8279 is shown.

In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor.

Display section:

The display section has eight output lines divided into two groups A0-A3 and B0-B3. The output lines can be used either as a single group of eight lines or as two groups of four lines, in conjunction with the scan lines for a multiplexed display. The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs. The cathodes are connected to scan lines through driver transistors. The display can be blanked by BD (low) line. The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM.

Scan section:

The scan section has a scan counter and four scan lines, SL0 to SL3. In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder. In encoded scan mode, the output of scan lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output. The scan lines are common for keyboard and display. The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a multiplexed display, to turn ON/OFF.

CPU interface section:

The CPU interface section takes care of data transfer between 8279 and the processor. This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and CPU. It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control register of8279. The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279. It has an interrupt request line IRQ, for interrupt driven data transfer with processor. The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler.

The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.

Programming the 8279:

The 8279 can be programmed to perform various functions through eight command words.

In a microprocessor b system, when keyboard and 7-segment LED display is interfaced using ports or latches then the processor has to carry the following task.

Keyboard scanning Key debouncing Key code generation Sending display code to LED Display refreshing

Interfacing 8279 with 8085 processor:

A typical Hexa keyboard and 7-segment LED display interfacing circuit using 8279 is shown.

The circuit can be used in 8085 microprocessor system and consist of 16 numbers of hexa-keys and 6 numbers of 7-segment LEDs.

The 7-segment LEDs can be used to display six digit alphanumeric character.

The 8279 can be either memory mapped or I/O mapped in the system. In the circuit shown is the 8279 is I/O mapped.

The address line A0 of the system is used as A0 of 8279.

The clock signal for 8279 is obtained by dividing the output clock signal of 8085 by a clock divider circuit.

The chip select signal is obtained from the I/O address decoder of the 8085 system. The chip select signals for I/O mapped devices are generated by using a 3-to-8 decoder.

The address lines A4, A5 and A6 are used as input to decoder.

The address line A7 and the control signal IO/M (low) are used as enable for decoder.

The chip select signal IOCS-3 is used to select 8279.

The I/O address of the internal devices of 8279 are shown in table.

The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in encoded scan. (Because in decoded scan, only 4 numbers of 7-segment LEDs can be interfaced)

In encoded scan the output of scan lines will be binary count. Therefore an external, 3-to-8 decoder is used to decode the scan lines SL0, SL1 and SL2 of 8279 to produce eight scan lines S0 to S7.

The decoded scan lines S0 and S1 are common for keyboard and display.

The decoded scan lines S2 to S5 are used only for display and the decoded scan lines S6 and S7 are not used in the system.

Anode and Cathode drivers are provided to take care of the current requirement of LEDs.

The pnp transistors, BC 158 are used as driver transistors.

The anode drivers are called segment drivers and cathode drivers are called digit drivers.

The 8279 output the display code for one digit through its output lines (OUT A0 to OUT A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

The display code is inverted by segment drivers and sent to segment bus.

The scan code is decoded by the decoder and turns ON the corresponding digit driver. Now one digit of the display character is displayed. After a small interval (10 milli-second, typical), the display is turned OFF (i.e., display is blanked) and the above process is repeated for next digit. Thus multiplexed display is performed by 8279.

The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as columns and decoded scan lines S0 and S1 as rows.

A hexa key is placed at the crossing point of each row and column. A key press will short the row and column. Normally the column and row line will be high.

During scanning the 8279 will output binary count on SL0 to SL3, which is decoded by decoder to make a row as zero. When a row is zero the 8279 reads the columns. If there is a key press then the corresponding column will be zero.

If 8279 detects a key press then it wait for debounce time and again read the columns to generate key code.

In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key press. The keycode consist of the binary value of the column and row in which the key is found and the status of shift and control key.

After a scan time, the next row is made zero and the above process is repeated and so on. Thus 8279 continuously scan the keyboard.

interrupt controller

PROGRAMMABLE INTERRUPT CONTROLLER - INTEL 8259

FEATURES OF 8259: 1. It is programmed to work with either 8085 or 8086 processor. 2. It manage 8-interrupts according to the instructions written into its control registers. 3. In 8086 processor, it supplies the type number of the interrupt and the type number is programmable. In 8085 processor, the interrupt vector address is programmable. The priorities of the interrupts are programmable. 4. The interrupts can be masked or unmasked individually. 5. The 8259s can be cascaded to accept a maximum of 64 interrupts. FUNCTIONAL BLOCK DIAGRAM OF 8259: It has eight functional blocks. They are, 1. 1. 1. 1. 1. 1. 1. 1. Control logic Read Write logic Data bus buffer Interrupt Request Register (IRR) In-Service Register (ISR) Interrupt Mask Register (IMR) Priority Resolver (PR) Cascade buffer.

The data bus and its buffer are used for the following activities.

1. The processor sends control word to data bus buffer through D0D7.

1. The processor read status word from data bus buffer through D0D7

1. From the data bus buffer the 8259 send type number (in case of 8086) or the call opcode and address (in case of 8085) through D0-D7 to the processor.

The processor uses the RD (low), WR (low) and A0 to read or write 8259.

The 8259 is selected by CS (low).

The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go high, the request is stored in IRR. It registers a request only if the interrupt is unmasked.

Normally IR0 has highest priority and IR7 has the lowest priority. The priorities of the interrupt request input are also programmable.

First the 8259 should be programmed by sending Initialization Command Word (ICW) and Operational Command Word (OCW). These command words will inform 8259 about the following,

1. 1. 1. 1. 1. 1.

Type of interrupt signal (Level triggered / Edge triggered). Type of processor (8085/8086). Call address and its interval (4 or 8) Masking of interrupts. Priority of interrupts. Type of end of interrupts.

The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be masked. The relevant information is send by the processor through OCW.

The in-service register keeps track of which interrupt is currently being serviced.

The priority resolver examines the interrupt request, mask and in-service registers and determines whether INT signal should be sent to the processor or not.

The cascade buffer/comparator is used to expand the interrupts of 8259.

In cascade connection one 8259 will be directly interrupting 8086 and it is called master 8259.

To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be connected. The 8259s interrupting the master 8259 are called slave 8259s.

Each 8259 has its own addresses so that each 8259 can be programmed independently by sending command words and independently the status bytes can be read from it.

Functional block diagram

CASCADING OF 8259 & INTERFACING OF 8259 WITH 8085

The cascade pins (CAS0, CAS1 and CAS2) from the master are connected to the corresponding pins of the slave.

For the slave 8259, the SP (low) / EN (low) pin is tied low to let the device know that it is a slave.

The SP (low) / EN (low) pin can be used as input or output signal.

In non-buffered mode it is used as input signal and tied to logic-I in master 8259 and logic-0 in slave 8259.

In buffered mode it is used as output signal to disable the data buffers while data is transferred from 8259A to the CPU.

It requires two internal address and they are A =0 or A = 1.

It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085 is shown in figure is I/O mapped in the system.

The low order data bus lines D0-D7 are connected to D0-D7 of 8259.

The address line A0 of the 8085 processor is connected to A0 of 8259 to provide the internal address.

The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for 8259.

The address lines A4, A5 and A6 are used as input to decoder.

The control signal IO/M (low) is used as logic high enables for decoder and the address line A7 is used as logic low enable for decoder.

The I/O addresses of 8259 are shown in table.

Fig - Cascade Connection of 8259 INTERFACING 8259 WITH 8085 MICROPROCESSOR CASCADING 8259:

Working of 8259 with 8085 processor:

First the 8259 should be programmed by sending Initialization Command Word (ICW) and Operational Command Word (OCW). These command words will inform 8259 about the following,

1. 1. 1. 1. 1. 1.

Type of interrupt signal (Level triggered / Edge triggered). Type of processor (8085/8086). Call address and its interval (4 or 8) Masking of interrupts. Priority of interrupts. Type of end of interrupts.

Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any one of the interrupt lines IR0-IR7 it checks for its priority and also checks whether it is masked or not.

If the previous interrupt is completed and if the current request has highest priority and unmasked, then it is serviced.

For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085.

In response it expects an acknowledge INTA (low) from the processor.

When the processor accepts the interrupt, it sends three INTA (low) one by one.

In response to first, second and third INTA (low) signals, the 8259 will supply CALL opcode, low byte of call address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and load the CALL address in PC and start executing the interrupt service routine stored in this call address.

DMA controller (8237)

PROGRAMMABLE DMA CONTROLLER - INTEL 8257

It is a device to transfer the data directly between IO device and memory without through the CPU. So it performs a high-speed data transfer between memory and I/O device.

The features of 8257 is,

The 8257 has four channels and so it can be used to provide DMA to four I/O devices

Each channel can be independently programmable to transfer up to 64kb of data by DMA.

Each channel can be independently perform read transfer, write transfer and verify transfer.

It is a 40 pin IC and the pin diagram is,

Functional Block Diagram of 8257:

The functional blocks of 8257 are data bus buffer, read/write logic, control logic, priority resolver and four numbers of DMA channels.

The functional block diagram of 8257 is shown in fig.

Functional block diagram

Each channel of 8257 Block diagram has two programmable 16bit registers named as address register and count register.

Address register is used to store the starting address of memory location for DMA data transfer.

The address in the address register is automatically incremented after every read/write/verify transfer.

The count register is used to count the number of byte or word transferred by DMA. The format of count register is,

14-bits B0-B13 is used to count value and a 2-bits is used for indicate the type of DMA transfer (Read/Write/Veri1 transfer).

In read transfer the data is transferred from memory to I/O device.

In write transfer the data is transferred from I/O device to memory.

Verification operations generate the DMA addresses without generating the DMA memory and I/O control signals.

The 8257 has two eight bit registers called mode set register and status register. The format of mode set register is,

The use of mode set register is, 1. Enable/disable a channel. 2. Fixed/rotating priority

3. Stop DMA on terminal count. 4.Extended/normal write time. 5. Auto reloading of channel-2.

The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1, 2 and 3 respectively. A one in these bit position will enable a particular channel and a zero will disable it.

If the bit B4 is set to one, then the channels will have rotating priority and if it zero then the channels wilt have fixed priority.

1. In rotating priority after servicing a channel its priority is made as lowest. 2. In fixed priority the channel-0 has highest priority and channel-2 has lowest priority.

If the bit B5 is set to one, then the timing of low write signals (MEMW and IOW) will be extended.

If the bit B6 is set to one then the DMA operation is stopped at the terminal count.

The bit B7 is used to select the auto load feature for DMA channel-2.

When bit B7 is set to one, then the content of channel-3 count and address registers are loaded in channel-2 count and address registers respectively whenever the channel-2 reaches terminal count. When this mode is activated the number of channels available for DMA reduces from four to three. The format of status register of 8257 is shown in fig.

The bit B0, B1, B2, and B3 of status register indicates the terminal count status of channel-0, 1,2 and 3 respectively. A one in these bit positions indicates that the particular channel has reached terminal count.

These status bits are cleared after a read operation by microprocessor.

The bit B4 of status register is called update flag and a one in this bit position indicates that the channel-2 register has been reloaded from channel-3 registers in the auto load mode of operation.

The internal addresses of the registers of 8257 are listed in table.

A simple schematic for interfacing the 8257 with 8085 processor is shown.

The 8257 can be either memory mapped or I/O mapped in the system.

In the schematic shown in figure is I/O mapped in the system.

Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0 to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.

The address line A7 and the control signal IO/M (low) are used as enable for decoder.

The D0-D7 lines of 8257 are connected to data bus lines D0-D7 for data transfer with processor during programming mode.

These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15 during the DMA mode.

The 8257 also supply two control signals ADSTB and AEN to latch the address supplied by it during DMA mode on external latches.

Two 8-bit latches are provided to hold the 16-bit memory address during DMA mode. During DMA mode, the AEN signal is also used to disable the buffers and latches used for address, data and control signals of the processor.

The 8257 provide separate read and write control signals for memory and I/O devices during DMA.

Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by a suitable logic circuit to generate separate read and write control signals f memory and I/O devices.

The output clock of 8085 processor should be inverted and supplied to 8257 clock input for proper operation.

The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD request to the processor.

The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the acknowledge signal from the processor once the HOLD request is accepted.

The RESET OUT of 8085 processor is connected to RESET of 8257.

The I/O addresses of the internal registers of 8257 are listed in table.

applications stepper motor temperature control.

Unit 5 MICROCONTROLLERS
Architecture of 8051 Microcontroller

The 8051 Microcontroller

8051 Microcontroller

Architecture

8051c is a 8bit microcontroller introduced by Intel Corporation in 1981 which comes in 40 pin dual inline package (DIP).

It has 4KB of inbuilt ROM i.e onchip program space.

It has 128bytes of inbuilt RAM space and if required external memory of 64KB can be interfaced to the microcontroller.

There are 4 parallel 8bit ports namely port 0, port 1, port 2 and port 3 which are addressable as well as programmable.

It has an onchip crystal oscillator with crystal frequency 11.0592MHz (~12MHz).

It has full duplex serial I/O port having two pins namely TxD, RxD.

It has two 16bit timers namely Timer 0 and Timer 1 which can be used either as timer for internal operation or as counter for external operation.

It has five interrupt sources. All of them are maskable as well as vector interrupts. They are External Interrupt 0, Timer Interrupt 0, External Interrupt 1, Timer Interrupt 1, Serial Port Interrupt.

The programming mode of this microcontroller consists of general purpose registers (GPRs), Special Purpose Registers (SPRs) and Special Function Registers (SFRs).

The instruction set of 8051 c consists of more number of bit manipulations or boolean variable manipulation group of instructions. The instructions are very much useful to manipulate SFR bits and also port pins.

Register and Internal RAM organization 8051 c provides two 8bit general purpose registers A (Accumulatr) and B. It provides 4 special purpose registers 16bit Program Counter (PC), 8bit Stack Pointer (SP), 16bit Data Pointer and 8bit Program Status Word (PSW).

It also provides few Special Function Registers. They are TMOD, TCON, IE, IP, SBUF, SCON, PCON. The 128bytes onchip RAM of 8051 c is divided into three portions as given below. o 00H 1FH : These 32bytes are arranged as 4 register banks namely Bank 0, Bank 1, Bank 2, Bank 3 where each bank consists of 8 registers namely R0

through R7. 20H 2FH : These 16bytes (128bits) are made available as bitaddressible.bytes. o 30H 7FH : These 80 bytes are available as scratch-pad RAM bytes.

Power Supply pins 8051 c works with +5V DC source applied to Vcc and 0V to Gnd input pin. It has an onchip crystal clock generator. As such it must be supported externally by connecting a crystal across crystal input XTAL1, XTAL2. It has active hign reset input pin. As such the controller is said to be reset upon application of active hign pulse. I/O port pins A total number of 32 I/O pins are provided as port pins divided into 4 ports port 0, port 1, port 2 and port 3. All ports are both byte and bit addressable. All ports are programmable. All the ports act as simple input/output ports. All the ports except port 1 offer alternate functions. They are as follows. Port 0 and Port 2: If input pin is grounded then port 0 acts as lower order 8bit address data bus where as port 2 acts as higher order 8 bit address bus. Port 3: Each and every pin in this port offer some separate functionality irrespective of level at input pin. Pin Special Function P3.0 RxD (Serial Input pin) P3.1 TxD (Serial Output pin) P3.2 (Interrupt 0 input pin) P3.3 (Interrupt 1 input pin) P3.4 (Timer 0 input if timer is counter) P3.5 (Timer 1 input if timer is counter) P3.6 (RAM write control signal output)

8051 Instructions 8051 has about 111 instructions. These can be grouped into the following categories 1. 2. 3. 4. 5. Arithmetic Instructions Logical Instructions Data Transfer instructions Boolean Variable Instructions Program Branching Instructions

The following nomenclatures for register, data, address and variables are used while write instructions. A: Accumulator B: "B" register C: Carry bit Rn: Register R0 - R7 of the currently selected register bank

Direct: 8-bit internal direct address for data. The data could be in lower 128bytes of RAM (00 - 7FH) or it could be in the specia function register (80 - FFH). @Ri: 8-bit external or internal RAM address available in register R0 or R1. This is used for indirect addressing mode. #data8: Immediate 8-bit data available in the instruction. #data16: Immediate 16-bit data available in the instruction.

Addr11: 11-bit destination address for short absolute jump. Used by instructions AJMP & ACALL. Jump range is 2 kbyte (one page) Addr16: 16-bit destination address for long call or long jump. Rel: 2's complement 8-bit offset (one - byte) used for short jump (SJMP) and all conditional jumps. bit: Directly addressed bit in internal RAM or SFR Arithmetic Instructions Mnemonics ADD A, Rn ADD A, direct ADD A, @Ri ADD A, #data ADDC A, Rn ADDC A, direct ADDC A, @Ri ADDC A, #data DA A DIV AB Description A A + Rn A A + (direct) A A + @Ri A A + data A A + Rn + C A A + (direct) + C A A + @Ri + C A A + data + C Decimal adjust accumulator Divide A by B A quotient B remainder A A -1 Rn Rn - 1 (direct) (direct) - 1 @Ri @Ri - 1 A A+1 Rn Rn + 1 (direct) (direct) + 1 Bytes 1 2 1 2 1 2 1 2 1 1 1 1 2 1 1 1 2 Instruction Cycles 1 1 1 1 1 1 1 1 1 4 1 1 1 1 1 1 1

DEC A DEC Rn DEC direct DEC @Ri INC A INC Rn INC direct

INC @Ri INC DPTR MUL AB

@Ri @Ri +1 DPTR DPTR +1 Multiply A by B A low byte (A*B) B high byte (A* B) A A A A A - Rn - C A - (direct) - C A - @Ri - C A - data - C

1 1 1

1 2 4

SUBB A, Rn SUBB A, direct SUBB A, @Ri SUBB A, #data Logical Instructions Mnemonics ANL A, Rn ANL A, direct ANL A, @Ri ANL A, #data ANL direct, A ANL direct, #data CLR A CPL A ORL A, Rn ORL A, direct ORL A, @Ri ORL A, #data ORL direct, A ORL direct, #data RL A RLC A RR A RRC A SWAP A XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data Data Transfer Instructions Mnemonics MOV A, Rn MOV A, direct MOV A, @Ri MOV A, #data MOV Rn, A MOV Rn, direct MOV Rn, #data MOV direct, A MOV direct, Rn MOV direct1, direct2 MOV direct, @Ri MOV direct, #data

1 2 1 2

1 1 1 1

Description A AND Rn A A AND (direct) A A AND @Ri A A AND data (direct) (direct) AND A (direct) (direct) AND data A 00H A A A A OR Rn A A OR (direct) A A OR @Ri A A OR data (direct) (direct) OR A (direct) (direct) OR data Rotate accumulator left Rotate accumulator left through carry Rotate accumulator right Rotate accumulator right through carry Swap nibbles within Acumulator A A EXOR Rn A A EXOR (direct) A A EXOR @Ri A A EXOR data (direct) (direct) EXOR A (direct) (direct) EXOR data A

Bytes 1 2 1 2 2 3 1 1 1 1 2 1 2 3 1 1 1 1 1 1 1 2 1 2 3

Instruction Cycles 1 1 1 1 1 2 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 2

Description A Rn A (direct) A @Ri A data Rn A Rn (direct) Rn data (direct) A (direct) Rn (direct1) (direct2) (direct) @Ri (direct) #data

Bytes 1 2 1 2 1 2 2 2 2 3 2 3

Instruction Cycles 1 1 1 1 1 2 1 1 2 2 2 2

MOV @Ri, A MOV @Ri, direct MOV @Ri, #data MOV DPTR, #data16 MOVC A, @A+DPTR MOVC A, @A+PC MOVC A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP direct XCH Rn XCH direct XCH @Ri XCHD A, @Ri Boolean Variable Instructions Mnemonics CLR C CLR bit SET C SET bit CPL C CPL bit ANL C, /bit ANL C, bit ORL C, /bit ORL C, bit MOV C, bit MOV bit, C Program Branching Instructions Mnemonics ACALL addr11 AJMP addr11 CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel DJNZ Rn, rel DJNZ direct, rel JC rel JNC rel JB bit, rel JNB bit, rel JBC bit, rel JMP @A+DPTR JZ rel JNZ rel

@Ri A @Ri (direct) @Ri data DPTR data16 A Code byte pointed by A + DPTR A Code byte pointed by A + PC A Code byte pointed by Ri 8-bit address) A External data pointed by DPTR @Ri A (External data - 8bit address) @DPTR A(External data - 16bit address) (SP) (direct) (direct) (SP) Exchange A with Rn Exchange A with direct byte Exchange A with indirect RAM Exchange least significant nibble of A with that of indirect RAM

1 2 2 3 1 1 1 1 1 1 2 2 1 2 1 1

1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1

Description C-bit 0 bit 0 C 1 bit 1 C bit C C C C C bit C. C. bit C+ C + bit bit C

Bytes 1 2 1 2 1 2 2 2 2 2 2 2

Instruction Cycles 1 1 1 1 1 1 1 1 1 1 1 2

Description (SP) ; addr 11 PC Addr11 PC Compare with A, jump (PC + rel) if not equal Compare with A, jump (PC + rel) if not equal Compare with Rn, jump (PC + rel) if not equal Compare with @Ri A, jump (PC + rel) if not equal Decrement Rn, jump if not zero Decrement (direct), jump if not zero Jump (PC + rel) if C bit = 1 Jump (PC + rel) if C bit = 0 Jump (PC + rel) if bit = 1 Jump (PC + rel) if bit = 0 Jump (PC + rel) if bit = 1 A+DPTR PC If A=0, jump to PC + rel If A 0 , jump to PC + rel PC + 2

Bytes 2 2 3 3 3 3 2 3 2 2 3 3 3 1 2 2

Instruction Cycles 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

LCALL addr16 LJMP addr 16 NOP RET RETI SJMP rel JMP @A+DPTR JZ rel JNZ rel NOP

PC + 3

(SP), addr16 PC Addr16 PC No operation (SP) PC (SP) PC, Enable Interrupt PC + 2 + rel PC A+DPTR PC If A = 0. jump PC+ rel If A 0, jump PC + rel No operation

3 3 1 1 1 2 1 2 2 1

2 2 1 2 2 2 2 2 2 1

Aim: Components/Software:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Atmel 89C51 microcontroller 8051 simulator- Win8051 Universal SP3 Programmer Win8051 Simulator and Software to load the code into Universal SP3 Programmer Computer System with Windows 98 or later operating system and RS-232 Cable +5V D.C Power Supply Analog to Digital converter (AD7574), Digital to Analog converter (DAC08) Resistors Capacitors 10 MHz crystal oscillator

To convert an analog signal to its digital equivalent and read the digital value from one port of AT89C51, write the same data on other port to convert it back to analog value.

11. Signal Generator and CRO

Description:

An analog signal is converted to 8-bit digital value using the ADC chip AD7574. After the conversion is complete, AD7574 will pin to high. As (connected to P3.1) pin goes high, chip select pin and read pin (connected to P3.0) are made low get valid digital data on to the bus (PORT1).The digital equivalent data is read from Port 1 and written back to Port 2. Digital d from port 2 is connected to DAC08 to convert it back to analog signal. As soon as data is read from the Port 1, P3.0 is set to s next conversion. Since analog output of DAC08 is an inverted one, an inverting amplifier (TL081CP) is employed to invert it ba and for the gain adjustment. The details of ICs used are given below.

AD7574:

1. 2. 3. 4. 5. 6. 7. 8-bit resolution Analog to digital converter Employs successive approximation technique Microprocessor compatible Conversion time 15 sec Analog input can vary in between 0 to |-Vref| 8-bit Digital to Analog converter 85 nsec settling time

DAC08:

TL081CP:
Operational amplifier (in present context operating as an inverting amplifier)

Procedure:

Write the assembly code in Win8051. Compile and simulate it. Once the code is error free, run it and check output with the Simulator After checking the code in the simulator, the code (file with .HEX extension) is loaded into Atmel 89C51 microcontro using Universal SP3 Programmer. Now connections are made as shown in the circuit diagram. Switch on the supply and push Reset button. Observe the results. Switch off the supply.

Assembly Code:

Observation:
Both analog signal input and analog output are of same shape with out any distortion with a sampling period of 15 sec.

Conclusion:

An analog signal is converted to digital equivalent using AD7574. Using AT89C51 the resultant digital data is read from a port a written to other port to convert it back to analog form using DAC08.

Fig 38.1 Circuit diagram for A/D and D/A interfacing with AT89C51

Observation

Microcontroller takes few microseconds to scan all 16 keys on the keypad whereas human response is of the order of millisecon Hence contact time of a key is long enough for it to be scanned by the microcontroller. Circuit Diagram

Fig 42.2 Circuit diagram for keypad interfacing

Aim
To interface LCD (Displaytech 162A) with PIC16F877microcontroller and to display "IITK" in the Liquid Crystal Display (LCD).

Components/Softwares
1. 2. 3. 4. 5. 6. MPLAB IDE (PIC microcontrollers simulator) PIC BURNER 3 with software to load the code LCD (Displaytech 162A) Computer System with Windows operating system and RS 232 cable PIC16F877 Microcontroller +5V D.C Power Supply 7. Resistors - 10K -1,50-1 8. Capacitors - 27 F-2 9. Potentiometers - 10K -1 10. 20MHz Crystal oscillator 11. SPST switches -1

Fig 43.1 A view of the PIC programmer connected to the PC serial Port (COM1)

Procedure
1. 2. 3. 4. 5.

Write the assembly code in MPLAB IDE simulator , compile it and check for errors Once the code was error free, run it and check the output in the simulator. After checking the code in the simulator, load the code (in .HEX format) into PIC16F877 microcontroller using P BURNER3. Make connections as shown in the circuit diagram. Switch on the power supply and observe "IITK" displayed in the LCD.

Conclusion
LCD was successfully interfaced with PIC16F877 microcontroller and displayed "IITK" in the LCD.

Assembly Code

Circuit Diagram

Fig 43.2 Circuit Diagram

Fig 43.3 Circuit assembly on breadboard

Liquid Crystal Display (LCD-Displaytech 162A )

LCD Displaytech 162A consists of a LCD panel, a controller IC (KS0070B) and a back light LED. The LCD module consists of to 16 pins in which, 2 are for power supply, 2 pins for Backlight LED, one pin for contrast adjustment, 3 pins are for control signals a 8 pins are data pins. In order to display any data, we need to do certain initiations. The following are the main three steps displaying any data in the LCD display. 1. Initializing LCD by sequence of instructions 2. Executing commands depending on our settings in the LCD 3. Writing data into the DRAM locations of LCD in the Standard Character Pattern of LCD

For doing above steps, refer the manual for LCD and follow the instructions and timing diagrams strictly.

MPLABIDE
MPLABIDE is a free software which can be downloaded from the website www.microchip.com Working with MPLABIDE : MPLABIDE is a simulator for PIC microcontrollers to write and edit the code in assembly language, compile it and also to run code. Output can be verified using simulator. Steps to Use MPLABIDE

After Installing the software MPLABIDEv7.2,open MPLABIDE. To built a new Project Project Project wizard Device 16F877 Location (Ex:C:\ProgramFiles\Microchip\MPASM <Project name>&<Project Directory>

project, Wizard New

open

Suite\MPASMWIN.EXE) Next

(Add file "f877tmpo.asm" which was located in programfiles microchip MPASMSuite Template Objec (Add file "16f877.lkr" which was located in programfiles microchip MPASMSuite LKR) Next Finish To have more clear refer to MPLABIDE help files. After building the project open the editor f877tmpo.asm and write the assembly code After writing the assembly code in the editor, build the project by clicking on the following option Project Build all Check for the errors in the output window View Output Once the error free code was made, simulate the code by following option Debugger Select Tool MPLAB SIM Simulator options are 1. Step into - Each time only one instruction will be executed (Single stepping mode) 2. Run - To run the whole code at once. 3. Animate - to animate the executing the code Additional things: 1. To view DRAM, program memory, SFRs, and External memory use the option VIEW 2. To set break points in the code (where simulation stops at that point). Debugger Breakpoints

To stop the simulation Debugger Halt After checking the code in the simulator, the code (file with .HEX extension) is loaded into 16F877 microcontroller using P BURNER 3.

PIC BURNER3
PIC BURNER3 can be used to program PIC microcontrollers. The steps to be followed to program the IC safely are as follows. 1. 2. 3. 4. Connect the PIC BURNER3 through RS232 Port to computer system with windows98 as operating system. Execute the file "icprog" which was in the software that comes with PIC BURNER3. Set the device as PIC16F877 Switch on the power supply of PIC BURNER3 Settings Hardware { JDM Programmer,Com1,Direct I/O}

5. 6. 7. 8. 9.

Settings Hardware check 1. on clicking "Enable Data out", Data in must be clicked automaticall 2. on clicking Enable MCLR, red LED on the PICBURNER3 must glow Settings Options Confirmation [ Erasing the devise,Code Protecting the Devise] Settings Options MISC Process Priority Normal

Settings Options Programming Verify After Programming. 10. Remaining options keep them at default settings. [Refer Manual of PICBURNER3 for detail] 11. Now insert the 16F877 microcontroller into the slot provided on the PICBURNER3 as the direction specified in the man of PICBURNER3. 12. load the .hex file File

13. Command 14. Command 15. 16. Command

open file Erase All Check

Blank Then there should be a notice on the window that "Device is Blank " Command Program All

Blank Check Then there should be a notice on the window that "Device is not blank at address 0x0000H".

17. Close the window, remove the IC from the PIC BURNER3 and switch off the power supply for PIC BURNER3.