EN 2012 Analog Electronics

Analog Laboratory Experiment: 2

DIFFERENTIAL AMPLIFIERS

Post-Laboratory Exercise


















Group: EE 9 Name: Karunarathna S.G.M.P.V
Group Members: W.A.I.S Kasthurirathn Admission No: 090246N
. Kaushala . A . H . K . Date of Exp: 14/10/2010
Date of Sub: 28/10/2010


01. BJT discrete differential amplifier.

1.1)
1.1.1 Voltage drop across D
4
& D
5
= 700 mV + 700 mV =1.4 V
V
BE
+ I
3
1K = 1.4V ( Assume that base current)
0.7 + I
3


1K = 1.4
I
3
=

mA
I
3
= 0.7 mA


1.1.2 Current through Q
1
is I
1
and Q2 is I
2

When no inputs are connected, above differential amplifier is symmetric. So,

I
1
= I
2
=

= 0.35 mA

I
1
= 0.35mA I
2
= 0.35mA

1.1.3 Collector Voltages of Q
1
is V
C1
and Q
2
is V
C2

Then,
V
C1
= V
C2
= 15V 0.35mA 33K
= 3.45 V

V
C1
= 3.45 V V
C2
= 3.45 V

1.1.4 Collector Emitter Voltages of Q
1
is V
CE1
and Q
2
is V
CE2
.
Due to the small base currents of the Q1 and Q2, the voltages of the V
CE

of Q1 and Q2 can be considered as the forward voltage drop of the BE
junction (0.7V).

V
CE1
= V
CE2
= 3.45 (-0.7) = 4.15V

V
CE1
= 4.15V V
CE2
= 4.15V

1.1.5 DC value at the Base of Q
1
is V
B1
and Q
2
is V
B2

v

mA
Small Signal
K
mA

K mv

V
B1
= -25.67mV V
B2
= -25.67mV



1.2)

In our calculations we assumed that the circuit is symmetric. But due to the
differences in resistors in the circuit, the symmetricity will be changed. Further
the diode forward voltage drop is not exactly 0.7V. So the practical values may
differ.


02. Amplification


2.1 Absolute gain =

=




= 82.6

Decibel Gain = log

= 39.34 dB


2.2
Since the biased voltage of the transistor is about 25.67mV and a signal with
DC offset other than the above value would change the Q point of the
transistor. Therefore it is important to only pass the AC variation of the signal.


03. Frequency Response of the Differential Amplifier

3.1)

Frequency(f)
Hz
Input (pk - pk)
mV
Output (pk - pk)
V
Voltage
gain
Log
10
( f )

50 50.4 4.36 86.51 1.70
100 50.7 4.22 83.23 2.00
1K 50.3 4.16 82.70 3.00
10K 50.1 3.34 66.67 4.00
100K 50.2 0.56 11.16 5.00
500K 50.4 0.20 3.97 5.67
1M 50.3 0.16 3.18 6.00









4. Common Mode Rejection Ratio

4.1)
Common mode rejection ratio is the ratio between the differential mode gain (the
ratio between the output voltage and the difference of the voltage levels of the
two inputs.) and the common mode gain (that is the output of the amplifier when
both inputs are fed with the same signal)
This measures the tendency for the amplifier to reject the input signal common to
both inputs.

4.2)

log

Frequency
Hz
Input (pk-pk)
mV
Output
(pk-pk)
m V
Common
made gain
A
C

Differential
Made gain
A
D

CMRR
dB
50 100 2.44 0.0244
100 100 2.44 0.0244
1K 100 2.64 0.0264
10K 100 2.97 0.0297
100K 100 5.76 0.0576
500K 100 6.08 0.0608
1M 100 6.58 0.0658
0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 4 5 6 7
V gain
V gain
Log (f)

5. Differential Mode and Common Mode Input Resistance

5.1) V
S
V
IN
= I
IN
R
IN

I

= k


5.2) I

= k


6. Simple Differential Mode Pre- Amplifier
ain of the simple uiffeiential moue pie ampliiei
v