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Simulation Symmetric N-dimensional Cube Network-on-Chip Architecture by Using Ns-2

Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

Abstract The symmetric recursive structure of the network-on-chip architecture has played an important role in developing parallel processing and is still popular and influential. The symmetric recursive structure of the hypercube support various elegant and efficient parallel algorithms that often serve as starting points for developing, or benchmarks for evaluating, algorithms on other architectures. This paper describes the design and simulation N-dimensional network-on-chip by recursive structure. We use network simulator NS-2 modeling and simulating NoC at high-level chip design and the different dimensions 2 to 6 (2D to 6D) has simulated. Index TermsNetwork-on-Chip (NoC), network simulator NS-2, cube-connected cycles (CCC), recursive structure, hypercube.

1 INTRODUCTION

oore's law predicts that by 2008, it will be possible to integrate over a billion transistors on a single chip. Current core based on SOC methodologies will not respond to the needs of the billion transistor era. Network on Chip (NOC), a new chip design paradigm concurrently proposed by many research groups[1],[2],[3] is expected to be an important architectural choice for future SOCs. The proposed NOC architectures offer a general but fixed communication platform which can be reused for a large number of SOC designs. Technology scaling is causing the energy consumption of the on-chip network to become increasingly important design criteria. The goal of macro networks is to maximize performance without regard for energy consumption, especially for large scale parallel computers where throughput and latency are of primary importance. It therefore stands to reason that a straightforward adaptation of macro network implementations for network-onchip is not appropriate. The problem faced by chip designers is that the design criteria run contrary to one another: Minimizing the energy consumption and maximizing performance are usually conflicting goals. Increased reliability usually means higher complexity, which results in larger area, degraded performance, and higher energy consumption. Therefore, designing a NoC interconnect requires searching through a vast multidimensional design space. There are many design parameters that can affect system performance and cost, but the design decision that has the largest impact is the choice of topology. The remainder of this section will briefly discuss the basic network topologies that other topologies are derived from. [4] Chip integration has reached a stage where a complete system can be placed on a single chip. The integration has

been made possible because of the rapid developments in the field of VLSI design. These chips, commonly termed as System on a chip (SoC), are primarily used in embedded systems. While designing an SoC, a vendor may use a library of cores designed by external designers in addition to using cores from in-house libraries. Cores are basically predesigned models of complex functions termed as Intellectual Property Blocks (IP Blocks), Virtual Components (VC) or simply micros. One key issue in the SoC design is heterogeneity; components of various vendors with significantly distinct characteristics lie on the same chip, making the design process even more complex [5]. A NoC has been proposed as a viable alternative for the inefficient buses of todays SoCs. A NoC is viewed as a collection of computational resources connected through a network where they communicate using packets. [6]

2 RECURSIVE STRUCTURE
Let S be a structure. Then: (a) S is called a recursive structure, if there is a representation of S, which admits a recursive extension, as well as a recursive right inverse operation over S, (b) S is called a strongly recursive structure, if there is a representation of S which is a recursive retraction over S. In these cases S is also called recursive via or strongly recursive via , respectively. By the following proposition = [ 1; ; n] is a recursive retraction over a natural structure S, if 1; ; n are. [7]

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3 NETWORK ARCHITECTURE
The NoC architecture is composed of tiles and communication links. Each tile consists of an intellectual property (IP) core, a network interface (NI), and a switch. The switches are interconnected by physical links. The network interface component decouples the core from the network. The switch implements the routing strategy needed to transmit data from one core to another. A common simplification is to combine all three components and to refer to them simply as a node (or tile) on the NoC.

3.1 Network Topologies

The network architecture, or topology, describes the physical organization of the interconnections network. A network topology can be classified as being either direct or indirect. A node in a network can be a terminal node, which acts as a source and sink for data, a switch that routes data, or both. In a direct network, every node acts as a terminal node. In an indirect network, a node is either a terminal or a switch node. A direct network can be redrawn as indirect by redrawing each node as two nodes and showing the switch and terminal nodes separately. Designers of large-scale SoCs must be aware of the advantages and disadvantages of each architecture in order to select an appropriate candidate for their implementations. The metrics that are of interest can be broadly categorized as [8]: Performance (latency, throughput, cross-section bandwidth), Energy consumption Reliability (error detection and/or correction) Scalability Implementation cost (area).

structed by iteratively adding dimensions. The twodimensional mesh can be constructed by connecting three 3-ary 1-meshes. Going one step further, a three dimensional mesh network, or cube, can be constructed by connecting three 3-ary 2-meshes, as shown in Figure 1. While it is tempting to use the three dimensional cube (and perhaps higher dimensioned tori/meshes) because of the high bisection bandwidth and increased path-diversity, one needs to consider some of the costs associated with such a topology. The higher degree switches will be larger due to an increased number of buffers and complexity, thus requiring more area and power. Furthermore, threedimensional topologies must be mapped onto a twodimensional surface for chip fabrication, and so the wiring complexity may result in longer wires and larger area requirements. For these reasons, lower dimensioned topologies that can be easily mapped to a two-dimensional space are largely preferred by the NoC research community. [14]

3.3 Cube-connected cycles (CCC) Topology

Fig.1. A 3-ary 3-mesh, or cube network, consisting of a total of 33 nodes.

3.2 Mesh and Torus Topologies

Many topologies have been proposed for NoCs including a 2D mesh [9], a fat tree [10], and a honeycomb [11]. However, most common proposals of all is a 2D mesh due to its simplicity and easiness in implementation. A torus is described as a k-ary n-cube, where n is the number of dimensions of the torus, k is the number of nodes in each dimension, and the total number of nodes is N = kn. The simplest torus topology is a single ring, or k-ary 1-cube, as shown in Figure 2.8a. The most well known example of a ring-based network topology is the token ring [12], which was developed in the late 1970s. Ring networks possess several characteristics that make them well suited for on-chip implementation [13]: They have regular physical arrangements that make them well suited for on-chip layout. At low dimensions, the physical wires between neighbouring switches are short, allowing high speed operation and low energy usage. For local communication patterns, they exhibit low latency and high throughput. Depending on the architecture, tori have high path diversity. Arbitrary dimensions of the torus and mesh can be con-

The original definition of cube-connected cycles (CCC) was based on a q-cube in which each node has been replaced with a cycle of length q, with the aim of reducing the node degree without significantly affecting the diameter. Figure 2 shows how a 3-cube is converted to a 24-node

Fig.2. Alternate derivation of CCC from a hypercube

CCC. Each node is replaced with a 3-cycle, with the original hypercube links distributed one per node in the cycle. Each node also has two cycle edges. The three edges of a node in CCC can be denoted as F: Forward link in the cycle

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B: Backward link in the cycle C: Intercycle or cube link Each node can be identified by a pair (x, y) of integers, where x is the cycle number (the node number in the original hypercube) and y is the node number within the cycle. The bisection bandwidth and path diversity of higher dimensioned topologies, such as the 3-ary 3-mesh shown in Figure 1, makes them ideal for interconnecting a large number of cores. However, the high node degree and wiring complexity makes them expensive in terms of area and power for on-chip implementation. The problem has to do with mapping a three (and higher) dimensional structure to a two-dimensional surface. The cube-connected cycles (CCC) [15] topology is a substitute for the nmesh network that uses interconnected rings to reproduce the structure of a higher dimensioned mesh while using switches of fixed node degree. Figure 2 shows an example of the CCC topology where multiple rings are connected such that a k-ary 3-mesh topology is reproduced. The CCC topology has the following properties [15]: The node degree of all switches is 3. Processing time is not significantly increased with respect to that achievable by the k-ary 3-mesh (3dimensional hypercube). The structure is more easily mapped to a twodimensional surface for on chip implementation. A directed cube-connected cycles DCCC topology [16] that uses unidirectional links has been shown to be even more layout efficient than the normal CCC topology. An express cube is a k-ary n-cube network augmented by express channels that reduce the path lengths for nonlocal messages [17]. The express channels can be inserted into an existing network without changing the implementation of the switches. Figure 3 shows a network that has been augmented by two levels of express channels, where the highest level bypasses the largest number of nodes. A hierarchical express cube has the locality of a torus and a diameter approaching that of a fully connected network [18]. The drawback of express channels is that the required number of channels increases with the dimension, leading to a larger area overhead associated with the extra routers and links. As special cases of m-ary q-cubes, hypercubes are also called binary q-cubes, or simply q-cubes, where q indicates the number of dimensions. We will use the term hypercube to refer to a generic architecture of this type and q-cube (particularly, 3-cube, 4-cube, and so forth) when the number of dimensions is relevant to the discussion. A q-dimensional binary hypercube (q-cube) is defined recursively as follows: A 1-cube consists of two nodes, labeled 0 and 1, with a link connecting them. A q-cube consists of two (q1)-cubes, with the nodes labeled by preceding the original Node labels of the two subcubes with 0 and 1, respectively, and connecting each node with the label 0x to the node

with the label 1x. The two (q 1)-cubes forming the q-cube are known as its 0 and 1 subcubes. If the label of a node x (its binary ID) is xq1 xq2 ... x2x1x0, then its q neighbors are xq1 xq2 ... x2 x1 x'0 neighbor along Dimension 0; denoted by N0(x) xq1 xq2 ... x2 x'1 x0 neighbor along Dimension 1 or N1(x) . .. x'q1 xq2 ... x2x1x0 neighbor along Dimension q1 or Nq1(x) In other words, the labels of any two neighboring nodes differ in exactly 1 bit. Two nodes whose labels differ in k bits (have a Hamming distance of k ) are connected by a shortest path of length k. Hypercubes are both node- and edge-symmetric, meaning that the roles of any two nodes (edges) can be interchanged with proper relabeling of the nodes. Swapping the leftmost 2 bits in every node label of a q-cube interchanges the roles of dimensions q-1 and q-2. As a result, 0 and 1 sub cubes can be defined for each of the q dimensions of a q-cube. Complementing a particular bit position in all node labels results in a relabeling of the nodes that switches the roles of the 0 and 1 sub cubes associated with that dimension A node label x can be transformed to a different node label y with k such complementation steps, where k is the Hamming distance between x and y. Similarly, swapping bit positions i and j in all node labels interchanges the roles of Dimension-i and Dimension-j links. Thus, the designations Dimension 0, Dimension 1, and so forth are arbitrary and no inherent order exists among the various dimensions. Hypercubes have many interesting topological properties, some of which will be explored in the remainder of this chapter and the end-of-chapter problems. The recursive structure of hypercubes makes them ideal for running recursive or divide-and-conquer type algorithms. The results of sub problems solved on the two (q1)dimensional subcubes of a q-cube can often be merged quickly in view of the one-to-one connectivity (matching) between the two subcubes. Multiple node-disjoint and edge-disjoint paths exist between many pairs of nodes in a hypercube, making it relatively easy to develop routing and other parallel algorithms that are tolerant of node or edge failures. A large MIMD-type hypercube machine can be shared by multiple applications, each of which uses a suitably sized subcube or partition.

3.4 PYRAMID
The pyramid architecture combines 2D mesh and tree connectivities in order to gain advantages from both schemes. Topologically, the pyramid inherits low logarithmic diameter from the tree and relatively wide bisection from the mesh. Algorithmically, features of each network can be utilized when convenient (e.g., fast semi group or prefix computation on the tree and efficient sorting or data permutation on the mesh). A pyramid network can be defined recursively. A single node is a one-level pyramid. The single node doubles as the pyramid's apex and its 11 base. An l -level pyramid

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consists of a 2l12l1 base mesh, with groups of four nodes, forming 22 submeshes on the base, connected to each node of the base of an ( l1)-level pyramid. The number of processors in an l-level pyramid is p = (22l 1)/3. From this expression, it is evident that roughly three-fourths of the processors belong to the base. It is thus not very wasteful of processors if we assume that only the base processors contain data and other processors are only used for data routing and various combining operations. This is similar to our assumption in Section 2.4 that only leaf nodes of tree architecture hold data elements. The diameter of an l-level pyramid is 2l2 and its maximum node degree is 9 for l4. The pyramid architecture is suitable for image-processing applications where the base holds the image data (one pixel or block of pixels per processor) and performs low-

6 RELATED WORKS
Several works have been investigating the 3D manufacturing processes [19], [20], [21]. Methods for 3D floorplanning and placement of cores, taking into account the thermal issues has been presented in [22]-[25]. Manufacturing of 3D interconnects has been addressed by [26] and [27]. Multi-dimensional regular topologies (like k-ary ncubes, hypercubes) have been explored by researchers as viable interconnect solutions for chip-to-chip networks [28]. However, such standard topologies are not suitable for application specific SoCs, which are heterogeneous in nature.

6 SIMULATION DETAILS
Networks on chips (NoCs) have been introduced as a remedy for the growing problems of current interconnects in VLSI chips. Being a relatively new domain in research, simulation tools for NoCs are scarce. To fill the gap, we use network simulator NS-2 for simulating NoCs, especially at high level chip design. The huge library of network elements along with its flexibility to accommodate customized designs, NS-2 becomes a viable choice for NoCs. We have used NS-2 to simulate our prototype of a fault tolerant protocol for NoCs. NS-2 is an open source, object-oriented and discrete event driven network simulator written in C++ and OTcl. Its a very common and widely used tool to simulate small and large area networks. Due to similarities between NoCs and networks, NS-2 has been a choice of many NoC researchers to simulate and observe the behavior of a NoC at a higher abstraction level of design. It has a huge variety of protocols and various topologies can be created with little effort. Moreover, customized protocols for NoCs can easily be incorporated into NS-2. The parameters for routers and links can easily be scaled down to reflect the real situation on a chip. Based on this fact, we have successfully simulated a hundred node 2D mesh based NoC using our reliable protocol for safe delivery of packets. As we will see in section 4 that we are not the only ones to use NS-2 for simulating a NoC.[29]

Fig. 4. Pyramid with three levels and 4 4 base along with its 2D layout..

level image operations that involve communication between nearby pixels. Processors in the upper layers of the pyramid deal with higher-level features and processes involving successively larger parts of the image.

6.1 MESHES OF TREES

The mesh of trees architecture represents another attempt at combining the advantages of tree and mesh structures. Like the pyramid, an l-level mesh of trees architecture has a 2l12ll base whose processors are the leaves of 2ll row trees and 2ll column trees. The number of processors in an l-level mesh of trees is p = 2l (322l2 1). From this expression, it is evident that roughly one-third of the processors belong to the base. The diameter of an llevel mesh of trees is 4l 4, its bisection width is 2l -1 , and its maximum node degree is 3. If the base processors are connected as a 2D mesh, the maximum node degree increases to 6. The ith row and ith column root nodes may be merged into a single node (increasing the node degree to 4) or interconnected by an extra link (preserving the maximum node degree of 3). Either modification increases the efficiency of some algorithms, One can also construct trees diagonally, in lieu of or in addition to row and/or column trees. The mesh of trees architecture has a recursive structure in the sense that removing the row and column root nodes, along with their associated links, yields four smaller meshes of trees networks. This property is useful in the design of recursive algorithms. A mesh of trees network with an mm base can be viewed as a switching network between m processors located at the row roots and m memory modules at the column roots.

3 SIMULATION RESULTS
We have simulated different network-on-chip topologies which they have recursive structure by using NS-2 simulator. Each of the topologies is simulated in different dimensional (2-D to 6-D). Figures of simulation and A part of the ns-2 script file about constructing the topology is shown below.

6.1 MESHES OF TREES

A part of the ns-2 script file about constructing the 2DCube topology is shown below: #Create nodes(switch) for {set x 0} {$x <= $num} {incr x} { for {set y 0} {$y <= $num} {incr y} { set sw([expr ($y*10+$x)]) [$ns node] $sw([expr ($y*10+$x)]) color blue }}

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#Create links between the switch-switch (dimension-x) for {set y 0} {$y <= $num} {incr y} { $ns duplex-link $sw([expr ($y*10+0)]) $sw([expr ($y*10+1)]) 1Mb 10ms DropTail } #Create links between the switch-switch (dimension-y) for {set x 0} {$x <= $num} {incr x} { $ns duplex-link $sw([expr (0*10+$x)]) $sw([expr (1*10+$x)]) 1Mb 10ms DropTail } Figure 5 shows the simulation of Network-on-chip by 2-Dimensional Cube topology by using NS-2.

$sw([expr ($z*100+$y*10+$x)]) color blue }}} Figure 6 shows the simulation of Network-on-chip by 3Dimensional Cube topology by using NS-2.

6.2 The NOC 3-Dimensional Cube topology

A part of the ns-2 script file about constructing the 3DCube topology is shown below: #Create nodes(switch)

Fig. 6. The NOC 2-Dimensional Cube topology

6.3 The NOC 4-Dimensional Cube topology

Some of the simulations in which the number of nodes is high may have a different view. For example Figures 7 and 8, show two different views of a 4D NOC which each of them consists of 16 nodes.

Fig. 5. The NOC 2-Dimensional Cube topology.

for {set x 0} {$x <= $num} {incr x} { for {set y 0} {$y <= $num} {incr y} { for {set z 0} {$z <= $num} {incr z} { set sw([expr ($z*100+$y*10+$x)]) [$ns node]

Fig. 7. the first type of 4d-Cube topology

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Fig.12. The second layout of 6D Cube topology. Fig. 8. the second presentation of 4d-Cube topology Fig. 10. The NOC 5-Dimensional Cube topology

6.4 The NOC 5-Dimensional Cube topology

In the the following figures a 5-dimensional Cube NOC are shown which consists of 32 nodes.

6.5 The NOC 6-Dimensional Cube topology

In the the following figures a 6-dimnsional Cube NOC are shown which consists of 64 nodes.

Fig. 11. the first layout of 6D Cube topology. Fig. 9. The NOC 5-Dimensional Cube topology.

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6 CONCLUSION
This paper presents the flexibility of ns-2 simulator so that there is no restriction on implementing various topologies in high dimensions. And also this paper shows arguments to effectively use NS-2 network simulator for simulating NoCs by Recursive structures. Our argument is that NS-2 is feasible candidates for simulating NoCs at a higher abstraction level since no specific NoC simulator exists so far. The in-built facilities of NS-2 can effectively facilitate in the design of new protocols for NoCs. The recursive structure of New Noc architectures makes them ideal for running recursive or divide-and-conquer type algorithms. There isn't any limitation for the simulation method and only the simulation time will be long.

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