Low Power High Speed Domino Logic based on Double Capacitive Body Biased Keeper

H.-T. Tung *, J.-P. Son, C.-R. Kim, N.-N. Wang. S.-W. Kim ASIC Design Lab, Department of Electrical and Computer Engineering, Korea University, 136-701, Seoul, Korea * Email: httung@asic.korea.ac.kr Abstract In this paper, a double capacitive body biased keeper (DCBBK) for domino logic gate is proposed. By using this technique, the threshold voltage of keeper transistor adapts to multi operating phase to reduce leakage power consumption and enhance speed compare to other techniques such as standard domino (SD) without body bias, dynamic body biased keeper (DBBK) and single capacitive body biased keeper (SCBBK). All the various body bias circuits are applied to a wide fan in OR domino gate for evaluating delay time, power consumption, power-delay product (PDP) and noise immunity. The simulation results for 0.18 um Hynix CMOS technology show that DCBBK reduces 44%, 20%, 9% in power compare to SD, DBBK, SCBBK while DBBK, SCBBK, DCBBK improve 46% in speed than SD gate. 1. Introduction The domino logic has great advantages in increasing speed and reducing implementation area, no static power consumption compare to static CMOS circuits [1], so that has been widely applied to large of high performance high speed system such as microprocessors with critical data-path, low clock delay distributed network, or synthesizing high speed digital system. However, the criterions of domino logic such as noise immunity, power consumption and operated speed are degraded by effects of charge leakage, charge sharing, capacitive coupling, and clock feed-through with very deep submicron CMOS technology [1] To overcome this problem, a PMOS keeper transistor is applied to guarantee the steady state of dynamic node in evaluation phase against noise and leakage effects [1]. The size of keeper must critically choose compare to size of pull-down transistor network, the domino logic with small size keeper can achieve low power, low delay dissipation but very poor noise immunity. As the result, there is a trade of between noise immunity and speed/energy efficient of domino logic. We overcome this problem by using adaptive body biased circuit based on modified double capacitive body biased keeper (DCBBK) to change threshold voltage of keeper correspond to clock signal. High threshold voltage keeper is used in pre-charge phase to reduce leakage current and also reduce leakage power consumption, while low threshold voltage keeper is used in evaluation phase to enhance speed of domino gate. Compare with other of body biased circuit such as SD, DBBK, and SCBBK our proposal consumes less than 44%, 20%, 9% of power but improve 46% in speed than SD. This paper is organized as follow. The structure of adaptive body biased keeper based on DCBBK is introduced and explained in section 2. In section 3, we simulate various body biases circuits with 16 inputs OR gate using Hynix 0.18 um CMOS technology for evaluating technical targets. Finally, we conclude advantages and drawbacks of proposal in section 4. 2. Double capacitive body biased keeper 2.1. Variable threshold voltage keeper We consider the effects of threshold voltage to gate delay, switching power, leakage energy [2] and the method to vary threshold voltage base on body techniques [1].

td =

Vdd

(Vdd

Von

out + d W ) in Win

W par

2 E switching = 0 1K e Wout + W par Vdd

Eleakage = norm dWin I 0 ( S in ) e Vth = Vth 0 +

(Vth Vdd )
V0

( 2 ) F

+ VSB

2 F

Vdd

Where, Von is directly proportional to Vth, Wout/Win is electrical fan-out of a gate, Wpar/Win is a measure of its intrinsic delay, is the probability of energy consuming transition at the output of the gate, KeWpar, is the self-loading and KeWout is the load capacitor. The other parameters are constants. Obviously, we can control threshold voltage dynamically to high/low value by applying reverse-body bias (VSB<0) or value forward-body bias (VSB>0) to obtain low/high leakage power dissipation, higher/lower delay, respectively. This is useful technique for very down scaling CMOS technologies with threshold voltage reduction.

1-4244-0161-5/06/$20.00 2006 IEEE

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2.2. Double capacitive body bias circuit The standard footed domino OR gate has structure in Figure 1. In pre-charge phase, clock is high so floating node is charge to Vdd by a pull-up transistor. The output voltage goes 0 logic, then keeper turn on to keep floating node in steady state. In evaluation phase, pull-up transistors turn off, output voltage is evaluated by state of pull-down transistors network. Then, the conventional circuit DBBK, SCBBK and our proposed DCBBK are shown in Figure 2.

Figure 1. Standard footed domino OR gate structure.

All of structure can provide high/low body biased voltage to keeper in low/high clock period. The DBBK circuit requires two supply voltage Vdd1 and Vdd2, so that has drawbacks such as consuming more power overhead and large implementation area [3]. The SCBBK needs only one supply voltage but can not achieve maximal body bias voltage, suppress noise immunity if clock is not ideal and inverter buffers size is not large enough,. Increasing inverter buffers size consumes more power for SCBBK. Furthermore, the value of capacitor must choose critically as twice of keeper bulk capacitance [4]. The DCBBK has two un-balanced capacitors in term of NMOS with size is choose easily to obtain appropriate capacitance value and maximum body bias value for high noise immunity. In the steady state, when _bCLK is low, the keepers body is charge to Vdd by two sources P6 and P7 as diode. Notice that, P6 and P7 are reverse body bias so their drop voltage quite small. And then, when the _bCLK is high, P6 and P7 turn off and keepers body becomes floating node and the charge from C21 makes keepers body increases to approximate 2Vdd. If we use un-balanced capacitors C21, C22 we can change the dynamic range of keepers body voltage. Totally, keepers body can change from Vdd to 2Vdd under clock controlling. The simulation waveform of all circuits is shown in Figure 3. The different phase Td between CLK signal and keepers body signal affect noise immunity, speed and power dissipation of domino logic gate. Higher Td decrease noise immunity, whereas less Td increase power, and delay.

Figure 2.a. Dynamic body bias keeper.

Figure 2.b. Single capacitive body bias keeper.

Figure 3. Waveforms of DBBK, SCBBK, DCBBK 3. Simulation results We apply all keeper body bias circuits for wide fain-in 16 inputs OR gate with enough large size footed transistor using 0.18 um Hynix process. The pull-down transistors have same size (1u/0.18um). The other same function transistors have minimum size (W/L=0.25um/0.18um), all the capacitors are in term of CMOS. The total size of CMOS capacitor C21 and C22 is equal to C11s size to obtain compact implementation

Figure 2.c. Double capacitive body bias keeper.

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area of DCBBK. The power dissipation, delay time, and power-delay product are evaluated in worst-case (only one input is connected to Vdd, the other inputs are connected to ground). For noise immunity evaluation, all the inputs of OR gate are connected to the same input noise signal in a DC analysis. These evaluations are considered with varying of KPDR, defined as width ratio of keeper and pull-down. The clock frequency, supply voltage, and load capacitor are 1.5V, 1GHz and 10fF, respectively. In the Figure 4, shows power dissipation, delay time, power-delay product and low noise margin (NML = VIL VOL [1] where VIL is the input voltage as dynamic node voltage is equal to input voltage in DC analysis, VOL is output low voltage) due to KPDR.

Figure 4.d. NML comparison With KPDR = 2.4, DCBBK consumes ~44 %, ~20%, ~9% power less than SD, DBBK and SCBBK, respectively. All of DBBK, SCBBK and DCBBK operate in 46% higher speed than SD. The performance at KPDR=2.4 is summarized in Table. 1 Table 1. Power, Delay, Power-Delay Product (PDP) and Low Noise Margin (NML) evaluation KPDR = 2.4 Delay Power PDP NML (ps) (uW) (fJ) (mV) 279 737 206 573 SD (100%) (100%) (100% (100%) 140 516 72 538 DBBK (-50%) (-30%) (-65%) (-6%) 150 456 69 539 SCBBK (-47%) (-38%) (-66%) (-6%) 148 415 61 538 DCBBK (-46%) (-44%) (-67%) (-6%) 4. Conclusions We proposed and investigated a double capacitive body biased keeper for domino logic. Based on this proposed scheme, the threshold voltage of keeper is changed for higher keepers size without increasing power, delay penalty and obtain higher noise immunity. The novel body biased circuit has one voltage supply, small area, non-critical for implementation, and provide maximum body biased voltage. In deep submicron technology, this circuit can be applied for low power, high speed, higher noise immunity, domino logic gate. Reference [1] J. M. Rabaey, et al, Digital Integrated Circuits ? A Design Perspectrve, Prentice Hall, , 2003 [2] R. W. Brodersen, et al, Methods for True Power Minimization, IEEE ICCAD 2002, Nov, 2003. [3] V. Kursun, et el, Domino Logic with Dynamic Body Biased Keeper, ESSCIRC, Sept, 2002. [4] A. Amirabadi, et al, Domino Logic with an Efficient Variable Threshod Voltage Keeper, ISCAS, May, 2005.

Figure 4.a. Power dissipation comparison

Figure 4.b. Delay comparison

Figure 4.c. Power-Delay product comparison

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