Short circuit dissipation in CMOS static circuits and its impact on buffer circuits

Introduction:- During the last years CMOS technology has become an important technology for designing of VLSI circuits. The most important reason for this is the low static power dissipation, due to the absence of dc currents when there is no signal transition. Static CMOS gates are very power efficient because they dissipate nearly zero power when idle. Earlier, the power consumption of CMOS devices was not the major concern while designing chips. Factors like speed and area dominated the design parameters. As the CMOS technology moved below sub-micron levels the power consumption per unit area of the chip has risen tremendously. The power dissipation in static CMOS circuits occurs due to dynamic current and static current components. The static current (off device) components includes subthreshold leakage current, gate leakage current (due to factors like thin gate oxide and power supply voltage) and source and drain junction leakage current (due to reverse biased p-n diodes formed at junctions). The static power dissipation is generally due to leakage currents so are unavoidable and depends on process parameters. The Dynamic current (on device characteristic) consists of average dynamic current component (when either pull-up or pull-down network is on) and short-circuit current(when both pull up and pull down are simultaneously on). The short circuit current leads to short circuit power dissipation which is dependent on various circuit parameters as will be discussed. Statement of Problem: - The paper deals with the impact of short circuit dissipation on Buffer circuits. In integrated circuits, it becomes necessary sometimes to drive high capacitances (eg. Bus lines, off chip circuits etc.), or high fan-out often at high clock frequencies. Such driving circuits are called buffers leads to a large part of the total power consumption of the chip. The optimization of these circuits is very important for improving circuit efficiency. One of the major optimization task is to obtain minimum power dissipation. As the short circuit dissipation takes place when both the pull-up and pull-down networks are on, i.e. only when the transition takes place, the duration is very small and thus leads to the consideration of rise and fall times of the circuit. The rise and fall times are closely related to capacitance if the circuit. Thus the above parameters will play an important role in analyzing the circuit. Study:- The above analysis is very important in VLSI design and circuit design field. Also in the field of circuit optimization, the research can also play an important role in circuit optimization study. The circuit optimization is very useful as the ultimate desire is to market a chip with minimum complexity and little constraints. The constraints include fan-in, fan-out, power dissipation, area, propagation delay, timing considerations etc. Out of all these mentioned, factors like power dissipation and propagation delay can be modelled and reviewed continuously to get desired performance. Talking in terms of power dissipation, the leakage power dissipation is hard to avoid due to limiting factors on process parameters but the dynamic power dependency on external parameters like capacitance makes it easy to remodel the device until the conditions are met. With the device length reaching in terms of nanometres, the task has become even harder as the power we are talking is in terms of microwatts. But as the number of chips increasing for a given circuit and also the functionality, it has

become even more important to fulfil all the desired tasks in a given time and power criteria. Methodology:- The methodology involves studying in detail the basic currentvoltage relationships of simple CMOS inverter and then extending the idea to buffer circuits and how these circuits can be designed with optimized power. Use of pspice software for analyzing and plotting of various results obtained by mathematical equations is done for easy interpretation and understanding of results the short circuit dissipation depends strongly on inverter design. The analysis starts by assuming a zero capacitance loads and then extends to larger load values. A static CMOS inverter does not dissipate power during the absence of transients on the inputs. During transition there is a time period in which both pmos and nmos conduct, causing a short circuit current to flow. If we load the inverter with a capacitance then it can be easily seen that sort circuit dissipation depends strongly on inverter design. Similarly the study is extended to string of inverters by using current equation for single inverter and then finding the results for multiple inverters. By varying various parameters in the inverter like supply voltage, supply frequency, threshold voltage, rise-time and fall-time, the effect of these can be observed on power dissipation. Outcomes: The various outcomes by varying circuit parameters in the currentvoltage equations are plotted and the results inferred. It is seen that the maximum short-circuit current occurs for a zero capacitive load inverter. As the capacitive load increases the short-circuit current decreases. The dissipation also depends on rise and fall time of the input signal. The results suggests that if the operation of the inverter is such that output and input signal have equal rise and fall times, the short circuit dissipation is only a fraction of total dissipation. But if there is a mismatch between output and input rise and fall times,the short circuit dissipation increases. The result of designing a string of inverters in such a way that input and output rise and fall times of each inverter are equal to obtain minimum dissipation can be applied to the design of static CMOS buffers. An expression is also derived for tapering factor between two successive inverters of such a string to minimize parasitic power dissipation. It is inferred that optimization in terms of power dissipation leads to a better overall performance than possible by minimization of propagation delay. Relevance:- The above research as mentioned is very relevant for circuit optimization and VLSI designing of circuits. The ongoing research for design of low-power circuits is initially based on the study of short circuit current dissipation. The design of buffer circuits as optimized by this papers work is very important for designing of complex circuits and for designing circuits having a large fan-out and high capacitive load. Similar studies can be done using simple current-voltage equations and varying circuit parameters by keeping secondary circuit conditions like narrow-channel effects,tunnelling,hot carrier effect, presence of coupling capacitors in mind. These phenomenon are usually neglected if device lengths are not too low. With the circuit channel length reaching to sub-microns these effects come into accounts. In future circuit can be further optimized by analyzing all the important factors, if physical parameters like temperature, pressure can be incorporated in the design equations. More accurate results can be found out leading to a much better design.